JPH07235547A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To avoid damage to the silicon surface of a semiconductor layer by a method wherein a polysilicon layer for solid-phase diffusion is opened without using a dry technique. CONSTITUTION:An insulating film is formed on a region to be formed with an opening part 19 of the surface of a semiconductor layer 11. A first silicon layer 16 is formed on the exposed silicon surface of the layer 11 by a selective epitaxial growth method and a second silicon layer is formed thereon by a CVD method. After the second silicon layer is opened so as to expose the head of the insulating film, the insulating film is removed by a wet technique to form the opening part 19. An external base region, an active base region and an emitter region are respectively formed by the solid=phase diffusion from the layer 16, through the part 19 and by the solid-phase diffusion from 50 emitter lead-out electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit capable of avoiding damage to a semiconductor surface due to etching.

[0002]

2. Description of the Related Art As a method for obtaining an extremely fine base-emitter junction, a method described in, for example, Japanese Patent Laid-Open No. 2-79436 is known. FIG. 6 shows the transistor structure. In the figure, 1 is a semiconductor layer which serves as a collector, and 2
Is a LOCOS oxide film for separating elements from each other, 3 is a P-type external base region, 4 is a P- type active base region, 5 is an N + type emitter region, 6 Is a base extraction electrode formed of a polysilicon layer for connection with the external base region 3, 7 is an emitter extraction electrode for connection with the emitter region 5, and 8 is a base extraction electrode 6 and an emitter extraction electrode. 7 is an insulating layer for insulating the same from each other, and 9 is a side wall insulating film for insulating the base lead-out electrode 6 and the emitter lead-out electrode 7.

The external base region 3 is a base lead electrode 6
By solid-phase diffusion, the active base region 4 is formed by ion implantation and diffusion through the opening of the base extraction electrode 6, and the emitter region 5 is formed by solid-phase diffusion from the emitter extraction electrode 7 provided in the opening. Done.
In order to form the opening of the base extraction electrode 6, usually, after depositing a polysilicon layer on the entire surface of the semiconductor layer 1,
The semiconductor layer 1 is etched by anisotropic dry etching to form an opening.

[0004]

However, a dry etching method is used for forming the opening because the line width of the opening is a submicron dimension. However, in the dry method, the silicon surface of the semiconductor layer 1 in the opening is formed. It has the drawback of causing considerable damage. Therefore, there is a drawback that the damage increases the leak current of the base-emitter junction.

[0005]

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and includes a step of leaving an insulating film in a region corresponding to an opening, and a first step for forming an external base region on a surface of a semiconductor layer. Step of selectively growing the silicon layer of
Forming a silicon layer, a step of removing the second silicon layer so as to expose the head of the insulating film, and a step of removing the insulating film by a wet method. And a method for manufacturing a semiconductor device in which damage to the silicon surface forming the emitter junction is eliminated.

[0006]

According to the present invention, since the opening is formed in the first silicon layer by removing the insulating film by the wet method, the silicon surface is not damaged by the dry method at all.

[0007]

EXAMPLE An example of the present invention will be described below. First,
An N-type semiconductor layer 11 serving as a collector is formed on the P-type semiconductor substrate by an epitaxial growth method to form the semiconductor layer 1
The surface of 1 is selectively oxidized to form a LOCOS oxide film 12 for element isolation. Reference numeral 13 is an N + type buried layer (FIG. 1A). Further, below the LOCOS oxide film 12, a P + type isolation region for separating the N type epitaxial layer from the PN junction is formed.

A CVD oxide film 14 is deposited on the entire surface (see FIG. 1).
B). The CDV oxide film 14 is photo-etched to leave the insulating film 15 on the surface of the semiconductor layer 11 where the diffusion of the emitter is planned (FIG. 1C). Since the insulating film 15 is also required to have fine processing accuracy, an anisotropic dry etching method is used. Naturally, the silicon surface of the semiconductor layer 11 remains damaged, but since this region is not a region forming the active portion of the base-emitter junction, it does not affect the transistor characteristics.

The semiconductor layer 11 not covered with the insulating film 15
A polysilicon layer is formed on the surface by a selective epitaxial growth method to form a first silicon layer 16 (FIG. 2).
A). In the selective epitaxial growth method, since the silicon layer grows only in the portion where the surface of the silicon single crystal is exposed, the silicon layer can be formed except for the LOCOS oxide film 12 and the insulating film 15. After that, boron is ion-implanted into the entire surface without a mask to dope the impurity for external base diffusion into the first silicon layer 16.

An amorphous silicon layer is deposited on the entire surface by LPCVD to form a second silicon layer 17 (FIG. 2).
B). Then, boron for giving conductivity to the second silicon layer 17 is masklessly ion-implanted. The second silicon layer 17 is photoetched to form a base lead electrode 18 with the first and second silicon layers 16 and 17. At the same time, the insulating film 15 is opened to expose the head of the insulating film 15 (FIG. 2C). First with respect to the etchant (dry) of amorphous silicon that forms the base extraction electrode 18.
Forming the silicon layer 16 and the insulating film 15
The silicon oxide film forming the film has relatively good selectivity.

The insulating film 15 is removed by a hydrofluoric acid-based etchant to form an opening 19 to expose the surface of the semiconductor layer 11 (FIG. 3A). Since the etching rate of the silicon oxide film is higher than that of the etching rate of amorphous silicon, the insulating layer Can be selectively removed. The whole is thermally oxidized to form a thermal oxide film 20 on the surface of the semiconductor layer 11 and the surfaces of the first and second silicon layers 16 and 17 (FIG. 3B). At the same time, the external base region 21 is formed from the first silicon layer 16 by solid phase diffusion.

Boron for forming an active base is ion-implanted into the surface of the semiconductor layer in the opening 19 through the thermal oxide film 20 without a mask (FIG. 3C). A polysilicon layer is deposited on the entire surface and anisotropically dry-etched to form a spacer 22 on the side wall of the opening 19 (FIG. 4).
A). HTO (High temperature)
re oxide) 23 is formed (FIG. 4B).

The HTO 23 is etched back to form the opening 1
The surface of the semiconductor layer 11 of No. 9 is exposed again (FIG. 4C). CV
A polysilicon layer is deposited by the D method, impurities for diffusion of the emitter are doped, and this is photoetched to form an emitter extraction electrode 24 in the opening 19 (FIG. 5).
A).

Then, the entire substrate is heat-treated to diffuse the previously implanted ions to diffuse the active base region 2.
5 is formed, and at the same time, the emitter region 26 is formed by solid phase diffusion from the emitter extraction electrode 24 (FIG. 4B).
The diffusion depth of the emitter region 26 is about 0.5 μ. Since the emitter region 26 is formed further inside from the side wall of the opening 19 by the spacer 22, the base-emitter junction does not reach the surface of the semiconductor layer 11 which is damaged by the dry etching of the insulating film 15. Therefore, it is possible to obtain a good PN junction with no leakage or the like.

In the above-described manufacturing method of the present invention, since the opening 19 is formed by the wet method, the semiconductor layer 11 is formed.
There is no treatment that damages the silicon surface. Therefore, it is possible to manufacture a high-frequency transistor finely processed by self-alignment while keeping the PN junction of the base-emitter junction in a good state.

[0016]

As described above, according to the present invention, the opening 19 necessary for self-alignment is formed by the wet method, so that the silicon surface of the semiconductor layer 11 is not damaged and the finely processed high frequency wave is not generated. It has the advantage that a transistor can be manufactured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a sectional view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining a conventional example.

Claims (2)

[Claims] 1. A step of forming an insulating film covering a part of the surface of the semiconductor region on the surface of the semiconductor region serving as a collector, wherein the surface of the semiconductor region adjacent to the insulating film contains impurities for forming an external base. Forming a first silicon layer, forming a second silicon layer on the insulating film and the first polycrystalline silicon layer, and forming a second silicon layer on top of the insulating film. Removing the insulating film to expose the surface of the semiconductor region, forming a side spacer on the sidewall of the opening from which the insulating film has been removed, and the opening. And a step of forming a polycrystalline silicon layer for emitter diffusion in the semiconductor integrated circuit. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the formation of the first silicon layer is performed by selective epitaxial growth.