JP3193736B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a so-called SOI type bipolar transistor.

With the improvement in SOI substrate manufacturing technology, the active portion of silicon on an oxide film is gradually thinned, and a submicron active portion is also possible. By using such a thin silicon film, a MOS transistor having a high gm and capable of suppressing a short channel effect can be formed.

However, in order to improve the load driving capability, it is desired that a bipolar transistor can be formed. A normal bipolar transistor is a vertical bipolar transistor that allows current to flow in the vertical direction.

However, the vertical bipolar transistor structure requires a large number of manufacturing steps and requires the formation of a subcollector buried layer. In an SOI structure, it is not easy to form a submicron collector buried layer.

[0005]

2. Description of the Related Art In a conventional lateral bipolar transistor, for example, a pair of n-type semiconductor regions are diffused from the upper surface of a p-type semiconductor layer to function as emitter / collector regions.

According to such a configuration, the width of the base region is non-uniform in the depth direction, and can be increased only in comparison with the vertical structure, which is a major obstacle to high speed operation.

[0007]

As described above, in the lateral bipolar transistor according to the prior art, the width of the base region cannot be reduced uniformly, and there is an obstacle in increasing the speed.

An object of the present invention is to provide a semiconductor device including a lateral bipolar transistor having a thin base region width and capable of operating at high speed.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A first conductivity type single crystal semiconductor layer which is disposed on the insulating substrate and has a substantially vertical first side surface, and covers a region of the first conductivity type single crystal semiconductor layer other than the first side surface; An insulating mask, a first semiconductor layer covering at least a part of the first side surface of the first conductivity type single crystal semiconductor layer and at least a part of the insulating mask, and a surface of the first semiconductor layer. A second semiconductor layer covering the first semiconductor layer, wherein the first semiconductor layer is formed in contact with the first side surface and has a second conductivity type opposite to the first conductivity type.
A single-crystal semiconductor base layer having a conductivity type of, a first conductivity-type single-crystal semiconductor emitter layer formed by penetrating into the single-crystal semiconductor base layer, and a layer continuous with the semiconductor emitter layer; A first conductivity type polycrystalline semiconductor layer formed on a partial region of the insulating mask;
The second semiconductor layer includes a second first conductivity type polycrystalline semiconductor layer formed in contact with the single crystal emitter layer and the first first conductivity type polycrystalline semiconductor layer.

[0010]

A substantially vertical side surface is formed on a single crystal semiconductor layer disposed on an insulating substrate, and a base region and an emitter region are formed from the vertical side surface by impurity diffusion, epitaxial growth, or other methods. be able to.

The base region thus formed can reproduce an extremely thin base width with good controllability.

[0012]

FIG. 1 is a sectional view showing a semiconductor device according to a reference example of the present invention. Formed of an insulator such as SiO ₂ ,
Or an insulating substrate 1 provided with an insulating layer such as SiO ₂ on the surface.
A single-crystal semiconductor layer 12 such as n-type single-crystal silicon
Is arranged.

In this structure, the n-type single crystal silicon semiconductor layer 12 forms an n-type collector region. The single-crystal semiconductor layer 12 has a side surface 12 a formed substantially vertically on the insulating substrate 11. P-type base region 14 is formed by impurity diffusion from this side surface.

After the formation of p-type base region 14, an n ⁺ -type polycrystalline silicon region 17 containing a large amount of n-type impurities is formed in contact with side surface 12a. The impurity diffusion from n ⁺ -type polycrystalline silicon region 17 forms a shallow n ⁺ -type emitter region 13 in single crystal semiconductor layer 12.

That is, the base region and the emitter region of the lateral transistor are formed by double diffusion from a solid phase. Note that on the single crystal semiconductor layer 12,
A p ⁺ -type polysilicon region 19 is formed separated from the n ⁺ -type polysilicon region by an oxide sidewall 23. This p ⁺ -type polycrystalline silicon region 19
A p ⁺ -type external base region 15 is formed by impurity diffusion from, and is connected to the p-type base region 14 described above.

At the other end of single crystal semiconductor layer 12, an n ⁺ -type polycrystalline silicon region 18 is formed on the exposed surface.
Is deposited, and n ⁺ -type collector ohmic region 16 is formed on the surface of single crystal semiconductor layer 12 by impurity diffusion from n ⁺ -type polycrystalline silicon region 18. Metal electrodes 25 such as aluminum are formed on the polycrystalline silicon regions 17 and 18, respectively, and are electrically connected.

In this specification, “polycrystalline silicon” includes amorphous silicon. With such a configuration, a lateral transistor having high performance similar to a vertical transistor is realized.

FIG. 2 shows the base regions 14, 1 of the configuration of FIG.
5 will be described. As shown in FIG. 2A, an n-type silicon single crystal semiconductor layer 1 is formed on an insulating substrate 11.
2 are formed. This n-type silicon single crystal semiconductor layer 1
2 is selectively covered with an insulating layer 21. P ⁺ extending from the surface of the insulating layer 21 and reaching the surface of the single crystal semiconductor layer 12
Form polycrystalline silicon region 19 is formed. This polycrystalline silicon region 19 is formed by first depositing polycrystalline silicon,
The impurity may be doped, or polycrystalline silicon doped with the impurity may be deposited.

On the polycrystalline silicon region 19, SiO ₂
And the like, a mask is formed with a photoresist thereon, and the insulating layer 22 and the polycrystalline silicon region 19 are patterned by photolithography.

Next, as shown in FIG. 2B, an insulating layer 23 such as an oxide film is deposited on the surface, and then the insulating layer 23 is deposited on the plane by anisotropic etching such as reactive ion etching (RIE). Remove the layer. Then, only the insulating layer 23 formed on the side wall remains. The polysilicon region 19 is covered by the insulating layer 23 on the side wall.

Next, as shown in FIG. 2C, the lower single crystal semiconductor layer 12 is selectively etched using the insulating layer 23 on the side wall as a mask. This selective etching is also performed by anisotropic etching such as reactive ion etching (RIE). Therefore, the single crystal semiconductor layer 12 has a substantially vertical side surface 12 a on the surface of the insulating substrate 11.

Next, as shown in FIG. 2D, a layer 27 of borosilicate glass (BSG) containing boron (B) is formed so as to cover the exposed side surface 12a of the single crystal semiconductor layer 12.
Is deposited.

P ⁺ -type polysilicon region 19 and B
By diffusing a p-type impurity from the SG film 27 into the single crystal semiconductor layer 12, ap ⁺ -type external base region 15 is formed on the surface and a p-type internal base region 14 is formed on the side surface. P-type internal base region 14 has a constant width in the lateral direction from side surface 12a, and is connected to p ⁺ -type external base region 15 at the upper portion.

FIG. 3 is a sectional view showing how the emitter region and the collector region of the semiconductor device shown in FIG. 1 are formed. As shown in FIG. 3A, after forming the internal base region 14 and the external base region 15, the BSG constituting the impurity source is removed, and the opening 2 for the collector region is formed in the insulating layer 21.
1a is provided.

Thereafter, as shown in FIG. 3B, a polycrystalline silicon layer containing a large amount of n-type impurities is deposited on the entire surface and patterned to form n ⁺ -type polycrystalline silicon regions 17 and 18 having a desired shape. obtain. Polycrystalline silicon region 17
Are arranged in contact with the vertical side surface 12a of the single crystal semiconductor layer 12, and constitute a polycrystalline emitter region.

The n ⁺ -type polycrystalline silicon region 18
Arranged in contact with single crystal semiconductor layer 12 exposed at opening 21a of insulating layer 21 to form a polycrystalline collector region. Impurities diffuse from these regions to form single-crystal emitter region 13 and single-crystal collector region 16, respectively.

In the bipolar transistor as shown in FIG. 1, an important parameter that determines the operation speed is the width of the base region 14. In the illustrated configuration, the width of the base region 14 is determined by the width of the impurity diffusion from the BSG film 27 deposited in FIG. 2D and the width of the impurity diffusion from the n ⁺ polycrystalline silicon region 17 deposited next. Is determined by the difference between Since these widths can be controlled thinly and with high precision by controlling the temperature and time of the diffusion process,
A high-speed bipolar transistor can be configured.

For example, a lateral bipolar transistor having a base width of 0.1 μm or less can be formed.
In the configuration of FIG. 1, the collector ohmic region 16
Was formed on the surface of the single crystal semiconductor layer 12, and the transistor structure was somewhat asymmetric.

FIG. 4 shows a reference example in which the transistor structure is configured more symmetrically. Compared with the configuration of FIG. 1, the single crystal semiconductor region 30 is patterned not only on the right side but also on the left side in the figure in a self-aligned manner according to the oxide film sidewall 23 to form side surfaces 30a and 30b.

An n ⁺ -type polycrystalline silicon region 18a is deposited on the left side surface 30b, and an n ⁺ -type collector ohmic region 16 is formed by impurity diffusion therefrom.

The collector ohmic region 16 on the side surface 30b is arranged in a shape facing the emitter region 13 on the other side surface 30a, and the symmetry of the transistor structure is improved. Therefore, in the bipolar transistor shown in FIG. 4, almost the entire thickness of single crystal semiconductor region 30 is effectively used.

FIG. 5 shows a manufacturing method for producing the device of the reference example of FIG. As shown in FIG. 5A, after a polycrystalline semiconductor layer 19a, an insulating layer 22, and an oxide sidewall 23 are formed over the single crystal semiconductor layer 30, the single crystal semiconductor layer 30 is formed using the sidewall 23 as a mask. Is anisotropically etched by RIE or the like and patterned. Thus, the side surface 30 is formed on the single crystal semiconductor layer 30.
a and 30b are formed.

Here, the process shown in FIG.
After forming the p-type base region by diffusion from G, the side wall 30b shown on the left side in the figure may be formed to obtain the structure of FIG.

The structure shown in FIG. 5A may be formed first, a p-type impurity diffusion source such as BSG may be formed on the side wall 30a shown on the right side of the figure, and a p-type base region may be formed by performing a diffusion process. .
Next, the side surfaces 30a, 30 of the exposed single crystal semiconductor layer 30
depositing an n ⁺ -type polycrystalline semiconductor layer so as to contact
By patterning, a polycrystalline semiconductor emitter layer 17 and a polycrystalline semiconductor collector layer 18 are obtained. These n-type polycrystalline semiconductor layers 17 and 18 (and p-type polycrystalline semiconductor layer 19)
The single crystal semiconductor layer 3 by diffusing impurities from
0, n ⁺ type emitter region 13, p type base region 14,
The p ^{+ type} external base region 15 and the n ⁺ type collector region 16 can be formed.

In this way, a configuration as shown in FIG. 4 can be created. FIG. 6 shows another manufacturing method for making the device of the reference example of FIG. In this manufacturing method, first, FIG.
After the polycrystalline semiconductor layer 19a, the insulating layer 22, and the oxide sidewall 23 are formed on the single crystal semiconductor layer 30 by the method described in (A), the single crystal semiconductor layer 30 is subjected to RIE using the sidewall 23 as a mask. Etching and patterning are performed by anisotropic etching.

Thus, the side surfaces 30a and 30b are formed in the single crystal semiconductor layer 30 as shown in FIG. Up to this point, the method is the same as the method in FIG. Next, FIG.
As shown in (A), a polycrystalline semiconductor layer is deposited on the entire surface,
After forming the resist mask, patterning is performed to form polycrystalline semiconductor layers 41 and 42. Thereafter, the polycrystalline semiconductor layer 42
A resist mask 43 is formed so as to expose only a portion, and a p-type impurity is implanted into polycrystalline semiconductor layer 42 and then heat treatment is performed.

Thus, the side surface 3 of the single crystal semiconductor layer 30
A p-type impurity is diffused from 0 a to form a p-type base region 14 in the single crystal semiconductor layer 30. By diffusing impurities from p-type polycrystalline semiconductor layer 19, p ⁺ -type external base region 15 is formed in single-crystal semiconductor layer 30.

Next, the resist mask 43 is removed, and FIG.
As shown in (B), heat treatment is performed after n-type impurities are implanted into the polycrystalline semiconductor layers 41 and 42. Thereby, n-type impurities are diffused from both side surfaces 30 a and 30 b of single-crystal semiconductor layer 30, and n ⁺ -type emitter region 13 is formed in single-crystal semiconductor layer 30.
And an n ⁺ -type collector region 16 is formed.

Thus, the impurity distribution of the transistor is formed. The polycrystalline semiconductor layers 41 and 42 become an n ⁺ -type polycrystalline semiconductor collector layer 41 and an n ⁺ -type polycrystalline semiconductor emitter layer 42, respectively. Further, the metal electrode 25
Is formed to form an apparatus having the configuration shown in FIG.

In the manufacturing method of FIG. 6, the base region and the emitter region can be formed by double solid phase diffusion from the same polycrystalline semiconductor layer 42, so that a thin base region can be formed. Further, the base region formed by diffusion from the emitter region side generates a drift electric field in the base region and transports carriers at high speed. For this reason, higher-speed operation becomes possible.

FIG. 7 shows a semiconductor device in which a base region is formed by epitaxy growth. On the insulating substrate 11,
A single-crystal semiconductor layer 30 such as n-type single-crystal silicon in which an n ⁺ -type region 16 is selectively formed is arranged.

This semiconductor layer 30 of n-type single crystal silicon
Constitutes an n-type collector region. n ⁺The mold area 16 is
Form a rectohmic region. This single crystal semiconductor layer
30 is a side surface 3 formed substantially vertically on the insulating substrate 11.
0a. Epitaxy growth from this aspect
Thus, a p-type base region 14 is formed. Also, p-type
After forming the base region 14, the shallow n⁺Type emitter region 13
Are formed.

FIG. 8 shows a manufacturing method for making the device of the embodiment of FIG. As shown in FIG. 8A, after a polycrystalline semiconductor layer 19a, an insulating layer 22, and an oxide sidewall 23 are formed over a single crystal semiconductor layer 30, the single crystal semiconductor layer 30 is formed using the sidewall 23 as a mask. Is anisotropically etched by RIE or the like and patterned.

As described above, the side surfaces 30 a and 30 b are formed on the single crystal semiconductor layer 30. However, the n ⁺ -type collector ohmic region 16 is formed in the single-crystal semiconductor layer 30 in advance by a known method such as ion implantation using a mask.

Next, as shown in FIG. 8B, a single crystal semiconductor is epitaxially grown while introducing a p-type impurity. At this time, a p-type single-crystal semiconductor grows on the exposed side surfaces 30a and 30b of the single-crystal semiconductor layer 30, and a p-type polycrystalline region grows on the insulator.

That is, the p-type base region 14 is formed on the side surface 30a, and the p-type polycrystalline semiconductor layer 50 grows on the insulating layer 22 and the sidewalls 23. Next, FIG.
As shown in (C), a polycrystalline semiconductor is further deposited to form a polycrystalline semiconductor layer 51, the right side in the figure is covered with a mask, and the exposed polycrystalline semiconductor layers 50, 51 and n ⁺ The p-type single crystal region on the mold region 16 is selectively etched and removed.

Further, as shown in FIG. 8D, an n-type impurity is implanted into the polycrystalline semiconductor layers 50 and 51 and heat treatment is performed. At this time, the p-type polycrystalline semiconductor layer 50 formed in FIG.

Generally, impurity diffusion in polycrystal is much faster than in single crystal. Since the p-type base region 14 formed on the exposed side surface 30a of the single-crystal semiconductor layer 30 is a single crystal, the heat treatment at this time does not completely compensate for the n-type. This utilizes the difference between the diffusion coefficients of impurities in the polycrystalline semiconductor and the single crystal semiconductor.

An n ⁺ -type emitter region 13 is formed in the p-type base region 14 by implanting an n-type impurity. Also, p
By diffusing impurities from type polycrystalline semiconductor layer 19a, p ^{+ type} external base region 1 is formed in single crystal semiconductor layer 30.
5 is formed. Further, a metal electrode 25 is formed to
Is created.

In the transistor thus formed, the base region is grown by epitaxy, so that the distribution of impurities can be made box-like. Therefore, when a thin base is formed, it is more resistant to punch-through than that formed by another forming method (for example, diffusion or implantation).

In each of the above-described reference examples and embodiments, the lateral dimension of the single crystal semiconductor layer 12 or 30 can be changed according to conditions such as withstand voltage.
Although the description has been given of the case of the npn transistor, the pnp transistor can be formed by inverting the conductivity type. In this case, PSG can be used as an n-type impurity source, and As or the like can be used as an n-type impurity to be doped into polycrystal. In addition, boron or the like is used as the p-type impurity doped into the polycrystal.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0053]

As described above, according to the present invention,
Using the SOI substrate, a lateral bipolar transistor with high controllability of the base region can be provided.

A high-speed integrated circuit device capable of high-speed operation is provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a reference example of the present invention.

FIG. 2 is a cross-sectional view showing a step of forming a base region of the semiconductor device shown in FIG. 2A to 2D show cross-sectional configurations during a manufacturing process of forming a base region.

3 is a cross-sectional view showing a step of forming a collector region of the semiconductor device shown in FIG. 3A and 3B show cross-sectional configurations of a manufacturing process for forming a collector region, respectively.

FIG. 4 is a sectional view of a semiconductor device according to another reference example of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing method for manufacturing the semiconductor device shown in FIG. FIG. 5 (A), (B)
Shows cross-sectional structures in steps for forming an emitter region and a collector region, respectively.

FIG. 6 is a cross-sectional view for explaining another manufacturing method for manufacturing the semiconductor device shown in FIG. FIG. 5 (A),
(B) shows a cross-sectional structure in a process for forming a base region, an emitter region, and a collector region, respectively.

FIG. 7 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining another manufacturing method for manufacturing the semiconductor device shown in FIG. 7; FIG. 8 (A)-
(D) shows the cross-sectional configuration during the manufacturing process of forming the base region and the emitter region, respectively.

[Explanation of symbols]

Reference Signs List 11 Insulating substrate 12, 30 Single-crystal semiconductor layer (n-type collector region) 13 n ⁺ -type emitter region 14 p-type internal base region 15 p ⁺ -type external base region 16 n ⁺ -type collector ohmic region 17, 18 n ⁺ -type polycrystalline Silicon region 19 p ⁺ -type polycrystalline silicon region 21, 22, 23 Insulating layer 25 Metal electrode

Claims (2)

(57) [Claims] A first vertically arranged first substrate disposed on an insulating substrate;
A first conductivity type single crystal semiconductor layer having a side surface;
An insulating mask covering a region other than the first side surface on the conductive type single crystal semiconductor layer; and at least on the first side surface of the first conductive type single crystal semiconductor layer and on the insulating mask. A first semiconductor layer covering a partial region; and a second semiconductor layer covering the first semiconductor layer, wherein the first semiconductor layer is formed in contact with the first side surface, A single crystal semiconductor base layer having a second conductivity type opposite to the first conductivity type, a first conductivity type single crystal semiconductor emitter layer formed by penetrating into the single crystal semiconductor base layer, and the semiconductor emitter layer And a first continuous-conductivity-type polycrystalline semiconductor layer formed on a partial region of the insulating mask. The second semiconductor layer is a single-crystal emitter layer. And the first first conductivity type polycrystalline semiconductor layer. A semiconductor device including a second first conductivity type polycrystalline semiconductor layer. 2. A method for manufacturing a semiconductor device according to claim 1, wherein a mask is formed on a single-crystal semiconductor layer of a first conductivity type disposed on an insulating substrate. Selectively anisotropically etching the crystalline semiconductor layer to form side surfaces of the single crystal semiconductor layer substantially perpendicular to the surface of the insulating substrate; and forming a second conductive type opposite to the first conductive type. By growing the single crystal semiconductor layer epitaxially while introducing impurities, a second conductivity type single crystal semiconductor base layer is formed on the side surface in contact with the side surface exposed by the anisotropic etching. Forming a second conductivity type polycrystalline semiconductor layer on the surface of the first conductivity type; and estimating an impurity source of the first conductivity type to diffuse the first conductivity type impurity, thereby forming the second conductivity type polycrystalline semiconductor layer. The conductivity type in the polycrystalline semiconductor layer is changed to the first conductivity type. Invert to the type,
Forming a first conductivity type single crystal emitter layer in the single crystal semiconductor base layer.