JP2613031B2 - Manufacturing method of bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor useful for a high-speed information processing system such as a computer and an optical communication, and more particularly, to improving a trench isolation process and the like to improve integration and performance. The present invention relates to a method of manufacturing a highly integrated self-aligned bipolar transistor.

[0002]

2. Description of the Related Art In order to improve the operation characteristics, a heterojunction bipolar transistor which uses an Si-based material instead of SiGe to reduce the energy band gap by adding Ge and uses the inclination characteristics has been emerging. Was.

The heterojunction transistor increases the injection efficiency of the emitter by using a SiGe base while simultaneously using polysilicon as a base electrode and a diffusion source of an emitter and an emitter impurity like a general homojunction transistor. Thus, the base has been grown into an ultrafine thin film with a high impurity concentration to improve the current gain and switching speed of the device.

Recently, the integration degree has been improved, that is, the device size has been reduced by scaling.
In order to reduce the parasitic capacitance between the base and the collector / base existing on the active region of the device, the process of selective thin film growth or the like is performed, and instead of the polysilicon as the base electrode thin film, Research on a process using a metallic silicide, for example, TiSi ₂ for GaN has been actively conducted.

[0005] FIG. 1 is a schematic diagram of a device fabricated using a super-self-aligned, selectively epitaxially grown SiGe base.
1 shows the structure of a conventional npn heterojunction bipolar transistor.

Referring to FIG. 1, a brief description will be given of a manufacturing process of a conventional bipolar transistor. After growing an n + sub-collector 2 and an n ~ collector 3 on a silicon substrate 1, a trench isolation process for device isolation is performed.

[0007] An insulating material is filled in the trench etched portion and flattened to form an isolation insulating film 4.

Subsequently, an insulating film 5, a p + polycrystalline silicon layer 6,
After an active region is defined by forming a pattern of the insulating film 7 and the side nitride film 8, an n collector 9 for selectively implanting ions into the active region to improve the high current characteristics of the device.
Is formed.

A gas source MBE is provided in the active region defined above.
(Gas source molecular beam epitaxy)
A Ge base 10, a polycrystalline silicon layer 6 serving as the base electrode thin film, and a polycrystalline silicon layer 11 for connecting the base 10 are continuously and selectively grown epitaxially.

Therefore, the parasitic capacitance region formed between the collector and the base is not defined as a photosensitive film, but is limited only by the region of the connection polycrystalline silicon layer 11.

The fabrication is performed by forming a sidewall insulating film 12 in the region of the intrinsic base 10 using anisotropic etching, forming a self-aligned emitter 13 and wiring an electrode 15. Complete.

This method uses the intrinsic base 10 as described above.
The emitter implantation efficiency is increased using SiGe as the base, and the collector-base and the emitter-base are all self-aligned.

Therefore, by limiting the base parasitic capacitance region only to the region corresponding to the pattern of the side nitride film 8 and the side wall insulating film 12, the size of the side nitride film 8 and the side wall insulating film 12 is adjusted, and the base parasitic capacitance region is adjusted. The resistance has been reduced.

[0014]

However, the insulating film 5
Connection polycrystalline silicon layer 11 by horizontal wet etching of
In the process of forming the pattern of the parasitic capacitance between the collector and the base by forming a pattern of the above, the stability of the process is reduced from the aspect of uniformity and reproducibility, which may cause a fatal deterioration of the device performance. Can be.

In addition, a selective thin film growth method in which the growth rate is extremely slow is used twice to form the base 10 and the connecting polycrystalline silicon layer 11, and the constituent materials are different depending on the single crystal and the polycrystal. Therefore, the process is complicated and the productivity is reduced.

Also, if polycrystalline silicon is grown on the ultra-thin film base 10 at all, it will have a fatal effect on the device.

It is an object of the present invention to provide a method of manufacturing a highly integrated self-aligned bipolar transistor which can improve the performance of a device by simplifying the process and improving the degree of integration of the device. is there.

[0018]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a highly integrated self-aligned bipolar transistor, comprising the steps of: (a) increasing the depth of a trench over the entire surface of a semiconductor substrate on which a conductive buried collector and a collector layer are formed; Controlling and sequentially forming a silicon oxide film, a polysilicon layer, a silicon oxide film, a nitride film, and a polycrystalline silicon thin film to be used as a polishing stop film during a planarization process described later; Forming a trench pattern by etching a predetermined portion of the buried collector to form a trench pattern, and then applying an insulator to a thickness sufficient to cover the trench pattern; (c) The polycrystalline silicon thin film is used as a first polishing stop film, and the nitride film is used as a second polishing stop film, and the insulator filled with the trench pattern is subjected to mechanochemical treatment. Planarizing by grinding method;
(D) forming a pattern for protecting the upper portion of the active region including the planarized isolation insulating film, exposing the collector layer of the non-active region isolated by the isolation insulating film, and performing thermal oxidation. Forming a thermally oxidized film by using a heat treatment; (e) forming an insulating film of polysilicon as an extrinsic base material on the entire surface of the substrate and exposing a portion of the insulating film in the active region; Simultaneously forming the external base region and the connection polycrystalline silicon film by patterning as described above;
(F) A nitride film is formed over the entire surface of the pattern, the exposed insulating film is etched, a base is formed on the etched portion by using a SEG (selective epitaxial growth) process, and a side surface of the nitride film is formed. Forming a sidewall film for defining an emitter region; and (g) forming a conductive emitter layer in the emitter region defined through said step;
This is achieved by a method for manufacturing a bipolar transistor, comprising a step of wiring each electrode.

Another object of the present invention is to provide a method of manufacturing a highly integrated self-aligned bipolar transistor, comprising: (a) controlling the depth of a trench over the entire surface of a semiconductor substrate on which a conductive buried collector and a collector layer are formed; Successively forming a silicon oxide film, a polysilicon layer, a silicon oxide film, a nitride film and a polycrystalline silicon thin film to be used as a polishing stop film during a planarization process; (b) defining an active region (C) sequentially etching the polycrystalline silicon thin film, the nitride film, and the silicon oxide film in the non-active region, and forming a side nitride film for determining the width of the trench on the side surface of the etched portion; Opening the side nitride film, forming a trench pattern using the opened side nitride film pattern, and burying an insulator over the entire surface of the substrate so that the trench can be sufficiently covered. (D) exposing the nitride film in the active region and the collector layer in the non-active region, and then thermally oxidizing the substrate to thermally oxidize the non-active region isolated by the shallow trench filled with the insulator. Forming a film; (e)
After forming an extrinsic base material such as polysilicon and an insulating film on the entire surface of the substrate, patterning is performed so that a part of the insulating film in the active region can be exposed and connected to the extrinsic base region. Simultaneously forming a polycrystalline silicon film;
(F) A nitride film is formed over the entire surface of the pattern, the exposed insulating film is etched, a base is formed on the etched portion by using a SEG (selective epitaxial growth) process, and a side surface of the nitride film is formed. Forming a sidewall film for defining an emitter region; and (g) forming a conductive emitter layer in the emitter region defined through said step;
This is achieved by a method for manufacturing a bipolar transistor, comprising a step of wiring each electrode.

[0020]

In the present invention, the trench isolation process for device isolation is improved to improve the degree of device integration, and the collector region outside the active region has a depth similar to that of the shallow bottom trench. Thermal oxidization reduces the number of trenches and simplifies the process. Also, the thickness of the insulating film related to the parasitic capacitance between the wiring electrode and the substrate is arbitrarily adjusted to about the thickness of the shallow trench to reduce the parasitic capacitance of the metal wiring.

Where possible, the SEG process is eliminated to simplify the process and the emitter, base and collector are all self-aligned.

[0022]

FIG. 2 shows a sectional structure of a bipolar transistor manufactured according to an embodiment of the present invention.

Referring to FIG. 2, the features of the present invention will be summarized as follows in comparison with the prior art of FIG.

First, the trench isolation process for element isolation was improved.

Since the planar area of the trench is increased in proportion to the depth of the etched trench, the present invention uses a shallow trench process to improve device integration. .

In addition, the number of trenches is reduced by thermally oxidizing the collector region outside the active region to a depth similar to the shallow trench.

Second, an unnecessary area between the isolation insulating film (4 in FIG. 1) formed by the conventional trench isolation process and the insulating film 5 formed on the isolation insulating film to define an active region. (See “L” in FIG. 1) to reduce the size of the device and the parasitic capacitance between the subcollector and the substrate.

Third, as described above, since the ultra-thin film base 10 and the connecting polycrystalline silicon layer 11 of FIG. 1 are all grown by SEG (Selective Epitaxial Growth), these regions are defined. The thickness of the insulating film 5 is limited only.

As a result, the parasitic capacitance between the wiring electrode and the substrate with the insulating film interposed therebetween increases and the operation speed of the device decreases, but the present invention also reduces the thickness of such an insulating film to the shallow bottom trench. Since the thickness can be arbitrarily adjusted to about the thickness, the parasitic capacitance of the metal wiring can be reduced.

Fourth, the present invention simplifies the process by eliminating the trench isolation process and the SEG process for connecting polycrystalline silicon growth, and self-aligns the emitter, base and collector.

Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG.

For the sake of simplicity, the elements constituting the elements are given the same reference numerals with the same numbers at the end, and explanations for overlapping parts are omitted.

Referring to FIG. 3, n-type high-concentration impurities are ion-implanted into silicon substrate 21 and heat-treated to form conductive buried collector 22 and collector layer 23.

Next, referring to FIG. 4, the depth of the trench is controlled on the entire surface of the silicon substrate 21 to form a large number of thin films to be used as a polishing stop film in a flattening step described later.

In the present embodiment, as a desirable example, for example, an insulating film 4 ', a polycrystalline silicon layer 5', a silicon oxide film 6 ', a nitride film 7' and a polycrystalline silicon layer 8 'are sequentially formed.

The insulating film 4 'is formed to a thickness of about 300 to 500 angstroms, and the polysilicon layer 5' is
It is formed to a thickness of about 2000 angstroms.

Further, the polycrystalline silicon thin film 8 ′ used as a primary polishing stop film in a flattening step described later,
The thickness of the nitride film 7 'used as the next polishing stop film is:
Each of them is determined in consideration of a depth of a trench pattern to be described later and a polishing selectivity of the isolation insulating film.

Referring to FIG. 8, a trench etching process for forming a trench is performed using a trench isolation mask (not shown).

That is, after an active region is defined using the mask, etching is continuously performed from the polycrystalline silicon thin film 8 ′ to a predetermined portion of the buried collector layer 22.

The trench pattern formed from this step is similar to the trench pattern formed by the conventional technique (see FIG. 1).

However, when the depth in the substrate is observed, there is a difference, and it can be seen that the trench pattern having the thickness corresponding to the etched thin film is immediately removed.

Subsequently, an isolation insulating film 24 'is formed on the entire surface of the substrate to a thickness that can sufficiently cover the trench.
Is applied.

At this time, as the isolation insulating film 24 'satisfying the trench pattern, for example, Si ₃ N ₄ , SiO ₂ ,
Alternatively, BPSG (boron phos) to which boron and phosphorus are added.
phorous silica glass) can be used.

Referring to FIG. 6, the isolation insulating film 24 'is planarized by a mechanical-mechanical polishing method until the polycrystalline silicon thin film 8' is exposed.

In this step, the polycrystalline silicon thin film 8 '
Is used as a primary polishing stop film.

Next, referring to FIG. 7, the exposed polycrystalline silicon thin film 8 'is removed by dry etching or wet etching, and then isolated by using the nitride film 7' as a secondary polishing stop film. The insulating film 24 'is mechanically polished and planarized.

Subsequently, the nitride film 7 'used as the second polishing stop film is etched.

Referring to FIG. 8, in order to protect an active region defined by the isolation insulating film 24 having the shallow trench from being planarized, from thermal oxidation in a subsequent process, the isolation insulating film 24 is formed. A double-layered insulating film pattern 9 ', 10' is formed on the active region included.

Subsequently, as shown in FIGS. 9 and 10, a patterned photoresist film is formed on the active region defined by the shallow trench, and then the insulating film pattern 9 'of the double layer is formed. 10 'and the exposed polycrystalline silicon thin film 5' and insulating film 4 'in the non-active region are sequentially removed.

Referring to FIG. 11, collector 23 in the non-active region exposed through the above process is thermally oxidized to form thermal oxide film 25 leaving only collector 23 in the active region.

Referring to FIG. 12, doped polysilicon 11 ', insulating film 12' and nitride film 13 'are continuously formed on the entire surface of the substrate.

Subsequently, referring to FIG. 13, patterning is performed so that a part of the insulating film 4 'in the active region can be exposed, and then a nitride film 28 is formed at this pattern portion. The insulating film 4 'is removed to form a region of the external base 26 to define an intrinsic base region.

At this time, a connection polycrystalline silicon film 31 for connecting the region of the external base 26 and the intrinsic base region is formed at the same time.

That is, the connection polycrystalline silicon film 31 can be formed on the external base 2 without a conventional SEG process or a separate process.
6 is formed at the same time as the formation of 6.

Referring to FIG. 14, after a base 30 is formed on the defined intrinsic base region by using the SEG process, a sidewall film 32 for defining an emitter region is formed on a side surface of the nitride film 28. Form.

Referring to FIG. 15, a conductive emitter layer 33 is formed in the emitter region defined through the above steps.

At this time, polysilicon having a high concentration, for example, an impurity concentration of 1 × 10 ²⁰ cm to ³ or more is used as the conductive emitter material.

As the emitter layer 33, instead of the single-layer high-concentration polysilicon, a multilayer structure, for example, the lower layer is made of single-crystal silicon having an impurity concentration of 10 ¹⁸ cm to ³ or less, top layer for the for ohmic connection can be composed of polycrystalline silicon containing 1 × 10 ²⁰ cm ~ ³ or more impurity concentration and high-concentration ion implantation.

Referring to FIG. 16, each electrode 35 is wired to complete the fabrication.

According to the present embodiment, the trench isolation process for device isolation is improved to improve the degree of device integration, and the collector region outside the active region has a depth similar to that of the shallow trench. By performing thermal oxidation, the number of trenches can be reduced and the process can be simplified.

Further, according to the present embodiment, the parasitic capacitance of the metal wiring is adjusted by arbitrarily adjusting the thickness of the insulating film related to the parasitic capacitance between the wiring electrode and the substrate to about the thickness of the shallow trench. It becomes possible to reduce.

Further, it is possible to eliminate the SEG process as much as possible, to simplify the process, and to make the emitter, base and collector self-aligned.

Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG.

The second embodiment shows another example of the step (the steps shown in FIGS. 3 to 11) of isolating the active region and the inactive region of the first embodiment.

The second embodiment of the present invention differs from the first embodiment in that the active region is defined by using the trench etching process using the trench isolation mask described above, and uses the region defined by the pattern of the side nitride film 54. It is manufactured using a shallow bottom trench formed as described above.

The steps in FIGS. 17 and 18 and the steps after FIG. 24 are the same as those in the first embodiment.

Referring to FIG. 19, an active region is defined using a predetermined photosensitive film pattern (not shown), and then the polycrystalline silicon layer 8 ', nitride film 7' and silicon in the inactive region are defined. The oxide film 6 'is etched sequentially.

Subsequently, a nitride is applied on the entire surface, and then a side nitride film 54 is formed on the side of the active region defined by using anisotropic etching. A silicon oxide film 9 'is formed on the exposed polysilicon layer 5' in the non-active region.

The width of the trench is determined by the width of the side nitride film 54, and the depth of the trench is determined by the thin film.

Referring to FIG. 20, after removing the side nitride film 54, a predetermined layer of the substrate 21 or the buried collector layer 22 can be formed by using the pattern of the removed side nitride film 54. A trench is formed by etching continuously to the site.

Subsequently, the trench is filled with an insulator 44 'to such a thickness that the trench can be sufficiently covered.

The insulator is, for example, BPSG (Boron Phosphorous Silica Glass) containing boron and phosphorus.
And nitride (Si ₃ N ₄ ) or polyimide.

Subsequently, referring to FIG. 21, the oxide film 9 'and the insulator 44' are etched.

Subsequently, as shown in FIG. 22, the polysilicon layers 5 'and 8' of the inactive region and the active region isolated by the trench 44 filled with the insulating film are removed.

FIG. 23 shows a step of forming a thermal oxide film 45 by thermally oxidizing the collector layer 23 exposed through the above steps.

According to the present embodiment, the thickness of the thermal oxide film 45 for isolating the active region can be arbitrarily adjusted to the thickness of the shallow trench 44, so that the parasitic capacitance at the time of metal wiring can be reduced. it can.

As described in the above embodiment, according to the improved manufacturing method of the present invention, unlike the conventional device isolation method using ion implantation or trench isolation, a shallow trench having a simple process can be formed. By utilizing this, the plane area of the isolation region can be reduced, and the degree of integration and productivity of the device can be improved.

Furthermore, the effect of minimizing the junction capacitance between the emitter / base / collector and improving the operation characteristics of the device from a high frequency band is exhibited.

[0079]

According to the present invention, there is provided a method of manufacturing a highly integrated self-aligned bipolar transistor capable of improving the performance of a device by simplifying the process and improving the degree of integration of the device. It becomes possible.

[0080]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a bipolar transistor manufactured by a conventional technique.

FIG. 2 is a cross-sectional view of a bipolar transistor manufactured according to the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing method according to a first embodiment of the present invention in each step.

FIG. 4 is a process sectional view illustrating a manufacturing method according to a first embodiment of the present invention for each step.

FIG. 5 is a process sectional view illustrating a manufacturing method according to a first embodiment of the present invention for each step.

FIG. 6 is a process sectional view illustrating a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 7 is a process sectional view showing a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 8 is a process sectional view showing a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 9 is a process sectional view illustrating a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 10 is a process sectional view illustrating a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 11 is a process sectional view illustrating a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 12 is a process sectional view illustrating a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 13 is a process sectional view illustrating a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 14 is a process cross-sectional view illustrating the manufacturing method according to the first embodiment of the present invention for each step.

FIG. 15 is a process sectional view showing a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 16 is a process sectional view showing a manufacturing method according to the first embodiment of the present invention for each step.

FIG. 17 is a process sectional view illustrating a manufacturing method according to a second embodiment of the present invention for each step.

FIG. 18 is a process sectional view illustrating a manufacturing method according to a second embodiment of the present invention for each step.

FIG. 19 is a process cross-sectional view illustrating a manufacturing method according to a second embodiment of the present invention for each step.

FIG. 20 is a process sectional view illustrating a manufacturing method according to a second embodiment of the present invention for each step.

FIG. 21 is a process cross-sectional view illustrating a manufacturing method according to a second embodiment of the present invention for each step.

FIG. 22 is a process cross-sectional view illustrating a manufacturing method according to a second embodiment of the present invention for each step.

FIG. 23 is a process sectional view illustrating a manufacturing method according to a second embodiment of the present invention for each step.

FIG. 24 is a process sectional view illustrating a manufacturing method according to a second embodiment of the present invention for each step.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Lee Shu-min ▼ 161 Kejeong-dong, Yuseong-gu, Daejeon, Republic of Korea Inside the Electronics Research Institute of Korea (72) Inventor Zhao Deok-ho Kejeong, Yuseong-gu, Korea 161 Dong Dong Inside the Korea Electronics and Communications Research Institute (72) Inventor Li Seung-hwan ▼ 161 Kejeong-dong, Yuseong-gu, Daejeon, Republic of Korea Inside the Korea Electronics and Communications Research Institute (72) Inventor Jang Jin-young Korea 161 Kejeong-dong, Yuseong-gu Inside the Korea Electronics Research Institute

Claims (9)

(57) [Claims] 1. A method of manufacturing a highly integrated self-aligned bipolar transistor, comprising: (a) controlling the depth of a trench over the entire surface of a semiconductor substrate on which a conductive buried collector and a collector layer are formed; Sequentially forming a silicon oxide film, a polysilicon layer, a silicon oxide film, a nitride film and a polycrystalline silicon thin film to be used as a polishing stop film in some cases; (b) using a separation mask to define the buried collector; (C) forming a trench pattern by etching the trench up to the portion, and then applying an insulating material to a thickness sufficient to cover the trench pattern; Using the nitride film as a polishing stop film and using the nitride film as a secondary polishing stop film, the insulator filled with the trench pattern is planarized by a mechanochemical polishing method. (D) forming a pattern for protecting the upper part of the active region including the planarized isolation insulating film, exposing the collector layer of the non-active region isolated by the isolation insulating film, and then applying heat. Oxidizing to form a thermal oxide film; (e) forming polysilicon as an extrinsic base material and an insulating film on the entire surface of the substrate, and then partially exposing the insulating film in the active region. Simultaneously forming an external base region and a connection polycrystalline silicon film by patterning to form a nitride film over the entire surface of the pattern, etching the exposed insulating film, and etching the exposed insulating film. Forming a base using an SEG (selective epitaxial growth) process, and forming a sidewall film for defining an emitter region on a side surface of the nitride film; and Tsu the data area to form an electrically conductive emitter layer, the manufacturing method of the bipolar transistor, characterized by comprising a step of wiring the electrodes. 2. The method according to claim 1, wherein the thickness of the polycrystalline silicon thin film used as the first polishing stop film and the thickness of the nitride film used as the second polishing stop film are the same as those of the trench pattern. The thickness of the polysilicon layer is about 2000 °, and the thickness of the oxide film is about 30 °.
A method for manufacturing a bipolar transistor, which is 0 to 500 °. 3. The method according to claim 1, wherein the insulator satisfying the trench pattern in the step (b) is B
PSG (Boron Phosphorous Silica Glass), Si
₃ N ₄ manufacturing method of the bipolar transistor, characterized in that, and is composed of one in the polyimide. 4. The conductive emitter layer according to claim 1, wherein the conductive emitter layer in the step (g) is 1 × 10 ²⁰ cm.
~ A method for manufacturing a bipolar transistor, comprising a single-component polysilicon having an impurity concentration of ³ or more. 5. The semiconductor device according to claim 1, wherein the conductive emitter layer in the step (g) has a high level because of ohmic contact between the lower layer made of single-crystal silicon having an impurity concentration of 10 ¹⁸ cm ³ or less and the electrode. Ion implanted to concentration
And a top layer made of polycrystalline silicon having an impurity concentration of × 10 ²⁰ cm to ³ or more. 6. A method of manufacturing a highly integrated self-aligned bipolar transistor, comprising: (a) controlling the depth of a trench over the entire surface of a semiconductor substrate on which a conductive buried collector and a collector layer are formed; Sequentially forming a silicon oxide film, a polysilicon layer, a silicon oxide film, a nitride film, and a polycrystalline silicon thin film, which are sometimes used as a polishing stop film; (b) defining an active region and then an inactive region Forming a side nitride film for determining the width of a trench on a side surface of the etched portion after sequentially etching the polycrystalline silicon thin film, the nitride film and the silicon oxide film; Forming a trench pattern by using the opened side-surface nitride film pattern and burying an insulator over the entire surface of the substrate so that the trench can be covered sufficiently; (d) Exposing the nitride film in the active region and the collector layer in the non-active region, and thermally oxidizing the substrate to form a thermal oxide film in the non-active region isolated by a shallow trench filled with an insulator; (E) forming an extrinsic base material such as polysilicon and an insulating film on the entire surface of the substrate, and then patterning the exposing base material to expose a portion of the insulating film in the active region; Simultaneously forming a region and a connecting polycrystalline silicon film; (f) forming a nitride film over the entire surface of the pattern, etching the exposed insulating film, and using a SEG (selective epitaxial growth) process at the etched portion. Forming a base film and forming a sidewall film for defining an emitter region on a side surface of the nitride film; and (g) forming a conductive emitter layer in the emitter region defined through the above-described process. Method for producing a bipolar transistor, characterized in that it comprises a step of wiring the electrodes. 7. The insulator according to claim 6, wherein the insulator satisfying the trench pattern in the step (c) is B
PSG (Boron Phosphorous Silica Glass), Si
₃ N ₄ manufacturing method of the bipolar transistor, characterized in that, and is composed of one in the polyimide. 8. The conductive emitter layer according to claim 6, wherein the conductive emitter layer in the step (g) is 1 × 10 ²⁰ cm.
~ A method for manufacturing a bipolar transistor, comprising a single-component polysilicon having an impurity concentration of ³ or more. 9. The semiconductor device according to claim 6, wherein the conductive emitter layer in the step (g) has a high level because of ohmic contact between the lower layer made of single crystal silicon having an impurity concentration of 10 ¹⁸ cm ³ or less and the electrode. Ion implanted to concentration
A method of manufacturing a bipolar transistor, comprising: an upper layer made of polycrystalline silicon containing an impurity concentration of × 10 ²⁰ cm to ³ or more.