KR100866923B1 - A bipolar transistor fabricating method - Google Patents

Abstract

The speed characteristic of device can be improved by self-aligning an emitter and a base. The film thickness and impurity concentration of the base epi can be uniformly maintained when growing the base-epi in wafer. The base resistance can be reduced. A step is for forming the buried zone on the silicon substrate(201) and providing the semiconductor substrate in which the collector sinker is divided into the first and second conductive layer, and the base layer by the element isolation film. A step is for etching the second insulating layer one of the first insulating layer and the second insulating which are stacked successively on the semiconductor substrate. A step for forming the base electrode electrically connected to the base layer of the second conductor layer which is exposed outwardly by performing the second etching selectively on the first insulating layer corresponds to the second conductor layer. A step is for forming the emitter electrode which is electrically connected to the base layer and the collector electrode which is electrically connected to the collector sinker.

Description

Bipolar Transistor Fabricating Method

The present invention relates to a method for manufacturing a bipolar transistor, and more particularly, it is possible to self-align the emitter and the base to improve the speed characteristics of the device, and the film thickness and impurities of the base epi when growing the base epitaxial in the wafer The present invention relates to a method for manufacturing a bipolar transistor that can maintain a uniform concentration and can improve base resistance.

In general, bipolar junction transistors (hereinafter referred to as bipolar transistors) have higher current driving capability and faster operating speed than MOS Field Effect Transistors (MOSFETs). Increasingly, specific parts are replaced by bipolar transistors instead of MOS field effect transistors.

Such bipolar transistors include three adjacently doped impurity regions or impurity layers having an NPN or PNP doping structure. The middle region forms a base, and the two end regions form an emitter and a collector.

Here, the emitter has a higher impurity concentration than the base and the collector, and the base has a higher impurity concentration than the collector.

Such bipolar transistors operate as amplifiers or switches, for example when used as amplifiers, amplify the input signal supplied between the base and the emitter, and the output signal appears across the emitter / collector. And, when used as a switch, the output signal appearing on both ends of the emitter / collector is switched to open or close the emitter / collector.

FIG. 1 is a vertical cross-sectional view of a bipolar transistor according to the prior art. As shown in FIG. 1, a conventional bipolar transistor includes an N + buried layer 102 and an N− collector epi region formed on a P-type substrate 101. 103 and an N + collector sinker region 104.

The N-collector epi region 103 is divided into a region where an emitter and a base are formed and a region where a collector is formed by an oxide device isolation film 105 provided by a LOCOS (LOCcal Oxidation of Silicon) process.

On the other hand, a silicon nitride film pattern layer 108 is formed on the semiconductor substrate as described above, including a window defining a collector region, and a P + polysilicon pattern layer 106 is provided thereon.

The N + polysilicon 107 is connected to the N + collector sinker region 104 to serve as a collector electrode.

The P + polysilicon pattern layer 106 and the silicon oxide film 109 are opened to the outside in the emitter region through dry etching using a mask.

In this case, when the silicon nitride film pattern layer 108 is formed, it is difficult to adjust the width etched to the side, so that it is difficult to control the bonding capacity between the base and the collector.

That is, in the above-described conventional structure, the base epi region 110 and the polysilicon base layer 111 are exposed only to a portion where the silicon material is exposed through the selective epitaxial growth technique by Molecular Beam Epitaxy (MBE). To grow. By the selective epitaxial growth technique, the base epi region 110 and the polysilicon base layer 111 are electrically connected to each other in the base linker 110a region.

However, there is a problem in that a local loading effect occurs when the base epitaxial layer is grown through the selective epitaxial growth technique in the process of manufacturing the conventional bipolar transistor. That is, the "local loading effect" is a phenomenon in which the thickness of the grown silicon layer is changed depending on the area ratio of the exposed silicon when the epitaxial layer is grown only on the exposed silicon (or polysilicon) through the selective epitaxial growth technique. (See Akihiko et. Al., "Local Loading Effect in Selective Silicon Epitaxy", Japanese Journal of Applied Physics, Vol. 23, No. 6, June, 1984 pp. L391-393.)

Therefore, when comparing the area of the exposed silicon and the area of the silicon oxide film in the entire wafer where the selective epitaxial growth process is performed in the conventional bipolar transistor manufacturing process, since the silicon area is relatively small, by the selective epitaxial growth method In the process of forming the base film, a local loading effect occurs in which the thickness of the base film varies depending on the area of the exposed silicon. In addition, there is a problem that the thickness of the base film is limited by the thickness of the coated silicon nitride film pattern layer.

Due to such a local loading effect, the characteristics of the bipolar transistor are different from each other in the wafer or between the wafers, and thus there is a problem in that the mass productivity may be significantly reduced.

In addition, it is difficult to control the width of the silicon nitride film pattern layer etched laterally to change the bonding capacity characteristics between the base and the collector to reduce the electrical properties, while the base epi area and the polysilicon base film are in contact with each other in the process of forming the base film As the linker was buried, there was a problem that it was difficult to control the thickness in the wafer.

Accordingly, the present invention is to solve the above problems, the object is to be able to self-align the emitter and the base to improve the speed characteristics of the device, the thickness of the base epi when the base epi growth in the wafer And to provide a bipolar transistor manufacturing method that can maintain the impurity concentration uniformly, while reducing the base resistance.

As a specific means for achieving the above object, the present invention provides a semiconductor substrate in which a buried region is formed in a silicon substrate, and the collector sinker is separated from the first and second conductive layers and the base layer by an isolation layer. ; First etching the second insulating film among the first insulating film and the second insulating film sequentially applied to the upper surface of the semiconductor substrate; Selectively etching the second insulating layer and the first insulating layer corresponding to the second conductive layer and forming a base electrode electrically connected to the base layer of the second exposed layer; Selectively etching the first insulating layer to form an emitter electrode electrically connected to an externally exposed base layer, and a collector electrode electrically connected to an externally exposed collector sinker during third etching; Provided is a method for manufacturing a transistor.

Preferably, the first conductive layer and the second conductive layer are made of a silicon semiconductor doped with N-type or P-type impurities at 1E14 / cm 3 to 1E21 / cm 3.

Preferably, the base layer is selectively made of a P-type or N-type silicon film, a silicon-germanium film, or a combination thereof.

Preferably, the first etching of the second insulating layer may include patterning a photoresist film on the surface of the second insulating layer by photolithography and an exposure process to expose the second insulating layer to the first, second and third pattern holes. Forming a; Forming first, second and third contact holes exposing the first insulating layer to the outside by removing the second insulating layer exposed through the first, second and third pattern holes by a wet etching process or a dry etching process; And removing the photosensitive film remaining on the surface of the second insulating film.

Preferably, the forming of the base electrode may include applying a third insulating film and a photosensitive film to an outer surface of the second insulating film; Patterning the third insulating film and the photosensitive film, and then removing the third contact hole corresponding to the second conductive layer and the third insulating film and the first insulating film applied around the second conductive layer by dry or wet etching; And forming an electrode in contact with the base layer exposed to the outside through the third contact hole.

More preferably, the base electrode is formed by a selective epitaxial growth method using the third insulating film and the second insulating film as a mask.

More preferably, the base electrode is selectively formed of a silicon thin film, polysilicon or metal silicide or combinations thereof doped with P-type or N-type impurities at 1E18 / cm 3 to 1E21 / cm 3.

The forming of the emitter electrode and the collector electrode may include forming a second contact hole corresponding to the base layer and a first contact hole corresponding to the collector sinker among the third insulating films coated on the outer surface of the second insulating film. Removing the third insulating film applied to the; Removing the first insulating layer exposed through the first and second contact holes by wet or dry etching; And forming an electrode contacting the base layer and the collector sinker, which are externally exposed through the first and second contact holes.

More preferably, the emitter electrode and the collector electrode are formed by coating polysilicon doped with P-type or N-type impurities at 1E18 / cm 3 to 1E21 / cm 3 in the second contact hole and the first contact hole.

According to the present invention, the collector sinker sequentially applies the first and second insulating films to the semiconductor substrate separated from the first and second conductive layers and the base layer by the device isolation film, and the second insulating film of the first and second insulating films is one. Second etching the second conductive layer and the first insulating layer corresponding to the second conductive layer to form a base electrode electrically connected to the base layer exposed to the outside, and third exposure of the first insulating layer corresponding to the collector sinker. Since the collector electrode which is electrically connected to the collector sinker can be formed, the process of forming the base epi and the electrode is simple, and the thickness and impurity concentration of the base film grown in the wafer substrate are uniform, resulting in uniform electrical characteristics. While the electrical isolation between the emitter and the base is formed by self-alignment, the speed characteristics of the device can be further improved. Impurities contained in the second conductive layer and the base electrode are diffused into the base layer, thereby reducing the base resistance, thereby increasing the maximum vibration frequency.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2 (i), the bipolar transistor according to the preferred embodiment of the present invention includes a semiconductor substrate, first and second insulating layers 208 and 209, first and second contact holes 209a, 209b and 209c, and The base electrode 213, the emitter electrode 214, and the collector electrode 215 are included.

That is, the semiconductor substrate includes an N-type buried region 202 on the P-type silicon substrate 201, and a collector sinker in the buried region 202 together with the collector epitaxial film that is the first conductive layer 203. a second conductive layer 206 is formed on the first conductive layer 203, and the first conductive layer 203 exposes the second conductive layer 206 to the outside. A device isolation film 205 is formed to form a base epi, which is the base layer 207, and to separate the base-emitter region A and the collector region B from each other.

Accordingly, the first conductive layer 203 and the second conductive layer 206 formed on the buried region 202 and the base layer 207 formed on the surfaces of the first and second conductive layers 203 and 206. The base-emitter region A including the collector region and the collector region B including the collector sinker 204 formed on the buried region 202 are electrically separated from each other by the device isolation layer 205. .

Here, the first conductive layer 203 may be formed of a silicon semiconductor doped with N-type or P-type impurities from 1E14 / cm 3 to 1E19 / cm 3, and the second conductive layer 206 may be a P-type or N-type impurity. The silicon thin film doped with 1E18 / cm 3 to 1E21 / cm 3 may be formed, and the base layer 207 may be formed of a P-type or N-type silicon film, a silicon-germanium film, or a combination thereof.

The first insulating film 208 made of a silicon oxide film and the second insulating film 209 made of a silicon nitride film are stacked on the surface of the semiconductor substrate to correspond to the base-emitter region A. FIG. Second and third contact holes 209b and 209c for externally exposing the base-emitter region by selectively etching the first and second insulating layers 208 and 209, and first and second corresponding to the collector regions B. The second insulating layers 208 and 209 are selectively etched to form first contact holes 209a for exposing the collector region to the outside.

The third contact hole 209c is provided in the first and second insulating layers 208 and 209 so as to externally expose the base layer 207 corresponding to the second conductive layer 206 and the second contact hole 209b. ) Is provided in the first and second insulating layers 208 and 209 to externally expose the first conductive layer 203 and the corresponding base layer 207, while the first contact hole 209a is formed in the collector sinker 204. ) Is provided in the first and second insulating films 208 and 209 to expose the externally.

Meanwhile, the emitter electrode 214 is coated with polysilicon doped with P-type or N-type impurities at 1E18 / cm 3 to 1E21 / cm 3 in the second contact hole 209b formed in the center region of the base-emitter region. Is formed.

In addition, the base electrode 213 is a silicon thin film, polysilicon, or metal doped with P-type or N-type impurities at 1E18 / cm 3 to 1E21 / cm 3 in a third contact hole formed outside the center area of the base-emitter region. And optionally formed of silicides or combinations thereof.

In addition, the collector electrode 215 is formed by applying polysilicon doped with N-type or P-type impurities at 1E18 / cm 3 to 1E21 / cm 3 in the first contact hole formed in the collector region.

2 (a) to 2 (i) are cross-sectional views sequentially illustrating a method of manufacturing a bipolar transistor according to a preferred embodiment of the present invention.

Forming a buried region in the silicon substrate and providing a semiconductor substrate in which the collector sinker is separated from the first and second conductive layers and the base layer by an isolation layer;

The process of manufacturing the bipolar transistor according to the preferred embodiment of the present invention begins with the preparation of the P-type silicon substrate 201, as shown in Figure 2 (a), the surface of the silicon substrate 201 N-type impurities are concentrated at high concentration by diffusion by ion implantation process to inject N-type impurities such as Arsenic (As) or Phosphorus (P) as ions or solid-state diffusion to solid phase. A doped N-type buried region 202 is formed, wherein the buried region 202 is also referred to as a sub-collector region.

Subsequently, a surface of the buried region 202 is a first conductive layer 203 which is a collector epitaxial film made of a lightly doped N-type single crystal silicon film using an epitaxial technique, and a collector sinker. 204 is formed.

Here, the first conductive layer 203 provided as the collector epitaxial film is made of a silicon semiconductor doped with N-type impurities of 1E14 / cm 3 to 1E19 / cm 3 or P-type impurities of 1E14 / cm 3 to 1E21 / cm 3 It may be made of a silicon semiconductor.

The first conductive layer 203 and the collector sinker 204 are electrically separated from each other by the device isolation layer 205, and the device isolation layer 205 is formed of LOCal Oxideation Silicon (LOCOS) and Shallow Trench Isolation (STI). , PSL (Polysilicon Spacer LOCOS), PBL (Polysilicon Buffered LOCOS) and the like.

Accordingly, the first conductive layer 203 corresponds to the base-emitter region A in which the base electrode and the emitter electrode are formed, and the collector sinker 104 is the collector region B in which the collector electrode is formed. ), And these regions are defined by the device isolation layer 105.

In addition, the device isolation layer 205 is illustrated and described as being provided after the first conductive layer 203 and the collector sinker 204 are formed on the surface of the buried region 202, but are not limited thereto. It may be provided before forming the one conductive layer 203 and the collector sinker 204.

Subsequently, a second conductive layer 206 is formed on the surface of the first conductive layer 203, which is a collector epitaxial film separated from the collector sinker 204 by the device isolation film 205.

Here, the second conductive layer 206 may be made of a silicon thin film doped with P-type impurities at 1E18 / cm 3 to 1E21 / cm 3, or may be made of a silicon thin film doped with N-type impurities at 1E18 / cm 3 to 1E21 / cm 3. .

In this process, the second conductive layer 206 serves to lower the resistance of the base electrode. In particular, in the process of using the epitaxial film as a base, the second conductive layer 206 is formed before the base epitaxial growth. The diffusion of impurity concentration in the base epitaxial layer is suppressed to increase the cutoff frequency fT.

Subsequently, as shown in FIG. 2 (b), the base layer, which is a base epitaxial layer, is formed on the surface of the semiconductor substrate corresponding to the base-emitter region A to which the first and second conductive layers 203 and 206 are externally exposed. 207).

In this process, the thickness of the base layer can be uniformly obtained by using a non-selective epitaxial growth method and a dry etching method by a photo process instead of using a selective epitaxial growth method in the growth of the base epitaxial, and almost no change in the concentration of impurities. Since it does not exist, the base epitaxial thickness and the impurity concentration change by the local loading effect are suppressed as much as possible.

The base layer 207 may be formed of a P-type or N-type silicon film, a silicon-germanium film, or a combination thereof.

First etching the second insulating layer among the first insulating layer and the second insulating layer sequentially applied to the upper surface of the semiconductor substrate;

As illustrated in FIG. 2C, a first insulating film 208 and a second insulating film 209 are sequentially stacked from the bottom to the top of the semiconductor substrate manufactured as described above, and the first insulating film may be sequentially stacked. The insulating film 208 is provided with a silicon oxide film, and the second insulating film 209 is provided with a silicon nitride film.

The photoresist film 210 is generally coated on the surface of the insulating layer formed of the first and second insulating films 208 and 209, and then the patterned photoresist film 210 is formed through a mask, a photo, and an exposure process, which are not shown. First, second and third pattern holes 210a, 210b and 210c may be formed to expose the second insulating layer 209 to the outside.

Here, the first pattern hole 210a is formed to correspond to the collector sinker 204 of the collector region B, and the second and third pattern holes 210b and 210c are the base-emitter region A. It is formed to correspond to the base layer 207 of the. In addition, the second pattern hole 210b corresponds to the first conductive layer 203 disposed under the base layer 207, and the third pattern hole 210c corresponds to the second conductive layer 206. Should be provided in the corresponding area.

Subsequently, the photoresist film 210 having the first, second and third pattern holes 210a, 210b, and 210c formed thereon as a mask is subjected to a first dry etching process such as reactive ion etching (RIE). As shown in FIG. 2D, the second insulating layer 209 is removed by removing the second insulating layer 209 that is externally exposed through the first, second and third pattern holes 210a, 210b, and 210c. First, second and second contact holes 209a, 209b, and 209c exposing the first insulating layer 208 to the outside are formed, and then the photoresist layer 210 remaining on the surface of the second insulating layer 209 is removed.

The etching process of etching the second insulating layer 209 to form the first, second and third contact holes 209a, 209b, and 209c exposing the first insulating layer 208 to the outside may be performed by a wet etching process. have.

Meanwhile, when the primary etching of the second insulating layer 209 is excessive, since the first insulating layer 208 may be partially etched, the first insulating layer stacked below the second insulating layer 209. The thickness of 208 should be formed so that it can remain more than a predetermined thickness even after the first etching of the first insulating film.

Selectively etching the second insulating layer and the first insulating layer corresponding to the second conductive layer to form a base electrode electrically connected to the base layer of the second exposed layer

As described above, the outer surface of the second insulating film 209 having the first, second and third contact holes 209a, 209b, and 209c for exposing the first insulating film 208 to the outside by primary etching is illustrated in FIG. As shown in e), a third insulating film 211, such as a silicon oxide film, is applied to a predetermined thickness, and then the photosensitive film 212 is coated on the upper surface of the third insulating film 211 at a predetermined thickness.

The third insulating film 211 and the photosensitive film 212 are also coated on the inner surfaces of the first, second and third contact holes 209a, 209b, and 209c with a predetermined thickness.

Subsequently, the third insulating film 211 and the photosensitive film 212 are patterned by a photo process using a mask (not shown), as shown in FIG. 2F, and then the second conductive layer 206 The corresponding third contact hole 209c, the third insulating film 211 coated around it, and the first insulating film 208 corresponding to the bottom surface of the third contact hole 209c are either dry or wet. The base layer 207 is externally exposed through the third contact hole 209c by removing by the selected secondary etching process, and then the photoresist film 212 remaining in the third insulating film 211 is removed.

As shown in FIG. 2G, in the third contact hole 209c to which the base layer 207 is externally exposed, the remaining third insulating film 211 and the second insulating film 209 are masked. And a base electrode 213 which is formed by selecting any one of silicon thin film, polysilicon, or metal silicide doped with P-type or N-type impurity from 1E18 / cm 3 to 1E21 / cm 3 by applying a selective epitaxial growth method. You can do it.

Here, impurities included in the base electrode 213 and the second conductive layer 206 made of silicon diffuse to the base layer 207 to decrease the base resistance, thereby increasing the maximum vibration frequency fmax.

Selectively etching the first insulating layer to form an emitter electrode electrically connected to an externally exposed base layer, and a collector electrode electrically connected to an externally exposed collector sinker during third etching;

As shown in FIG. 2 (h) in the state where the base electrode 213 is formed in the third contact hole 209 c, the surface of the second insulating film 209 and the surface of the base electrode 213 are formed. The fourth insulating film 216 is coated to a predetermined thickness so that the third insulating film 211 is exposed to the outside, and then a photosensitive film 216a is applied to the surface of the fourth insulating film 216.

In this state, the externally exposed third insulating film 211 and the first insulating film 208 are removed by a third etching process by dry or wet etching, and thus the first conductive layer is formed through the second contact hole 209b. While exposing the base layer 207 corresponding to 203 externally, the collector sinker 204 is externally exposed through the first contact hole 209a, and then the photoresist film 216a is removed.

Subsequently, as shown in FIG. 2 (i), the second contact hole 209b to which the base layer 207 is externally exposed is poly-doped with P-type or N-type impurities at 1E18 / cm 3 to 1E21 / cm 3. Silicon is applied to form the emitter electrode 214.

In addition, the first contact hole 209a to which the collector sinker 204 is externally exposed is coated with polysilicon doped with P-type or N-type impurities at 1E18 / cm 3 to 1E21 / cm 3 to form the collector electrode 215. do.

After the emitter electrode 214 and the collector electrode 215 are formed, all of the remaining fourth insulating layer 216 is removed to expose the second insulating layer 209 to the outside.

Here, the emitter electrode 214 and the collector electrode 215 may be formed at the same time by applying polysilicon to the first and second contact holes 209a and 209b, but the present invention is not limited thereto. May be

Subsequently, a base electrode and an emitter electrode are formed in the base-emitter region, and a metal wiring process is performed on the substrate on which the collector electrode is formed in the collector region, thereby completing a process of manufacturing a bipolar transistor.

 While the invention has been shown and described with respect to particular embodiments, it will be understood that various changes and modifications can be made in the art without departing from the spirit or scope of the invention as set forth in the claims below. It will be appreciated that those skilled in the art can easily know.

1 is a longitudinal sectional view showing a bipolar transistor according to the prior art.

2 (a) to 2 (i) are cross-sectional views sequentially illustrating a method of manufacturing a bipolar transistor according to a preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

201: silicon substrate 202: buried region

203: first conductive layer 204: collector sinker

205: device isolation layer 206: second conductive layer

207: base layer 208: first insulating film

209: Second insulating film 209a, 209b, 209c: First, second, third contact hole

210,212,216a: photosensitive film 211: third insulating film

213: base electrode 214: emitter electrode

215: collector electrode 216: fourth insulating film

Claims (10)

Forming a buried region in the silicon substrate, and the collector sinker providing a semiconductor substrate separated from the first and second conductive layers and the base layer by an element isolation film; First etching the second insulating film among the first insulating film and the second insulating film sequentially applied to the upper surface of the semiconductor substrate; Selectively etching the second insulating layer and the first insulating layer corresponding to the second conductive layer and forming a base electrode electrically connected to the base layer of the second exposed layer; Selectively etching the first insulating layer to form an emitter electrode electrically connected to an externally exposed base layer, and a collector electrode electrically connected to an externally exposed collector sinker during third etching; Transistor manufacturing method. The method of claim 1, wherein the first conductive layer and the second conductive layer are made of a silicon semiconductor doped with N-type or P-type impurities from 1E14 / cm 3 to 1E21 / cm 3. The method of claim 1, wherein the base layer is selectively formed of a P-type or N-type silicon film, a silicon-germanium film, or a combination thereof. The method of claim 1, wherein the first etching of the second insulating layer is performed. Patterning a photoresist film coated on a surface of the second insulating film by photolithography and an exposure process to form first, second and third pattern holes for externally exposing the second insulating film; Forming first, second and third contact holes exposing the first insulating layer to the outside by removing the second insulating layer exposed through the first, second and third pattern holes by a wet etching process or a dry etching process; And Removing the photoresist film remaining on the surface of the second insulating film. The method of claim 1, wherein the forming of the base electrode Coating a third insulating film and a photosensitive film on an outer surface of the second insulating film; Patterning the third insulating film and the photosensitive film, and then removing the third contact hole corresponding to the second conductive layer and the third insulating film and the first insulating film applied around the second conductive layer by dry or wet etching; And And forming an electrode in contact with the base layer that is exposed to the outside through the third contact hole. The method of claim 5, wherein the base electrode is formed by a selective epitaxial growth method using the third insulating layer and the second insulating layer as a mask. The bipolar transistor of claim 5, wherein the base electrode is selectively formed of a silicon thin film, polysilicon, or a metal silicide or a combination thereof doped with P-type or N-type impurities at 1E18 / cm 3 to 1E21 / cm 3. Way. The method of claim 1, wherein the forming of the emitter electrode and the collector electrode Removing a third insulating film applied to a second contact hole corresponding to the base layer and a first contact hole corresponding to the collector sinker among the third insulating films applied to an outer surface of the second insulating film; Removing the first insulating layer exposed through the first and second contact holes by wet or dry etching; And And forming an electrode contacting the base layer and the collector sinker, which are externally exposed through the first and second contact holes. The method of claim 8, wherein the emitter electrode and the collector electrode is formed by applying polysilicon doped with P-type or N-type impurities of 1E18 / cm3 to 1E21 / cm3 in the second contact hole and the first contact hole. A bipolar transistor manufacturing method. Bipolar transistor produced by the method of any one of claims 1 to 9.

Images