KR0161197B1 - Method for fabricating self-aligned bipolar transistor - Google Patents
Method for fabricating self-aligned bipolar transistor Download PDFInfo
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- KR0161197B1 KR0161197B1 KR1019950055092A KR19950055092A KR0161197B1 KR 0161197 B1 KR0161197 B1 KR 0161197B1 KR 1019950055092 A KR1019950055092 A KR 1019950055092A KR 19950055092 A KR19950055092 A KR 19950055092A KR 0161197 B1 KR0161197 B1 KR 0161197B1
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000010408 film Substances 0.000 claims abstract description 93
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 28
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000010409 thin film Substances 0.000 claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052796 boron Inorganic materials 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000005520 cutting process Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000010365 information processing Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- XUIMIQQOPSSXEZ-RNFDNDRNSA-N silicon-32 atom Chemical compound [32Si] XUIMIQQOPSSXEZ-RNFDNDRNSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
본 발명은 베이스 전극을 선택적 금속 실리사이드 단결정 성장하여 저저항의 베이스 전극을 형성하고 에미터와 베이스가 자기 정렬되게 함으로써 베이스 기생저항을 크게 감소키킨 바이폴러 트랜지스터 제조방법에 관한 것으로서, 그 특징은 자기정렬 바이폴러 트랜지스터의 제조공정에 있어서, 실리콘 기판에 고농도의 불순물을 이온주입하여 서브렉터를 형성시키는 제 1 과정과, 컬렉터를 다결정 성장시키는 제 2 과정과, 소자격리를 위한 산화막을 형성시키는 제 3 과정과, 고농도의 불순물을 이온주입하여 컬렉터 싱커를 형성시키는 제 4 과정과, 베이스 박막을 형성시키는 제 5 과정과, 산화막과 질화막과 산화막을 도포하는 제 6 과정과, 산화막과 질화막과 산화막을 식각하는 제 7 과정과, 비활성 베이스 영역을 고농도의 붕소로 도핑함으로써 금속 실리사이드과의 오옴 저항을 작게 하는 제 8 과정과, 금속 실리사이드 박막을 선택적으로 단결정 성장시키는 제 9 과정과, 실리콘을 상기 금속 실리사이드 박막 위에 연속하여 단결정 성장시키는 제 10 과정과, 산화막을 식각하여 제거하고 단결정 성장된 실리콘을 저온에서 열산화하여 산화막을 형성시키는 제 11 과정과, 산화막을 도포하고 다시 식각하여 측벽막을 형성하는 제 12 과정과, 질화막과 산화막을 차례로 식각하여 측벽막을 완성하는 제 13 과정과, 에미터 전극인 다결정 실리콘을 도포하고 불순물을 첨가하는 제 14 과정과, 식각하여 에미터를 형성하는 제 15 과정과, 절역막을 전면에 도포하고 에미터 접합을 형성하기 위한 열처리를 행하는 제 16 과정과, 절연막을 식각하여 금속접촉 부분을 정의하는 제 17 과정 및 금속을 증착하고 식각하여 소자를 완성하는 제 18 과정을 포함하는 데에 있으므로, 본 발명은 비활성 베이스로 금속 실리사이드 박막을 사용하기 때문에 소자의 기생 베이스 저항이 작으며, 에미터와 베이스를 자기정렬시킴으로써 재현성이 높고 소자의 크기를 줄여 집적도를 높일 수 있고, 비활성 베이스로 금속 실리사이드 박막을 단결정으로 성장시키기 때문에 금속 실리사이드(metal salicide) 형성공정에 의해 제조된 것보다 실리콘과 금속 실리사이드 계면의 고온반응에 의해 발생하는 계면 모양이 보다 더 평평하므로 계면 누설 전류가 작아지고, 계면의 면적이 작아지므로 베이스-걸렉터 접합용량도 또한 감소하게 되는 등 소자의 고주파 응답 특성이 우수하다는 데에 그 효과가 있다.The present invention relates to a method of manufacturing a bipolar transistor in which the base electrode is selectively grown on a single metal silicide single crystal to form a low resistance base electrode, and the emitter and the base are self-aligned, thereby greatly reducing the base parasitic resistance. In the manufacturing process of a bipolar transistor, a first process of forming a collector by ion implantation of a high concentration of impurities into a silicon substrate, a second process of polycrystalline growth of the collector, and a third process of forming an oxide film for device isolation And, a fourth process of forming a collector sinker by ion implantation of a high concentration of impurities, a fifth process of forming a base thin film, a sixth process of applying an oxide film, a nitride film, and an oxide film, and etching the oxide film, the nitride film, and the oxide film. The seventh process and the metal by doping the inactive base region with high concentration of boron An eighth process of reducing ohmic resistance with silicide, a ninth process of selectively monocrystalline growing a metal silicide thin film, a tenth process of continuously growing single crystal of silicon on the metal silicide thin film, and etching and removing an oxide film to form a single crystal An eleventh process of thermally oxidizing the grown silicon at a low temperature to form an oxide film, a twelfth process of applying an oxide film and etching again to form a sidewall film, a thirteenth process of sequentially etching a nitride film and an oxide film to complete the sidewall film, A sixteenth process of applying polycrystalline silicon as an emitter electrode and adding impurities, a fifteenth process of etching to form an emitter, a sixteenth process of applying a cutting film to the entire surface and a heat treatment to form an emitter junction; 17th process of defining the metal contact portion by etching the insulating film and depositing and etching the metal Since the eighteenth process of completing the ruler is included, the present invention uses a metal silicide thin film as the inactive base, so the parasitic base resistance of the device is small, and the device is highly reproducible by self-aligning the emitter and the base. Increasing the density, and growing the metal silicide thin film as a single crystal with an inert base, the interface shape caused by the high temperature reaction of silicon and metal silicide interface is more than that produced by the metal salicide formation process Because of the flatness, the interface leakage current is small and the area of the interface is small, so that the base-collector junction capacitance is also reduced.
Description
제1도는 종래의 기술에 의해 제작된 바이폴러 트랜지스터의 단면도.1 is a cross-sectional view of a bipolar transistor manufactured by a conventional technique.
제2도는 본 발명에 따른 바이폴러 트랜지스터의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a bipolar transistor according to the present invention.
제3도는 본 발명에 의한 바이폴러 트랜지스터의 제조방법을 순차적으로 나타낸 공정 단면도.3 is a cross-sectional view sequentially showing a method of manufacturing a bipolar transistor according to the present invention.
본 발명은 컴퓨터나 통신기기 등의 차세데 고속 정보처리 시스템에 널리 이용되고 있는 고속 바이폴러(bipolar) 트랜지스터의 제조방법에 관한 것으로서, 베이스 전극을 선택적 금속 실리사이드 단결정 성장하여 저저항의 베이스 전극을 형성하고 에미터와 베이스가 자기 정렬되게 함으로써 베이스 기생저항을 크게 감소시킨 바이폴러 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a high speed bipolar transistor widely used in next-generation high-speed information processing systems such as computers and communication devices, wherein the base electrode is selectively grown on a metal silicide single crystal to form a low resistance base electrode. The present invention relates to a bipolar transistor manufacturing method which greatly reduces the base parasitic resistance by allowing the emitter and the base to self-align.
제1도는 종래의 기술에 의해 제작된 바이폴러 트랜지스터의 단면도이다.1 is a cross-sectional view of a bipolar transistor manufactured by a conventional technique.
제1도를 참조하여 종래의 기술에 의해 제작된 바이폴러 트랜지스터를 설명하면 다음과 같다.Referring to FIG. 1, a bipolar transistor manufactured by a conventional technique will be described.
이런 구조의 트랜지스터를 얻기 위해서는, 먼저, 실리콘 기판(1)에 고농도의 불순물을 이온주입하여 서브컬렉터(sub collector)(2)를 형성시킨다.In order to obtain a transistor of this structure, first, a high concentration of impurities are ion-implanted into the silicon substrate 1 to form a sub collector 2.
그 위에 컬렉터(3)를 단결정 성장한 후, 소자 격리를 위한 산화막(4)을 형성한다.After the collector 3 is grown on the single crystal, an oxide film 4 for device isolation is formed.
그 다음, 고농도의 불순물을 이온주입하여 컬렉터 싱커(sinker)(5)를 형성시키고, 베이스 박막(6)을 형성한다.Then, a high concentration of impurities are ion implanted to form a collector sinker 5 and a base thin film 6.
이어서, 다결정 실리콘막(7)과 산화막(8)을 도포하고 식각한 다음, 산화막을 도포하고 식각하여 측벽 산화막(9)을 형성함으로써 에미터와 베이스가 자기정렬(self aligned)되게 한다.Subsequently, the polycrystalline silicon film 7 and the oxide film 8 are coated and etched, and then the oxide film is applied and etched to form the sidewall oxide film 9 so that the emitter and the base are self aligned.
베이스(6) 상부에 불순물이 첨가된 다결정 실리콘(10)을 도포하고 식각하여 에미터를 형성한다.The polycrystalline silicon 10 to which impurities are added is applied on the base 6 and etched to form an emitter.
다음, 금속전극(11)을 형성하여 소자를 완성한다.Next, the metal electrode 11 is formed to complete the device.
상술한 바와 같은 제조방법에 의해 바이폴러 트랜지스터를 제조하는 경우에, 비활성 베이스로 자체저항이 큰 실리콘(7)을 사용하기 때문에 기생 베이스 저항(parasitic base resistance)(상기 실리콘(7)의 저항과 상기 실리콘(7) 및 금속(11)간의 접촉저항의 합)이 크므로 소자의 고주파 성능인 최대 진동 주파수(maximum oscillation frequency) 특성이 저하된다는 문제점이 있었다.In the case of manufacturing a bipolar transistor by the above-described manufacturing method, since parasitic base resistance (parasitic base resistance) (resistance of the silicon 7 and the Since the sum of the contact resistances between the silicon 7 and the metal 11) is large, there is a problem that the maximum oscillation frequency characteristic, which is a high frequency performance of the device, is degraded.
특히, 이 구조에서는 실리콘 에미터를 형성하기 위해 다결정 실리콘(7)을 선택적으로 식각해야 하는 어려움이 존재하게 되는 문제점도 있었다.In particular, this structure also has a problem in that it is difficult to selectively etch the polycrystalline silicon 7 to form a silicon emitter.
상기 문제점을 해결하기 위한 본 발명의 목적은 소자의 기생 베이스 저항(parasitic base resistance)을 줄이고, 에미터와 베이스를 자기정렬시킴으로써 소자의 크기를 줄여 집적도를 높일 수 있는 바이폴러 트랜지스터의 제조공정을 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention to solve the above problems is to provide a manufacturing process of a bipolar transistor that can reduce the parasitic base resistance of the device (parasitic base resistance), and to increase the degree of integration by reducing the size of the device by self-aligning the emitter and the base Is in.
상기 목적을 달성하기 위한 본 발명의 특징은 자기정렬 바이폴러 트랜지스터의 제조공정에 있어서, 실리콘 기판에 고농도의 불순물을 이온주입하여 서브컬렉터를 형성시키는 제 1 과정과, 컬렉터를 다결정 성장시키는 제 2 과정과, 소자격리를 위한 산화막을 형성시키는 제 3 과정과, 고농도의 불순물을 이온주입하여 컬렉터 싱커를 형성시키는 제 4 과정과, 베이스 박막을 형성시키는 제 5 과정과, 산화막과 질화막과 산화막을 도포하는 제 6 과정과, 산화막과 질화막과 산화막을 식각하는 제 7 과정과, 비활성 베이스 영역을 고농도의 붕소로 도핑함으로써 금속 실리사이드과의 오옴 저항을 작게 하는 제 8 과정과, 금속 실리사이드 박막을 선택적으로 단결정 성장시키는 제 9 과정과, 실리콘을 상기 금속 실리사이드 박막 위에 연속하여 단결정 성장시키는 제 10 과정과, 산화막을 식각하여 제거하고 단결정 성장된 실리콘으로 저온에서 열산화하여 산화막을 형성시키는 제 11 과정과, 산화막을 도포하고 다시 식각하여 측벽막을 형성하는 제 12 과정과, 질화막과 산화막을 차례로 식각하여 측벽막을 완성하는 제 13 과정과, 에미터 전극인 다결정 실리콘을 도포하고 불순물을 첨가하는 제 14 과정과, 식각하여 에미터를 형성하는 제 15 과정과, 절역막을 전면에 도포하고 에미터 접합을 형성하기 위한 열처리를 행하는 제 16 과정과, 절연막을 식각하여 금속접촉 부분을 정의하는 제 17 과정 및 금속을 증착하고 식각하여 소자를 완성하는 제 18 과정을 포함하는 데에 있다.A feature of the present invention for achieving the above object is a first step of forming a sub-collector by ion implantation of a high concentration of impurities into a silicon substrate in the manufacturing process of a self-aligned bipolar transistor, and a second process of polycrystalline growth of the collector And a third step of forming an oxide film for device isolation, a fourth step of forming a collector sinker by ion implantation of a high concentration of impurities, a fifth step of forming a base thin film, and applying an oxide film, a nitride film, and an oxide film A sixth process, an seventh process of etching the oxide film, the nitride film, and the oxide film, an eighth process of reducing the ohmic resistance with the metal silicide by doping the inactive base region with a high concentration of boron, and selectively single crystal growth of the metal silicide thin film. A ninth process, wherein silicon is continuously grown on the metal silicide thin film A tenth process, an eleventh process of etching and removing the oxide film and thermally oxidizing at a low temperature with single crystal grown silicon to form an oxide film, a twelfth process of applying an oxide film and etching again to form a sidewall film, and a nitride film and an oxide film A thirteenth process of sequentially etching to form a sidewall film, a fourteenth process of applying polycrystalline silicon as an emitter electrode and adding impurities, a fifteenth process of forming an emitter by etching, and applying a cutting film to the entire surface of the emitter And a sixteenth process of performing a heat treatment to form a junction, a seventeenth process of etching an insulating film to define a metal contact portion, and an eighteenth process of depositing and etching metal to complete a device.
상기 목적을 달성하기 위한 본 발명의 다른 특징은 자기정렬 바이폴러 트랜지스터의 제조공정에 있어서, 산화막과 질화막과 산화막을 도포하고 식각하는 제 1 과정과, 금속 실리사이드 박막을 선택적으로 단결정 성장하는 제 2 과정과, 실리콘을 그 위에 연속하여 성장시키는 제 3 과정과, 산화막을 식각하여 제거하는 제 4 과정과, 단결정 성장된 실리콘을 저온에서 열산화하여 산화막을 형성하는 제 5 과정 및 측벽막을 형성하는 제 6 과정을 포함하는 데에 있다.According to another aspect of the present invention for achieving the above object, a first process of coating and etching an oxide film, a nitride film, and an oxide film in a manufacturing process of a self-aligned bipolar transistor, and a second process of selectively single crystal growing a metal silicide thin film And a third process of continuously growing silicon thereon, a fourth process of etching and removing oxide film, a fifth process of thermally oxidizing single crystal grown silicon at low temperature, and a sixth process of forming sidewall film. It involves the process.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시예들을 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 바이폴러 트랜지스터의 구조를 나타낸 단면도이다.2 is a cross-sectional view showing the structure of a bipolar transistor according to the present invention.
제2도를 참조하여 본 발명에 따른 바이폴러 트랜지스터의 구조를 설명하면 다음과 같다.Referring to FIG. 2, the structure of a bipolar transistor according to the present invention will be described.
먼저, 실리콘 기판(21)에 고농도의 불순물을 이온주입하여 서브컬렉터(22)를 형성시킨다.First, a high concentration of impurities are implanted into the silicon substrate 21 to form the sub collector 22.
그리고 나서, 커렉터(23)를 다결정 성장한 후에 소자격리를 위한 산화막(24)을 형성한다.Then, after the collector 23 is polycrystalline grown, an oxide film 24 for device isolation is formed.
그 다음, 고농도의 불순물을 이온주입하여 컬렉터 싱커(25)를 형성시키고, 베이스 박막(26)을 형성한다.Next, a high concentration of impurities are ion implanted to form the collector sinker 25 and the base thin film 26 is formed.
이어서, 산화막(27), 질화막(28), 그리고 산화막을 도포하고 식각한 후, 비활성 베이스 영역을 고농도의 붕소(boron)로 도핑함으로써 금속 실리사이드과의 오믹저항(ohmic resistance)을 작게한다.Subsequently, after the oxide film 27, the nitride film 28, and the oxide film are coated and etched, the ohmic resistance with the metal silicide is reduced by doping the inactive base region with a high concentration of boron.
그런 다음, 금속 실리사이드 박막(29)을 선택적으로 단결정 성장시키고 실리콘을 그 위에 연속하여 단결정 성장시킨다.The metal silicide thin film 29 is then selectively grown single crystal and silicon is continuously grown on it.
그 후, 산화막(27)을 식각하여 제거하고 단결정 성장된 실리콘으로 저온에서 열산화하여 산화막(30)을 형성한다.Thereafter, the oxide film 27 is etched and removed, and the oxide film 30 is thermally oxidized at low temperature with single crystal grown silicon to form the oxide film 30.
그런 후, 산화막(31)을 도포하고 식각하여 측벽막을 형성한다.Thereafter, the oxide film 31 is applied and etched to form a sidewall film.
그 다음, 질화막(28)과 산화막(27)을 차례로 식각하여 측벽막을 완성한다.Next, the nitride film 28 and the oxide film 27 are sequentially etched to complete the sidewall film.
그 후에, 에미터 전극인 다결정 실리콘(32)을 도포하고 불순물을 첨가한다음 식각하여 에미터를 형성한다.Thereafter, polycrystalline silicon 32, which is an emitter electrode, is applied and impurities are added and then etched to form an emitter.
다음으로, 절연막(33)을 전면에 도포하고 에미터 접합을 형성하기 위한 열처리를 행한 후, 절연막(33)을 식각하여 그속접촉 부분을 정의 한다.Next, after the insulating film 33 is applied to the entire surface and subjected to a heat treatment for forming an emitter junction, the insulating film 33 is etched to define its fast contact portion.
그 후, 금속(34)을 증착하고 식각하여 소자를 완성한다.Thereafter, the metal 34 is deposited and etched to complete the device.
상기 제2도에 따른 한 실시예를 제3도 (a)-(g)를 통하여 제조공정을 설명한다.An embodiment according to FIG. 2 will be described with reference to FIGS. 3A through 3G.
먼저, (a)공정은 실리콘 기판(41)에 고농도의 불순물을 이온주입하여 서브컬렉터(42)를 형성한다.First, in the step (a), a high concentration of impurities are ion implanted into the silicon substrate 41 to form the sub collector 42.
그리고 나서, 컬렉터(43)를 단결정 성장한 후, 소자격리를 위한 산화막(44)을 형성한다.Then, after the collector 43 is grown by single crystal, an oxide film 44 for device isolation is formed.
그 다음, 고농도의 불순물을 이온주입하여 컬렉터 싱커(45)를 형성시키고, 베이스 박막(46)을 형성한다.Then, a high concentration of impurities are implanted into the ion to form the collector sinker 45 and the base thin film 46 is formed.
그 후, 산화막(47), 질화막(48), 산화막(49)을 차례로 도포한다.Thereafter, the oxide film 47, the nitride film 48, and the oxide film 49 are applied in this order.
(b)는 (a) 공정 후에 감광막으로 마스킹(masking)하여 산화막(47), 질화막(48), 산화막(49)을 차례로 식각하는 공정이다.(b) is a step of sequentially etching the oxide film 47, the nitride film 48, and the oxide film 49 by masking the photosensitive film after the step (a).
(c)는 (b)공정 후에 금속 실리사이드(50)를 선택적 단결정 성장하고 실리콘(51)을 선택적 단결정 성장시키는 공정이다.(c) is a step of selectively growing single crystals of the metal silicide 50 and growing of silicon 51 after the step (b).
(d)는 (c)공정 후에 산화막(49)을 제거하고, 선택적으로 단결정 성장된 실리콘(51)을 저온에서 열산화하여 산화막(52)을 형성하는 공정이다.(d) is a step of forming the oxide film 52 by removing the oxide film 49 after the step (c), and selectively thermally oxidizing the silicon 51 that has grown single crystal at low temperature.
(e)는 (d)공정 후에 산화막(53)으로 도포하고 식각한 후, 질화막(48)과 산화막(47)을 식각하여 측벽막을 형성하는 공정이다.(e) is a step of forming a sidewall film by etching the nitride film 48 and the oxide film 47 after applying and etching the oxide film 53 after the step (d).
(f)는 (e)공정 후에 컬렉터 위의 베이스 박막(46)을 제거하고, 다결정 실리콘(54)을 도포한 후, 불순물을 주입하고 식각하여 에이터 전극을 정의한다.(f) removes the base thin film 46 on the collector after the step (e), applies polycrystalline silicon 54, and then implants and etches the impurities to define the electrode electrode.
(g)는 (f)공정 후에 절연막(55)을 도포하고, 접촉부분을 정의한 후, 금속(56)을 증착하고 식각한다.In (g), after the step (f), the insulating film 55 is applied, the contact portion is defined, and the metal 56 is deposited and etched.
이상과 같은 구성으로 된 본 발명은 소자의 비활성베이스로 금속실리사이드 박막을 사용하여 기생 베이스 저항이 작으며, 에미터와 베이스가 자기정렬되게 함으로써 재현성이 높고 소자의 크기를 줄여 초고집적화가 가능한 초고속 바이폴러 소자를 제조하엿고, 또한 이종접합 바이폴러 소자도 동시에 가능하게 되었으므로, 실리콘 바이폴러 트랜지스터의 동작속도 한계를 뛰어넘어서 새로운 초고속 소자의 영역을 개발하였다.According to the present invention having the above structure, the parasitic base resistance is small by using a metal silicide thin film as an inactive base of the device, and the emitter and the base are self-aligned, so that the reproducibility is high and the size of the device is reduced, so that the ultra-high integration is possible. Since a polar device has been manufactured, and a heterojunction bipolar device is also enabled at the same time, a new ultrafast device area has been developed beyond the operating speed limit of a silicon bipolar transistor.
이 결과 고속정보처리 및 저전력을 요하는 고속 컴퓨터, 통신기기 등 정보처리 시스템에서 실리콘 바이폴러 트랜지스터의 한계를 대폭 확장시켜서 실리콘 바이폴러 트랜지스터의 응용범위가 화합물 고속소자의 영역까지 확장되게 되었다.As a result, the limitations of silicon bipolar transistors have been greatly expanded in information processing systems such as high speed computers and communication devices requiring high speed information processing and low power, thereby extending the application range of silicon bipolar transistors to the area of compound high-speed devices.
물론 화합물 고속소자의 전범위를 다 포함하는 것은 아니지만 값싸고 안전하며 집적화가 용이한 실리콘 고속 바이폴러 트랜지스터가 앞으로 어느 정도 화합물 고속소자를 대체하게 될 것이다.Of course, not all the range of compound high-speed devices, but cheap, safe and easy to integrate silicon high-speed bipolar transistors will replace the compound high-speed device to some extent in the future.
그러므로, 상술한 바와 같은 본 발명은 비활성 베이스로 금속 실리사이드 박막을 사용하기 때문에 소자의 기생 베이스 저항이 작으며, 에미터와 베이스를 자기정렬시킴으로써 재현성이 높고 소자의 크기를 줄여 집적도를 높일 수 있고, 비활성 베이스로 금속 실리사이드 박막을 단결정으로 성장시키기 때문에 금속 샐리사이드(metal salicide) 형성공정에 의해 제조된 것보다 실리콘과 금속 실리사이드 계면의 고온반응에 의해 발생하는 계면 모양이 보다 더 평평하므로 계면 누설 전류가 작아지고, 계면의 면적이 작아지므로 베이스-걸렉터 접합용량도 또한 감소하게 되는 등 소자의 고주파 응답 특성이 우수하다는 데에 그 효과가 있다.Therefore, the present invention as described above uses a metal silicide thin film as the inactive base, the parasitic base resistance of the device is small, the self-aligned emitter and the base is high reproducibility, and the size of the device can be reduced to increase the integration, Since the metal silicide thin film is grown as a single crystal with an inert base, the interface leakage current is increased because the interface shape generated by the high temperature reaction of the silicon and metal silicide interface is flatter than that produced by the metal salicide forming process. The effect is that the high frequency response characteristics of the device are excellent, such that the size of the interface is small and the base-collector junction capacitance is also reduced.
상기에서는 일 실시예의 제조공정을 설명하였으나 본 발명의 사상에 벗어남이 없이 다르게 실시할 수도 있음은 이 분야에 통상적인 지식을 가진 자는 쉽게 알 수 있을 것이다.In the above description of the manufacturing process of one embodiment, it will be apparent to those skilled in the art that the present invention may be implemented differently without departing from the spirit of the present invention.
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