JPH06291132A - Bipolar transistor and fabrication thereof - Google Patents

Abstract

PURPOSE:To decrease parasitic capacitances between base-collector and base- substrate by employing a structure, being determined by the epitaxial film thickness, in a graft base region. CONSTITUTION:The bipolar transistor comprises a first impurity layer of first conductivity type formed on a semiconductor substrate, a first insulation film 5 touching the impurity layer, a first electric conductive film 6 of second conductivity type touching the first insulation film, and a second electric conductive film 8 of second conductivity type for connecting the first conductive film 6 of second conductivity type with the first impurity layer within an opening defined by a second insulation film 7 touching the first conductive film 6 and simultaneously forming the base of transistor. When a structure being determined by the epitaxial film thickness is employed in a graft base region, parasitic capacitance can be decreased between base-collectors and a high operating speed can be achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, further large scale and high performance LSIs have been demanded, and further higher performance of bipolar transistors has been demanded. This means shortening the base running time by reducing the base width,
This is achieved by reducing the base resistance and the parasitic capacitance represented by the capacitance between the base and the collector, but these are related to each other and need to be optimized.

With the reduction of the emitter width due to miniaturization, the diffusion layer (so-called graft base) region for taking out the base electrode and the link base region connecting the intrinsic base region and the graft base are larger in area than the intrinsic base region. This is large, and it is essential to reduce this parasitic capacitance component for speeding up. On the other hand, reduction of the link base region (width) causes deterioration of characteristics between the emitter and base of the transistor and deterioration of high-frequency characteristics, and reduction of the graft base region has a problem in terms of process stability. There are points.

The above problem will be described in detail with reference to the conventional example shown in FIG. This figure is a cross-sectional view of the upper portion of the silicon substrate 1 in the vicinity of the emitter 15 and the base 13 of a conventional high speed bipolar transistor (NPN). This structure employs a so-called double polysilicon structure in which the emitter and base electrodes are formed of two layers of polysilicon 6 and 14, and each electrode is separated by a side wall 16 of an insulating film to form a base-collector. The capacity has been significantly reduced. Further, a link base for connecting the base and the base electrode is formed.

However, in the example shown in the figure, the width of the P ⁺ graft base 12 is 400 nm (on the design pattern) with respect to the emitter width of 300 nm, and 1100 nm after diffusion.
The area that becomes a parasitic component is overwhelmingly wide. In order to increase the speed, it is necessary to make the graft base region sufficiently narrow without hindering the characteristics of the link base connection.

[0006]

In order to realize a high performance bipolar transistor, the present invention secures a margin of lithography when forming a graft base for connecting a base lead electrode portion made of polysilicon and a link base by opening a window. In order to provide a bipolar transistor having a wider graft base region and a large parasitic capacitance, the parasitic capacitance between the base and the collector is significantly reduced, thereby achieving further speedup, and a manufacturing method thereof. It is something to do.

[0007]

According to a first aspect of the present invention, a first conductivity type first impurity layer formed on a semiconductor substrate and a first insulating film in contact with the impurity layer are provided. A second electrically conductive film of a second conductivity type in contact with the first insulating film, and a second electrically conductive film in an opening formed by a second insulating film in contact with the electrically conductive film. A bipolar transistor composed of a second electrically conductive film of a second conductivity type which connects the first electrically conductive film and the first impurity layer and at the same time forms the base of the transistor. To achieve.

According to a second aspect of the present application, a second conductive layer which connects the opening, the first electrically conductive film of the second conductive type, and the first impurity layer and at the same time forms a base of a transistor. Laterally separated by a second electrically conductive film of the mold and a third insulating film formed inside the second electrically conductive film,
The bipolar transistor according to claim 1, wherein the third electrically conductive film of the first conductivity type which is vertically connected to the second electrically conductive film constitutes an emitter or an emitter diffusion source. To achieve.

The invention according to claim 3 of the present application is the bipolar transistor according to claim 2, wherein the third electrically conductive film has a larger energy band gap than the second electrically conductive film. Is achieved.

According to a fourth aspect of the present invention, the second electrically conductive film of the second conductivity type has a multilayer structure of a polysilicon layer doped with P type impurities and a silicide layer. The described bipolar transistor achieves the above object.

According to a fifth aspect of the present application, a first conductivity type first impurity layer formed on a semiconductor substrate, a first insulating film in contact with the impurity layer, and the first impurity layer A first electric conduction of the second conductivity type in an opening formed by a first electric conduction film of a second conduction type in contact with the insulation film and a second insulation film in contact with the electric conduction film. A method of manufacturing a bipolar transistor comprising a second electrically conductive film of a second conductivity type for connecting a film and a first impurity layer and at the same time forming a base of the transistor, wherein a second insulating film is formed on the entire surface. After the formation, a third insulating film is formed on the entire surface, the insulating film is left only on the sidewalls around the opening by etching back, and after smoothing, the entire surface is etched back to form a second insulating film on the bottom of the opening. Of the first insulating film without leaving the conductive film of the first insulating film above the second insulating film. A method of manufacturing a bipolar transistor, characterized in that connected to the conductive film, thereby is to achieve the above object.

[0012]

[Operation] According to the present invention, specifically, the base electrode lead-out portion of polysilicon and the intrinsic base region are connected at the same time when the intrinsic base region is formed by epitaxy (CVD), and the fineness determined by the film thickness is determined. Stable connection across the width, greatly reducing the parasitic capacitance. That is, according to the present invention, the graft base can be formed in a self-aligned manner without considering the lithography margin, the graft base area can be significantly reduced, and the intrinsic base area and the polysilicon can be stably formed. Can be connected to the base extraction electrode.

[0013]

EXAMPLES Specific examples of the present invention will be described below with reference to FIGS. 1 and 2 to 13. These figures are NP
FIG. 6 is a cross-sectional view of the upper portion of the silicon substrate of the emitter and base of the N transistor.

First, the steps of this embodiment will be described with reference to FIGS. As shown in FIG. 2, after the N ⁺ collector buried layer 2 is formed on the P type substrate 1, the N type epitaxial layer 3 is grown as shown in FIG.

After that, as shown in FIG. 4, the insulating film is separated by the insulating film 4. The example shown in the figure shows what is called trench isolation in which an insulator is embedded after forming a groove. Further, the SiO ₂ insulating film 5 is formed to a thickness of 300
m. Since the film thickness acts as a parasitic capacitance between the base extraction electrode and the collector (epitaxial layer), the thicker the film, the better. However, the thicker the film, the larger the step becomes, which is a problem when the electrode is formed.

Now referring to FIG. After forming the insulating film 5,
The polysilicon layer 6 is formed to 100 nm by the CVD method. Since this polysilicon layer 6 will be used as a take-out electrode such as a base after the completion of the device, it is doped with P-type impurities to have a low resistance. Unnecessary portions of the polysilicon layer 9 are removed by lithography and dry etching, and window opening etching is performed.

Next, as shown in FIG. 6, the insulating film 7 (S
iO ₂ ) is formed to a thickness of 300 nm by the CVD method.

Next, as shown in FIG. 7, lithography and RIE (Reactive Ion Etchinn) are performed.
By the method g), a window which becomes an active region of the base and the emitter is formed. At the same time, an electrode lead-out (not shown) of the collector can be formed.

Next, referring to FIG. Low temperature (500-6
A P-type conductive thin film epitaxy film 8 is formed on the entire surface by high vacuum epitaxy (00 ° C.). Since this epitaxy film 8 forms an intrinsic base region, it has a specific resistance of 10
About kΩ to 20 kΩ / □ is desirable, and the thickness is about 50 nm to 80 nm in order to improve high frequency characteristics. In the side surface of the opening of the epitaxy film 8, the influence of the underlying layer is polysilicon, but the region is on the order of the film thickness, and there is no influence on the intrinsic base region due to separation by the sidewall insulating film described later. Also, at the edge of the peripheral portion of the opening, the junction is formed in the single crystal due to the diffusion of the P-type impurity toward the N epitaxy layer side, so that the leak current is of a negligible order.

FIG. 9 is an enlarged view of the main part of FIG. Hereinafter, an enlarged view will be described.

Further, the insulating film 9 is formed by CVD to 100
nm, and leave a sidewall-like film around the opening by the RIE method. As a result, the structure shown in FIG. 10 is obtained.

As shown in FIG. 11, the entire surface including the opening is smoothed by applying a photoresist or the like. Furthermore R
By the IE method or the chemical mechanical polishing method,
Etch back is performed until the insulating film 7 is exposed. Figure 11
In the figure, E indicates a region to be etched back.

Further, using the photoresist or the like remaining in the opening as a mask, the epitaxy layer 8 (which is polysilicon in the vicinity) in the opening is etched back by the RIE method. As a result, the structure shown in FIG. 12 is obtained. This protects the intrinsic base region,
The connection with the base extraction electrode is completed.

As shown in FIG. 13, an insulating film 11 is formed to a thickness of 100 nm by the CVD method and etched back by the RIE method to fill the upper portion of the epitaxy layer (which is polysilicon in the vicinity) around the opening.

Subsequently, the polysilicon 12 for forming the emitter diffusion layer is formed to 100 nm by the CVD method.
Formed and As is 1E16 / cm ² by ion implantation.
Implantation and annealing at 800 ° C. for 30 minutes in a nitrogen atmosphere. Furthermore, RTA (Rapid Thermal An
The emitter-base junction is stably formed by the "neal". This results in the bipolar transistor structure of FIG. Hereinafter, the metal electrode forming step is performed.

The present invention is not limited to the above-mentioned embodiments, but various modifications can be made based on the technical idea of the present invention.

For example, in the step shown in FIG. 5, by adding a silicide (for example, titanium silicide) layer to the polysilicon layer 6, the resistance of the base take-out portion can be reduced and the speed can be increased.

Further, the combination of the intrinsic base shown in FIG. 8 and the emitter shown in FIG. 1 to form the emitter having a larger bandgap can improve the injection efficiency and reduce the base resistance to achieve high speed. Contribute to This combination is possible by using polysilicon (SiOxPy) containing oxygen and an N-type impurity (for example, phosphorus) on the emitter side and Ge doping on the base side for one or both of them.

Further, by reducing the thickness of the insulating film in FIGS. 11 and 13, it is possible to further reduce the parasitic region other than the intrinsic base.

As described above, in this embodiment, the graft base and the link base of the bipolar transistor and the parasitic region other than the intrinsic base are further reduced by reducing the insulating film thickness in FIGS. 10 and 13. Can be reduced.

[0031]

As described above, according to the present invention, in the formation of the graft base, the link base, and the base of the bipolar transistor, the structure in which the graft base region is determined by the film thickness of the epitaxy significantly reduces the gap between the base and collector. And, it has become possible to reduce the parasitic capacitance between the base and the sub. As a result, the operating speed can be increased.

[Brief description of drawings]

1 shows the structure of Example 1. FIG.

FIG. 2 shows a process of Example 1 (1).

FIG. 3 shows a process of Example 1 (2).

FIG. 4 shows the process of Example 1 (3).

FIG. 5 shows a process of Example 1 (4).

FIG. 6 shows the process of Example 1 (5).

FIG. 7 shows the process of Example 1 (6).

FIG. 8 shows the process of Example 1 (7).

FIG. 9 shows the process of Example 1 (enlargement of (7)).

FIG. 10 shows a process of Example 1 (8).

FIG. 11 shows a process of Example 1 (9).

FIG. 12 shows the process of Example 1 (10).

FIG. 13 shows a process of Example 1 (11).

FIG. 14 shows a conventional example.

[Explanation of symbols]

 1 Substrate 5 First Insulating Film 6 First Electrically Conductive Film 7 Second Insulating Film 8 Second Electrically Conductive Film

Claims (5)

[Claims] 1. A first impurity layer of a first conductivity type formed on a semiconductor substrate, a first insulating film in contact with the impurity layer, and a second insulating film in contact with the first insulating film. Conductive type 1
In the opening formed by the electric conductive film and the second insulating film in contact with the electric conductive film, the first electric conductive film of the second conductivity type and the first impurity layer are connected to each other, and A bipolar transistor composed of a second electrically conductive film of a second conductivity type forming a base. 2. A second conductive type second conductive film which connects the opening, the second conductive type first conductive film and the first impurity layer and simultaneously forms a base of a transistor. And a third insulating film formed inside the second electrically conductive film, the first electrically conductive type third electrically conductive film is separated in the lateral direction, and is vertically connected to the second electrically conductive film. The bipolar transistor according to claim 1, wherein the element constitutes an emitter or an emitter diffusion source. 3. The bipolar transistor according to claim 2, wherein the third electrically conductive film has a larger energy band gap than the second electrically conductive film. 4. The bipolar transistor according to claim 1, wherein the second electrically conductive film of the second conductivity type has a multilayer structure of a polysilicon layer doped with P type impurities and a silicide layer. 5. A first impurity layer of a first conductivity type formed on a semiconductor substrate, a first insulating film in contact with the impurity layer, and a second insulating film in contact with the first insulating film. Conductive type 1
In the opening formed by the electric conductive film and the second insulating film in contact with the electric conductive film, the first electric conductive film of the second conductivity type and the first impurity layer are connected to each other, and A method of manufacturing a bipolar transistor comprising a second conductive type second electrically conductive film forming a base, comprising: forming a second insulating film on the entire surface and then forming a third insulating film on the entire surface. By etching back, the insulating film is left only on the side wall around the opening, and after smoothing, the entire surface is etched back to leave the second conductive film at the bottom of the opening and the upper part of the second insulating film. A method for manufacturing a bipolar transistor, characterized in that the bipolar transistor is connected to the first conductive film without being left behind.