JPH11340326A - Method for manufacturing semiconductor device - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor device capable of preventing a short circuit between an impurity diffusion layer and a semiconductor substrate due to a wiring layer and an increase in junction leak and achieving miniaturization without considering the alignment accuracy of contact holes. To provide a manufacturing method. After opening a contact hole on an impurity diffusion layer, a silicon oxide film is formed by a vapor phase growth method to fill a groove formed simultaneously with the opening of the contact hole. After that, the entire surface of the silicon oxide film 11 is etched except for the inside of the groove 10 and the side surface of the contact hole 9, and then a metal film is deposited and patterned to form a wiring layer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a buried element isolation region.

[0002]

2. Description of the Related Art A description will be given, with reference to the drawings, of a conventional semiconductor device using a buried element isolation method, in which a matching margin between a diffusion layer region and a contact hole is 0 μm. First, as shown in FIG.
A silicon oxide film 102 of about 5 nm is formed, and thereafter,
Polycrystalline silicon 103 is formed to a thickness of about 400 nm. Next, a resist 104 is formed and patterned. next,
Using the resist 104 as a mask, the polycrystalline silicon 103 and the silicon oxide film 102 are etched. Next, the semiconductor substrate 101 is etched to form a trench 105.

[0003] Next, as shown in FIG. 3 (b), after removing the resist 104, a silicon oxide film 106 having a thickness of about 1000 nm is formed on the surface by a vapor phase growth method, and the trench 105 is filled. Next, using the polycrystalline silicon 103 as a stopper material, the silicon oxide film 106 on the semiconductor substrate 101 is removed by a polishing method and flattened.

Next, as shown in FIG. 3C, the semiconductor substrate 101 is protected by a silicon oxide film 102, and the entire surface of the polycrystalline silicon 103 is etched by an isotropic etching method. Next, the silicon oxide film 102 is removed by an ammonium fluoride etching method.

Next, as shown in FIG. 3D, an N-type impurity is added to the semiconductor substrate 101 by an ion implantation method, and thermal diffusion is performed to form an impurity diffusion layer 107. Next, as shown in FIG. 3E, a silicon oxide film 108 is formed to a thickness of about 400 nm. Next, the silicon oxide film 1 on the impurity diffusion layer 107 is formed by lithography.
08 is etched to open a contact hole 109. Next, the wiring layer 110 is formed on the surface.

[0006]

Conventionally, LSI (Large)
With the miniaturization of the memory cell array of a scale integrated circuit, the area of the impurity diffusion layer region has also been reduced, and it has become difficult to provide a sufficient margin for the impurity diffusion layer 107 when the contact hole 109 is formed. For example, when a contact hole 109 of 0.25 μm square is formed in the impurity diffusion layer 107 having a line width of 0.25 μm, assuming that an alignment margin is provided by 0.1 μm on each side,
Impurity diffusion layer 1 only in opening of contact hole 109
07 has a width of 0.45 μm, which impedes miniaturization.

However, it is difficult to reliably control the misalignment between the impurity diffusion layer 107 and the contact hole 109. If there is not enough alignment margin, the contact hole 109 deviates from the impurity diffusion layer 107 and the element isolation region. Over the trench 105.
That is, when the silicon oxide film 108 serving as an interlayer insulating film for opening the contact hole 109 is etched, the silicon oxide film 106 in the trench 105 adjacent to the impurity diffusion layer 107 is also etched. Semiconductor substrate 101 that has not been
May be exposed. The wiring layer 110 as it is
Is formed, the semiconductor substrate 101 and the impurity diffusion layer 107 are formed.
However, there is a problem that the short circuit may occur or the junction leak may increase.

FIG. 4 shows an example of a problem of the conventional semiconductor device. As shown in FIG.
09 and the impurity diffusion layer 107, the region of the impurity diffusion layer 107 is small, or the contact hole 109
Is large, the contact hole 109 deviates from above the impurity diffusion layer 107 and covers the trench 105 in the element isolation region, and when the silicon oxide film 108 is etched, the contact hole 109 in the trench 105 in the element isolation region is removed. A part of the silicon oxide film 106 is simultaneously etched to form a groove 111. Then, FIG.
As shown in FIG.
10 is formed, and when the inside of the groove 111 is filled with a wiring material,
There is a problem that the impurity diffusion layer 107 and the semiconductor substrate 101 thereunder are short-circuited via the wiring layer 110.

In particular, when the element isolation region is formed by the burying method, the LOCOS (Local Oxidation of Silico) is used.
There is a high possibility that a deep groove is formed as compared with the case formed by the n) method, and there is a problem that the groove becomes deeper as the amount of etching over when the contact hole 109 is opened increases.

In view of the above circumstances, the present invention prevents a short circuit or an increase in junction leak between an impurity diffusion layer and a semiconductor substrate by a wiring layer, and achieves miniaturization without considering the alignment accuracy of contact holes. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be used.

[0011]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: filling a concave portion of a semiconductor substrate with a first insulating film; Forming an interlayer insulating film on the surface of the semiconductor substrate; removing the first insulating film and the interlayer insulating film on the semiconductor substrate adjacent to the first insulating film to form a contact hole; Forming a second insulating film, etching the second insulating film to expose a part of the semiconductor substrate, and electrically connecting the semiconductor substrate to a part of the semiconductor substrate in the contact hole. Forming a wiring layer. Further, it is preferable that the method further includes, after the step of forming the first insulating film, a step of ion-implanting a part of the semiconductor substrate to form an impurity diffusion layer. Further, it is preferable that the second insulating film remains on the side wall of the contact hole. A step of forming a groove in an element isolation region adjacent to an element region of the semiconductor substrate; a step of filling a first insulating film in the groove; and implanting ions into the element region to form an impurity diffusion layer And forming an interlayer insulating film on the first insulating film and the impurity diffusion layer; and forming a contact hole exposing the impurity diffusion layer by removing the interlayer insulating film on the element region and the trench. Forming, forming a second insulating film on a side surface of the contact hole, and forming a wiring layer electrically connected to the precursor impurity diffusion layer in the contact hole. There is a method of manufacturing a semiconductor device characterized by the following. A step of forming a first groove in a semiconductor substrate of a first conductivity type; a step of filling a first insulating film in the first groove; Implanting an impurity of the second conductivity type to form an impurity diffusion layer, and forming an interlayer insulating film on the surface;
A contact hole including a second groove newly formed in the first insulating film by removing a part of the interlayer insulating film and the first insulating film on the impurity diffusion layer and the first groove; Forming a second insulating film in a second groove; removing the second insulating film to expose the impurity diffusion layer; and forming the impurity diffusion layer in the contact hole. Forming a wiring layer electrically connected to the layer. Further, in the step of removing the second insulating film, it is preferable that the second insulating film is removed by etching the entire surface. Further, it is preferable that the second insulating film is a silicon oxide film. Preferably, the second insulating film is a silicon nitride film.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings. FIG. 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 2 of about 25 nm is formed on a P-type semiconductor substrate 1.
Is formed, and then polycrystalline silicon 3 is formed to a thickness of about 400 nm. Next, a resist 4 is formed and patterned. Next, using the resist 4 as a mask, the polysilicon 3
And the silicon oxide film 2 is etched. Next, the semiconductor substrate 1 is etched to form a trench 5.

Next, as shown in FIG. 1B, after the resist 4 is removed, a silicon oxide film 6 of about 1000 nm is formed on the surface by a vapor phase growth method, and the trench 5 is buried. Next, using the polycrystalline silicon 3 as a stopper material, the silicon oxide film 6 on the semiconductor substrate 1 is removed by a polishing method and flattened.

Next, as shown in FIG. 1C, the semiconductor substrate 1 is protected by a silicon oxide film 2 and the entire surface of the polycrystalline silicon 3 is etched by an isotropic etching method. Next, the silicon oxide film 2 is removed by an ammonium fluoride etching method. Next, an N-type impurity, for example, phosphorus is added to the semiconductor substrate 1 by an ion implantation method, and thermal diffusion is performed to form an impurity diffusion layer 7 in the semiconductor substrate 1.

Next, as shown in FIG. 1D, a silicon oxide film 8 is formed on the surface to a thickness of about 400 nm. Next, the silicon oxide film 8 on the impurity diffusion layer 7 is etched by lithography to open a contact hole 9. At this time, a part of the silicon oxide film 6 in the trench 5 is simultaneously etched to form a groove 10.

Next, as shown in FIG. 1E, a silicon oxide film 11 is formed on the surface by, for example, about 1
It is formed as thin as 0 nm or less. As a result, the inside of the trench 10 is filled with the silicon oxide film 11. Next, the entire surface of the silicon oxide film 11 is etched by RIE (Reactive Ion Etching) while leaving the inside of the groove 10 and the side surface of the contact hole 9.

Next, as shown in FIG. 1F, a metal is deposited and patterned to form a wiring layer 12.
With the above, the manufacturing process of the semiconductor device according to the first embodiment of the present invention is completed.

Even if trench 10 deeper than impurity diffusion layer 7 is formed in trench 5 in the element isolation region due to misalignment of impurity diffusion layer 7 and contact hole 9, impurity diffusion layer 7 is buried with silicon oxide film 11. And the semiconductor substrate 1 are electrically insulated from each other, so that a short circuit and an increase in junction leak can be prevented.

Further, conventionally, when a part of the element isolation region by the LOCOS method is lost due to misalignment of a contact hole, a technique of re-injecting and diffusing an impurity into a semiconductor substrate at the defective part is known. Since the exposed surface of the formed element isolation region is likely to be a deep groove, ions are not sufficiently implanted, and a sufficient impurity diffusion layer cannot be formed. Also, for example, CM
In the case of manufacturing an OS type semiconductor device, both N-type and P-type ion implantation are required, so that PEP (Photo Engraving Pr
ocess) There was a problem that the number of processes increased. However, in the present invention, it is not necessary to use a mask, and it is only necessary to increase the number of steps of forming the silicon oxide film 11 on the entire surface and then etching the entire surface. Therefore, an increase in the number of manufacturing steps can be minimized. .

Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention.

FIG. 1A shows the state before the impurity diffusion layer is formed.
The description is omitted because it is the same as that of (c). However, the same components are denoted by the same reference numerals. Next, as shown in FIG. 2A, a silicon oxide film 8 is formed on the surface.
Of about 400 nm. Next, the silicon oxide film 8 on the impurity diffusion layer 7 is etched by lithography to open a contact hole 9. At this time, a part of the silicon oxide film 6 in the trench 5 is simultaneously etched, so that a groove 21 is formed. The groove 21 in this case is wider than the groove formed in the first embodiment.

Next, as shown in FIG. 2B, a silicon oxide film 22 is formed on the surface to a thickness of about 10 nm by a vapor growth method.
The following is formed. At this time, since the width of the groove 21 is larger than twice the thickness of the silicon oxide film 22, the groove 21 is not buried, and the silicon oxide film 22 is
1 is formed on the inner wall.

Next, as shown in FIG. 2C, the entire surface of the silicon oxide film 22 is etched by the RIE method, leaving the side surfaces of the contact hole 9 and the groove 21, so that the impurity diffusion layer 7 appears. .

Next, as shown in FIG. 2D, a metal is deposited on the surface and patterned to form a wiring layer 12. Thus, the manufacturing process of the semiconductor device according to the second embodiment of the present invention is completed.

When the width of the groove 21 formed in the trench 5 is large as in the semiconductor device according to the second embodiment, it is not necessary to bury the groove 21 and the silicon oxide film is so small that the side surface of the impurity diffusion layer 7 does not appear. Since it is sufficient to form the semiconductor device 22, the semiconductor device according to the present invention can be realized without increasing the manufacturing time.

The thicknesses of the silicon oxide films 11 and 22 are not limited to those in the first and second embodiments, but are preferably formed thin so as to be easily removed. Also, grooves 10,
It is possible to use not only the silicon oxide films 11 and 22 in the inside 21 but also a silicon nitride film or the like having an excellent withstand voltage as long as it is an insulating film.

[0028]

According to the present invention, in a method of manufacturing a semiconductor device having a buried type element isolation region, a trench formed in a trench when a contact hole is opened is buried with an insulating film to thereby improve impurity diffusion. Short circuit between the layer and the semiconductor substrate and increase in junction leak can be prevented. Further, it is possible to manufacture a miniaturized semiconductor device without considering the alignment accuracy of the contacts.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of a conventional semiconductor device.

FIG. 4 is a diagram showing a problem example of a conventional semiconductor device.

[Explanation of symbols]

1, 101: semiconductor substrate, 2, 6, 8, 11, 22, 102, 106, 108: silicon oxide film, 3, 103: polycrystalline silicon, 4, 104: resist, 5, 105: trench, 7, 107 ... impurity diffusion layer, 9, 109 ... contact hole, 10, 21, 111 ... groove, 12, 110 ... wiring layer

Claims (8)

[Claims] A step of filling a concave portion of the semiconductor substrate with a first insulating film; a step of forming an interlayer insulating film on the surface of the first insulating film and the surface of the semiconductor substrate; Removing the interlayer insulating film on the semiconductor substrate adjacent thereto and forming a contact hole; forming a second insulating film in the contact hole; and etching the second insulating film. A method of manufacturing a semiconductor device, comprising: exposing a part of the semiconductor substrate; and forming a wiring layer in the contact hole, the wiring layer being electrically connected to the part of the semiconductor substrate. . 2. The semiconductor device according to claim 1, further comprising, after the step of forming the first insulating film, a step of ion-implanting a part of the semiconductor substrate to form an impurity diffusion layer. Manufacturing method. 3. The method according to claim 1, wherein the second insulating film remains on a side wall of the contact hole. 4. A step of forming a groove in an element isolation region adjacent to an element region of a semiconductor substrate, a step of filling a first insulating film in the groove, and implanting ions into the element region to diffuse impurities. Forming a layer; forming an interlayer insulating film on the first insulating film and the impurity diffusion layer; removing the interlayer insulating film on the element region and the trench to expose the impurity diffusion layer Forming a contact hole, forming a second insulating film on a side surface of the contact hole, and forming a wiring layer electrically connected to the impurity diffusion layer in the contact hole. A method for manufacturing a semiconductor device, comprising: 5. A step of forming a first groove in a semiconductor substrate of a first conductivity type, a step of filling a first insulating film in the first groove, and a step of adjoining the first groove. Implanting a second conductivity type impurity into the semiconductor substrate to form an impurity diffusion layer; forming an interlayer insulating film on the first insulating film and the impurity diffusion layer; Forming a contact hole including a second groove newly formed in the first insulating film by removing a part of the interlayer insulating film and the first insulating film on the first groove; Second
Forming a second insulating film in the trench, removing the second insulating film to expose the impurity diffusion layer, and electrically connecting the impurity diffusion layer in the contact hole Forming a wiring layer. 6. The method according to claim 5, wherein in the step of removing the second insulating film, the second insulating film is removed by etching the entire surface. 7. The method for manufacturing a semiconductor device according to claim 1, wherein said second insulating film is a silicon oxide film. 8. The method for manufacturing a semiconductor device according to claim 1, wherein said second insulating film is a silicon nitride film.