JP2797774B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high performance bipolar transistor and a bipolar integrated circuit having small parasitic capacitance and base resistance.

[0002]

2. Description of the Related Art The performance of bipolar devices has been greatly improved in recent years.

[0003] Advances in lithography have significantly improved the pattern miniaturization method to reduce base resistance and parasitic capacitance. In addition, a shallow emitter
A base junction is formed to reduce the carrier's base travel time. As a result, significant improvement in characteristics is expected.

Next, an NPN transistor having a P-type base layer formed of Si-MBE will be described with reference to FIG.

First, an N-type epitaxial layer 4 is grown on an N ⁺ -type silicon substrate 1 and an isolation oxide film 5 is formed, and then a P-type semiconductor layer 7 serving as a base is grown. Next, after forming the insulating film 11, a P ⁺ type semiconductor layer 15 serving as a graft base is formed. Next, after the insulating film 12 is formed, the N ⁺ type polysilicon 10 is formed. Next, the emitter electrode 17 and the base electrode 18 made of aluminum
Is formed to complete the element portion.

Usually, the P ⁺ type graft base 15 for reducing the base resistance is formed deeper than the intrinsic base 7. Therefore, the parasitic capacitance between the collector and the base is increased by the fringe capacitance.

On the other hand, it is desirable that the graft base be as close to the emitter as possible in order to reduce the base resistance.
, The capacitance between the emitter and the base increases, and the breakdown voltage between the emitter and the base decreases.

Further, the distance between the emitter and the graft base is determined by the distance in which the high concentration P-type layer of the graft base diffuses in the lateral direction and misalignment. Therefore, there is a limit to the reduction of the base resistance and the improvement of the transistor characteristics due to the distance between the emitter and the graft base even if the pattern miniaturization advances.

[0009]

However, there is a limit to the pattern miniaturization due to the graft base for reducing the base resistance. Further, reduction of parasitic capacitance such as base resistance and collector-base capacitance cannot be realized, which hinders improvement of characteristics.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
An intrinsic base is formed on the collector layer of the bipolar transistor, an emitter and a sidewall of the emitter are formed on the intrinsic base, and a side surface of the intrinsic base and a side wall of the intrinsic base are self-aligned with the emitter and the sidewall. A graft base made of a single crystal doped with a high concentration of impurities and in contact with the upper surface of the collector layer is formed.

[0011]

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of sequentially growing an opposite conductivity type semiconductor layer and at least one one conductivity type semiconductor layer on a one conductivity type semiconductor substrate; Forming a sidewall on the side surface of the one-conductivity-type semiconductor layer after selectively etching a part of the first-conductivity-type semiconductor layer; Doping step.

[0013]

The first related art EXAMPLES Introduction to the invention,
FIGS. 1 (a) described with reference ~ to (d). As shown in FIG. 1A , an N-type epitaxial layer 4 is grown on an N ⁺ -type semiconductor substrate 1 to form an isolation oxide film 5. Next, after growing a P-type semiconductor layer 7 serving as a base and an N ⁺ -type semiconductor layer 9 serving as an emitter, an insulating film 11 is deposited and a photoresist 13 is patterned. Next, as shown in FIG. 1B, the insulating film 1 is
1 and the N ⁺ type semiconductor layer 9 are etched. At this time, RIE is generally used, but wet etching with a mixed solution of nitric acid and sulfuric acid can be used to increase the selectivity between the N ⁺ type semiconductor layer 9 and the P type semiconductor layer 7. Next, as shown in FIG. 1C, an insulating film is grown on the entire surface and then etched back by anisotropic etching.
A sidewall 14 made of an insulating film is formed.

Next, the insulating film 11 and the side wall 1
Using P.4 as a mask, boron (boron) is ion-implanted to form a P ⁺ type semiconductor layer 14 serving as a graft base. Instead of ion implantation, low-temperature diffusion using a polyboron film manufactured by Tokyo Ohka Kogyo Co., Ltd. can also be used. Finally, as shown in FIG. 2D, an interlayer insulating film 16 is deposited, contacts of the emitter and the base are opened, and an emitter electrode 17 and a base electrode 18 are formed to complete an element portion. In a hetero-bipolar transistor based on SiGe, as shown in FIG. 2A, an N-type semiconductor layer 8 and a contact N ⁺ -type semiconductor layer 9 may be stacked on a P-type base 7 in some cases.

Further, as shown in FIG. 2B, a polysilicon emitter in which an N ⁺ type polysilicon 10 is superposed on an N-type semiconductor layer 8 or a P-type semiconductor layer 7 as shown in FIG. An N ⁺ type polysilicon (or amorphous silicon) 10 can be used on the substrate.

These structures can be applied to not only NPN transistors but also PNP transistors.
Next, a first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. First, as shown in FIG. 3A, an N-type epitaxial layer 4 is grown on an N ⁺ -type semiconductor substrate 1 to form an oxide film 5 for isolation. Next, after a P-type semiconductor layer 7 serving as a base and an N-type semiconductor layer 8 serving as an emitter are grown, an insulating film 11 is deposited, and the insulating film 11 and the N-type semiconductor layer 8 are selectively etched. Next, an insulating film is grown on the entire surface and then etched back to form a sidewall 14 made of the insulating film.

Next, as shown in FIG.
The P-type semiconductor layer 7 is etched using the first and side walls 14 as a mask.

Next, as shown in FIG. 3C, the Si-MBE or UHV (ultra-high v) is formed by using ^the side wall of the P-type semiconductor layer 7 and the N-type epitaxial layer 4 as nuclei.
acuum) CVD, P ⁺ to be a graft base
The type semiconductor layer 15 is grown at a low temperature. Next, FIG.
As shown in FIG. 7, an interlayer insulating film 16 is deposited, and the emitter and base contacts are opened.
Then, the element portion is completed by forming the base electrode 18. S
In an iGe-based hetero bipolar transistor, an N-type semiconductor layer 8 and a contact N ⁺ -type semiconductor layer 9 may be stacked on a P-type base 7 as shown in FIG.

Further, as shown in FIG. 4B, a polysilicon emitter in which an N ⁺ type polysilicon 10 is superimposed on an N type semiconductor layer 8, or as shown in FIG. An N ⁺ type polysilicon (or amorphous silicon) 10 can be used on the substrate.

These structures can be applied to not only NPN transistors but also PNP transistors.
Next, a second related technique of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 5A, an N ⁺ type buried layer 3 is selectively formed in an N ⁺ type semiconductor substrate 1, and then an N type epitaxial layer 4 is grown. Next, after the isolation oxide film 5 is formed, the collector pull-up portion 6 is formed, and the insulating film 11 is formed.

Next, as shown in FIG. 5B, a P-type semiconductor layer 7 and an N-type semiconductor layer 8 are grown, an insulating film 12 is deposited, and a photoresist 13 is formed.

Next, as shown in FIG. 5C, the insulating film 12 and the N-type semiconductor layer 8 are etched using the photoresist 13 as a mask. Next, the photoresist 13 is removed, an insulating film is deposited, and then etched back to form a sidewall 14, and a P ⁺ type semiconductor layer 15 is formed by ion implantation.

Thereafter, an interlayer insulating film is deposited, and an emitter,
The element portion is completed by opening the base contact and forming an electrode. Next, a second embodiment of the present invention will be described with reference to FIG. 6 (a) ~ (d) .

First, as shown in FIG. 6A, an N ⁺ -type buried layer 3 is selectively formed in an N ⁺ -type semiconductor substrate 1, and then an N-type epitaxial layer 4 is grown. Next, after the isolation oxide film 5 is formed and the insulating film 11 is formed, the collector upper part 6 is formed.

Next, as shown in FIG. 6B, a P-type semiconductor layer 7 and an N-type semiconductor layer 8 are grown, an insulating film 12 is deposited and a photoresist 13 is formed, and then the insulating film 12 is etched.

Next, as shown in FIG. 6C, the N-type semiconductor layer 8 is etched, and then the photoresist 13 is removed. Next, an insulating film is deposited and then etched back to form a sidewall 14. Next, the P ⁺ type semiconductor layer 15 is grown by Si-MBE or UHV-CVD.

After that, as shown in FIG. 6D, after the interlayer insulating film 16 is deposited, the emitter and base contacts are opened, and the emitter electrode 17 and the base electrode 18 are formed to complete the element portion. .

[0029]

According to the present invention, a P ⁺ type semiconductor layer serving as a graft base is formed on the side surface of the intrinsic base. The side wall is isolated between the emitter and the graft base. Since the emitter and base are formed in a self-aligned manner,
The margin between bases is no longer needed. The limit of miniaturization was determined by the thickness of the sidewall, and the base resistance could be significantly reduced.

Since the emitter is protected by the sidewall, the junction capacitance between the emitter and the base is reduced. Unnecessary carriers from the side of the emitter are no longer injected,
The current amplification factor and the breakdown voltage between the emitter and the base are improved.

Since the graft base conventionally formed in the epitaxial layer is formed on the epitaxial layer, the parasitic capacitance between the collector and the base is reduced, and the reverse breakdown voltage is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first reference technique of the present invention in the order of steps.

FIG. 2 is a sectional view showing a partially modified example of the first reference technology of the present invention .

FIG. 3 is a sectional view showing the first embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing a partially modified example of the first embodiment of the present invention .

FIG. 5 is a sectional view showing a second reference technology of the present invention in the order of steps.

FIG. 6 is a cross-sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 7 is a sectional view showing a conventional epitaxial base NPN transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N ⁺ type semiconductor substrate 2 P type semiconductor substrate 3 N ⁺ type buried layer 4 N type epitaxial layer 5 Separation oxide film 6 Collector upper part 7 P type semiconductor layer (base) 8 N type semiconductor layer (emitter) 9 N ⁺ Type semiconductor layer 10 N ⁺ type polysilicon (or amorphous silicon) 11 insulating film 12 insulating film 13 photoresist 14 side wall 15 P ⁺ type semiconductor layer 16 interlayer insulating film 17 emitter electrode 18 base electrode 19 collector electrode

Claims (4)

(57) [Claims] 1. An intrinsic base is formed on a collector layer of a bipolar transistor, an emitter and a sidewall of the emitter are formed on the intrinsic base, and the intrinsic base is self-aligned with the emitter and the sidewall. It consists of a single crystal doped with a high concentration of impurities in contact with the side surface of the intrinsic base and the upper surface of the collector layer.
The semiconductor device graft base is formed that. 2. A step of sequentially growing a first opposite conductivity type semiconductor layer and at least one one conductivity type semiconductor layer on a one conductivity type semiconductor substrate, and selectively etching a part of the one conductivity type semiconductor layer. Forming a sidewall made of an insulating film on a side surface of the one conductivity type semiconductor layer, and etching the first opposite conductivity type semiconductor layer using the one conductivity type semiconductor layer and the sidewall as a mask. the method of manufacturing a semiconductor device including the step of forming a second opposite conductivity type semiconductor layer in contact with a side surface and the one conductivity type semiconductor layer on surfaces of said first opposite conductivity type semiconductor layer. 3. The semiconductor device according to claim 2, wherein the second opposite conductivity type semiconductor layer is made of a single crystal.
3. The method of manufacturing a semiconductor device according to claim 2, wherein 4. The semiconductor device according to claim 1, wherein the second opposite conductivity type semiconductor layer is Si-MBE.
3. The method according to claim 2, wherein the semiconductor device is formed by UHV-CVD.