KR20010046495A - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
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- KR20010046495A KR20010046495A KR1019990050290A KR19990050290A KR20010046495A KR 20010046495 A KR20010046495 A KR 20010046495A KR 1019990050290 A KR1019990050290 A KR 1019990050290A KR 19990050290 A KR19990050290 A KR 19990050290A KR 20010046495 A KR20010046495 A KR 20010046495A
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- drain region
- low concentration
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 23
- -1 halo ions Chemical class 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 27
- 238000002955 isolation Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 125000001475 halogen functional group Chemical group 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자에 대한 것으로, 특히 소오스영역의 저항을 낮추어서 세cb레이션 전류(Saturation Current)를 증가시키기에 알맞은 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for increasing a saturation current by lowering a resistance of a source region.
첨부 도면을 참조하여 종래 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a conventional semiconductor device is as follows.
도 1a 내지 도 1e는 종래에 따른 반도체소자의 제조방법을 나타낸 공정단면도이고, 도 2는 도 1c에서의 레이아웃도이다.1A to 1E are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device, and FIG. 2 is a layout diagram of FIG. 1C.
종래 반도체소자의 제조방법은 도 1a에 도시한 바와 같이 필드영역과 액티브영역이 정의되어 있는 반도체기판(1)의 필드영역에 필드격리막(2)을 형성한다. 이때 필드격리막(2)은 반도체기판(1)에 홈을 갖고 매립하여 형성한다.In the conventional method of manufacturing a semiconductor device, as shown in FIG. 1A, the field isolation film 2 is formed in the field region of the semiconductor substrate 1 in which the field region and the active region are defined. At this time, the field isolation film 2 is formed by filling the semiconductor substrate 1 with a groove.
이후에 상기 반도체기판(1)에 산화막과 실리콘층을 차례로 증착하고, 게이트 형성 마스크를 이용해서 실리콘층과 산화막을 차례로 이방성 식각해서 액티브영역의 일영역에 게이트산화막(3)과 게이트전극(4)을 적층형성 한다.Subsequently, an oxide film and a silicon layer are deposited on the semiconductor substrate 1 in turn, and anisotropically etch the silicon layer and the oxide film by using a gate forming mask to gate oxide film 3 and gate electrode 4 in one region of the active region. To form a laminate.
그리고 도 1b에 도시한 바와 같이 전면에 제 1 포토레지스트(5)를 도포한 후에 상기 게이트전극(4) 양측의 액티브영역이 노출되도록 상기 필드격리막(2)상에만 남도록 노광 및 현상공정으로 선택적으로 제 1 포토레지스트(5)를 패터닝한다. 이후에 상기 노출된 게이트전극(4) 양측의 반도체기판(1)의 표면에 저농도의 불순물이온을 주입해서 LDD(Lightly Doped Drain)의 저농도 소오스/드레인영역(6)을 형성한다. 이후에 제 1 포토레지스트(5)를 제거한다.As shown in FIG. 1B, after the first photoresist 5 is applied to the entire surface, the photoresist 5 may be selectively exposed and developed to remain only on the field isolation film 2 so that the active regions on both sides of the gate electrode 4 are exposed. The first photoresist 5 is patterned. Thereafter, a low concentration of impurity ions are implanted into the surface of the semiconductor substrate 1 on both sides of the exposed gate electrode 4 to form a low concentration source / drain region 6 of a lightly doped drain (LDD). Thereafter, the first photoresist 5 is removed.
그리고 도 1c에 도시한 바와 같이 전면에 제 2 포토레지스트(7)을 도포한 후에 상기 저농도 소오스/드레인영역(6)이 드러나도록 노광 및 현상공정으로 선택적으로 제 2 포토레지스트(7)를 패터닝한다.After the second photoresist 7 is applied to the entire surface as shown in FIG. 1C, the second photoresist 7 is selectively patterned by an exposure and development process so that the low concentration source / drain regions 6 are exposed. .
이때 제 2 포토레지스트(7)는 도 2에 도시한 바와 같이 소오스영역이나 드레인영역이 모두 노출되도록 패터닝한다.In this case, as shown in FIG. 2, the second photoresist 7 is patterned to expose all of the source and drain regions.
이후에 패터닝된 제 2 포토레지스트(7)를 마스크로 반도체기판(1)과 할로(Halo) 이온을 경사각을 갖고 주입하여 상기 저농도 소오스/드레인영역(6)의 모서리 하부에 포켓모양을 갖도록 포켓 할로이온주입영역(8)을 형성한다. 이때 할로이온 주입은 저농도 소오스영역과 드레인영역에 동일한 횟수로 주입된다.(도면에는 4방향을 한 횟수로 볼 때 3회 주입된 것으로 도시했음.)Afterwards, the semiconductor substrate 1 and the halo ions are implanted with an inclination angle using the patterned second photoresist 7 as a mask to have a pocket shape so as to have a pocket shape under the corner of the low concentration source / drain region 6. An ion implantation region 8 is formed. In this case, the halo ion implantation is injected into the low concentration source region and the drain region at the same number of times. (The figure is illustrated as being injected three times in one direction in four directions.)
그리고 도 1d에 도시한 바와 같이 전면에 산화막이나 질화막을 증착한 후에 이방성 식각하여 게이트산화막(3)과 게이트전극(4)의 양측면에 측벽스페이서(9)를 형성한다.1D, an oxide film or a nitride film is deposited on the entire surface, and then anisotropically etched to form sidewall spacers 9 on both sides of the gate oxide film 3 and the gate electrode 4.
다음에 도 1e에 도시한 바와 같이 전면에 제 3 포토레지스트(10)를 도포한 후에 상기 측벽스페이서(9)와 게이트전극(4) 양측의 반도체기판(1)이 드러나도록 노광 및 현상공정으로 선택적으로 제 3 포토레지스트(10)를 패터닝한다.Next, after the third photoresist 10 is applied to the entire surface as shown in FIG. 1E, the semiconductor substrate 1 on both sides of the sidewall spacer 9 and the gate electrode 4 is selectively exposed and developed. The third photoresist 10 is patterned.
이후에 패터닝된 제 3 포토레지스트(10)를 마스크로 반도체기판(1)에 고농도의 불순물이온을 주입해서 고농도 소오스/드레인영역(11)을 형성한다. 이때 고농도 소오스/드레인영역(11)은 상기 저농도 소오스/드레인영역(6)보다 깊게 형성한다.Thereafter, a high concentration source / drain region 11 is formed by implanting a high concentration of impurity ions into the semiconductor substrate 1 using the patterned third photoresist 10 as a mask. In this case, the high concentration source / drain region 11 is formed deeper than the low concentration source / drain region 6.
상기와 같은 종래 반도체소자의 제조방법은 다음과 같은 문제가 있다.The conventional method of manufacturing a semiconductor device as described above has the following problems.
LDD의 저농도 소오스/드레인영역의 모서리 부분에 포켓 할로이온주입영역을 형성할 때 소오스영역에도 형성되므로 소오스의 저항이 증가하여 트랜지스터의 세츄레이션 전류가 저하되는 문제가 있다.When the pocket halo implantation region is formed in the corner portion of the low concentration source / drain region of the LDD, it is also formed in the source region, thereby increasing the resistance of the source and decreasing the transistor current.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 소오스영역의 저항을 줄여서 세츄레이션 전류(Saturation Current)가 감소되는 것을 방지하기에 알맞은 반도체소자의 제조방법을 제공하는 데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device suitable for preventing the reduction of the saturation current by reducing the resistance of the source region. .
도 1a 내지 도 1e는 종래에 따른 반도체소자의 제조방법을 나타낸 공정단면도1A through 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 2는 도 1c에서의 레이아웃도FIG. 2 is a layout diagram in FIG. 1C
도 3a 내지 도 3e는 본 발명 실시예에 따른 반도체소자의 제조방법을 나타낸 공정단면도3A through 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 4a는 도 3c에서의 본 발명 제 1 실시예에 따른 레이아웃도4A is a layout diagram according to the first embodiment of the present invention in FIG. 3C.
도 4b는 도 3c에서의 본 발명 제 2 실시예에 따른 레이아웃도4B is a layout diagram according to the second embodiment of the present invention in FIG. 3C.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 필드격리막31: semiconductor substrate 32: field isolation film
33 : 게이트산화막 34 : 게이트전극33: gate oxide film 34: gate electrode
35 : 제 1 포토레지스트 36 : 저농도 소오스/드레인영역35 first photoresist 36 low concentration source / drain region
37 : 제 2 포토레지스트 38 : 포켓 할로이온주입영역37: second photoresist 38: pocket halo ion implantation region
39 : 측벽스페이서 40 : 제 3 포토레지스트39 sidewall spacer 40 third photoresist
41 : 고농도 소오스/드레인영역41: high concentration source / drain area
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 제조방법은 기판의 일영역에 게이트절연막과 게이트전극을 적층 형성하는 공정, 상기 게이트전극 양측의 기판내에 저농도 소오스영역과 드레인영역을 형성하는 공정, 상기 저농도 드레인영역은 오픈시키고 상기 저농도 소오스영역은 상기 드레인영역의 오픈된 폭보다 작게 상기 게이트전극 일측을 따라 오픈되도록 마스크패턴을 형성하는 공정, 상기 마스크패턴을 이용해서 상기 게이트전극 하부의 상기 저농도 드레인영역과 저농도 소오스영역의 일측모서리에 할로이온을 주입하는 공정, 상기 마스크패턴을 제거하는 공정, 상기 게이트전극 양측면에 측벽스페이서를 형성하는 공정, 상기 게이트전극과 상기 측벽스페이서 양측의 상기 기판에 고농도 소오스/드레인영역을 형성하는 공정을 포함함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of laminating a gate insulating film and a gate electrode in one region of a substrate, forming a low concentration source region and a drain region in the substrate on both sides of the gate electrode; Forming a mask pattern such that the low concentration drain region is opened and the low concentration source region is opened along one side of the gate electrode to be smaller than an open width of the drain region, and the low concentration drain under the gate electrode using the mask pattern. Implanting a halo ion into one corner of a region and a low concentration source region, removing the mask pattern, forming sidewall spacers on both sides of the gate electrode, and high concentration source on the substrate on both sides of the gate electrode and the sidewall spacer. / Process to form the drain area It is characterized by a ship.
첨부 도면을 참조하여 본 발명 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method for manufacturing a semiconductor device of the present invention will be described.
도 3a 내지 도 3e는 본 발명 실시예에 따른 반도체소자의 제조방법을 나타낸 공정단면도이고, 도 4a는 도 3c에서의 본 발명 제 1 실시예에 따른 레이아웃도이고, 도 4b는 도 3c에서의 본 발명 제 2 실시예에 따른 레이아웃도이다.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, FIG. 4A is a layout diagram according to the first embodiment of the present invention in FIG. 3C, and FIG. 4B is a view in FIG. 3C. A layout diagram according to a second embodiment of the invention.
본 발명 반도체소자의 제조방법은 도 3a에 도시한 바와 같이 필드영역과 액티브영역이 정의되어 있는 반도체기판(31)의 필드영역에 필드격리막(32)을 형성한다. 이때 필드격리막(32)은 반도체기판(31)에 홈을 갖고 매립하여 형성한다.In the method of manufacturing the semiconductor device of the present invention, as shown in FIG. 3A, the field isolation film 32 is formed in the field region of the semiconductor substrate 31 in which the field region and the active region are defined. At this time, the field isolation film 32 is formed by filling the semiconductor substrate 31 with a groove.
이후에 상기 반도체기판(31)에 산화막과 실리콘층을 차례로 증착하고, 게이트 형성 마스크를 이용해서 실리콘층과 산화막을 차례로 이방성 식각해서 액티브영역의 일영역에 게이트산화막(33)과 게이트전극(34)을 적층형성 한다. 이때 게이트전극(34)은 일직선의 라인을 이룰 수도 있고, 일정각을 갖고 굽은 형태일 수도 있다.Subsequently, an oxide film and a silicon layer are sequentially deposited on the semiconductor substrate 31, and anisotropic etching of the silicon layer and the oxide film is sequentially performed using a gate forming mask to form a gate oxide film 33 and a gate electrode 34 in one region of the active region. To form a laminate. In this case, the gate electrode 34 may form a straight line, or may be bent at a predetermined angle.
그리고 도 3b에 도시한 바와 같이 전면에 제 1 포토레지스트(35)를 도포한 후에 상기 게이트전극(34) 양측의 액티브영역이 노출되도록 상기 필드격리막(32)상에만 남도록 노광 및 현상공정으로 선택적으로 제 1 포토레지스트(35)를 패터닝한다. 이후에 상기 노출된 게이트전극(34) 양측의 반도체기판(31)의 표면에 저농도의 불순물이온을 주입해서 저농도 소오스/드레인영역(36)을 형성한다. 이후에 제 1 포토레지스트(35)를 제거한다.As shown in FIG. 3B, after the first photoresist 35 is applied to the entire surface, the photoresist 35 may be selectively exposed and developed to remain only on the field isolation layer 32 so that the active regions on both sides of the gate electrode 34 are exposed. The first photoresist 35 is patterned. Subsequently, a low concentration source / drain region 36 is formed by implanting a low concentration of impurity ions into the surface of the semiconductor substrate 31 on both sides of the exposed gate electrode 34. Thereafter, the first photoresist 35 is removed.
그리고 도 3c에 도시한 바와 같이 전면에 제 2 포토레지스트(37)을 도포한 후에 게이트전극(34) 일측의 드레인영역은 노출시키고, 타측의 소오스영역은 노출되지 않도록 노광 및 현상공정으로 선택적으로 제 2 포토레지스트(37)를 패터닝한다.As shown in FIG. 3C, after the second photoresist 37 is applied to the entire surface, the drain region on one side of the gate electrode 34 is exposed, and the source region on the other side is selectively exposed by the exposure and development processes. 2 Photoresist 37 is patterned.
이후에 패터닝된 제 2 포토레지스트(37)를 마스크로 경사각을 주어 할로(Halo) 이온을 주입하여서 저농도 소오스/드레인영역(36)의 모서리부분에 포켓 할로이온주입영역(38)을 형성한다.Afterwards, the halo ions are implanted with an inclination angle using the patterned second photoresist 37 as a mask to form a pocket halo implantation region 38 at the corners of the low concentration source / drain region 36.
이때 도 4a에서와 같이 게이트전극(34)이 일방향의 라인으로 형성되었을 경우에 저농도 드레인영역은 제 2 포토레지스트(37)를 전부 오픈하고, 저농도 소오스영역은 게이트전극(34) 일측의 소정폭만큼만 오픈한다. 즉, 저농도 소오스영역의 오픈된 폭을 저농도 드레인영역의 오픈된 폭보다 작게한다.In this case, when the gate electrode 34 is formed in one direction as in FIG. 4A, the low concentration drain region completely opens the second photoresist 37, and the low concentration source region has a predetermined width on one side of the gate electrode 34. Open it. That is, the open width of the low concentration source region is made smaller than the open width of the low concentration drain region.
이에 따라서 4개의 직교하는 방향으로 할로(Halo) 이온이 주입되고 각 방향을 1회라고 정의할 때 드레인영역은 3방향에서 할로이온이 주입되므로 3회 이온주입되는데 비해서, 소오스영역은 2방향으로만 할로이온이 주입되므로 2회 이온주입된다.Therefore, when halo ions are implanted in four orthogonal directions and each direction is defined as one time, the ion region is implanted three times because halo ions are implanted in the drain region in three directions, whereas the source region is only in two directions. Since halo ions are implanted, they are implanted twice.
그리고 도 4b에서와 같이 게이트전극(34)이 각을 갖고 굽어서 형성되었을 경우에 저농도 드레인 영역은 제 2 포토레지스트(37)를 전부 오픈하고, 저농도 소오스영역은 굽은 게이트전극(34)의 일측을 따라 소정폭 만큼만 오픈시킨다. 따라서 저농도 드레인영역은 각을 갖고 굽은 부분만 2방향으로 할로이온이 주입되므로 2회 이온주입되고, 나머지 부분은 3방향에서 할로이온이 주입되므로 3회 이온주입된다. 이에 비해서 저농도 소오스영역은 각을 갖고 굽은부분은 할로이온이 주입되지 않고, 굽지 않은 부분만 2방향에서 할로이온이 주입되므로 2회 이온주입된다.When the gate electrode 34 is bent at an angle, as shown in FIG. 4B, the low concentration drain region completely opens the second photoresist 37, and the low concentration source region opens one side of the bent gate electrode 34. Therefore, only the predetermined width is opened. Therefore, the low concentration drain region has an angle and only two bent portions are implanted with halo ions in two directions, and the remaining portions are implanted three times with halo ions in three directions. On the other hand, the low concentration source region has an angle and the bent portion is not implanted with halo ions, and only the uncured portion is implanted with halo ions in two directions.
위와 같이 할로이온을 주입한 후에 제 2 포토레지스트(37)를 제거한다.After injecting the halo ion as described above, the second photoresist 37 is removed.
이후에 도 3d에 도시한 바와 같이 전면에 산화막이나 질화막을 증착한 후에 이방성 식각하여 게이트산화막(33)과 게이트전극(34)의 양측면에 측벽스페이서(39)를 형성한다.Thereafter, as illustrated in FIG. 3D, an oxide film or a nitride film is deposited on the entire surface, and then anisotropically etched to form sidewall spacers 39 on both sides of the gate oxide film 33 and the gate electrode 34.
다음에 도 3e에 도시한 바와 같이 전면에 제 3 포토레지스트(40)를 도포한 후에 상기 측벽스페이서(39)와 게이트전극(34) 양측의 반도체기판(31)이 드러나도록 노광 및 현상공정으로 선택적으로 제 3 포토레지스트(40)를 패터닝한다.Next, as shown in FIG. 3E, after the third photoresist 40 is applied to the front surface, the sidewall spacer 39 and the semiconductor substrate 31 on both sides of the gate electrode 34 are selectively exposed and developed to expose. The third photoresist 40 is patterned.
이후에 패터닝된 제 3 포토레지스트(40)를 마스크로 반도체기판(31)에 고농도의 불순물이온을 주입해서 고농도 소오스/드레인영역(41)을 형성한다. 이때 고농도 소오스/드레인영역(41)은 상기 저농도 소오스/드레인영역(36)보다 깊게 형성한다.Thereafter, a high concentration of source / drain regions 41 are formed by implanting a high concentration of impurity ions into the semiconductor substrate 31 using the patterned third photoresist 40 as a mask. At this time, the high concentration source / drain region 41 is formed deeper than the low concentration source / drain region 36.
상기와 같은 본 발명 반도체소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing the semiconductor device of the present invention as described above has the following effects.
소오스영역에 포켓 할로이온주입 회수를 적게하여 도핑농도를 낮게 형성하면 소오스영역의 저항이 감소하여서 소자의 세츄레이션 전류(Saturation Current)가 감소하는 것을 방지할 수 있다.If the doping concentration is lowered by reducing the number of pocket halo implants in the source region, the resistance of the source region is reduced to prevent the reduction of the saturation current of the device.
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| KR100935775B1 (en) * | 2007-12-03 | 2010-01-08 | 주식회사 동부하이텍 | Semiconductor Device and Method for Manufacturing Thereof |
| KR100947567B1 (en) * | 2003-03-28 | 2010-03-12 | 매그나칩 반도체 유한회사 | High Voltage Device and Method for the Same |
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| US5894158A (en) * | 1991-09-30 | 1999-04-13 | Stmicroelectronics, Inc. | Having halo regions integrated circuit device structure |
| US5534449A (en) * | 1995-07-17 | 1996-07-09 | Micron Technology, Inc. | Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry |
| US5595919A (en) * | 1996-02-20 | 1997-01-21 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned halo process for reducing junction capacitance |
| KR100212150B1 (en) * | 1996-11-04 | 1999-08-02 | 윤종용 | Cmos transistor and fabrication method thereof |
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| KR100935775B1 (en) * | 2007-12-03 | 2010-01-08 | 주식회사 동부하이텍 | Semiconductor Device and Method for Manufacturing Thereof |
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