KR100522763B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can ensure a stable transistor characteristics against process variations, the method of manufacturing a semiconductor device of the present invention is a PMOS formed in the core region defined NMOS region and PMOS region Like NMOS, NBN 1/2 ion implantation (for the purpose of reducing the electric field of the cell region) is performed while the thickness of the gate spacer is reduced to have LDD characteristics, and at this time, the LDD region is also formed in the PMOS region to reduce the electric field and change the process. It is effective to secure stable device characteristics.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a transistor of a semiconductor device.

The DRAM is divided into a cell region (Cell Mat.) In which a cell transistor and a capacitor are formed, and a peripheral circuit such as a sense amplifier for driving an element of the cell region and a core region (CORE) in which a logic circuit is formed.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a field oxide film 12 is formed on the semiconductor substrate 11 for isolation between devices. Here, in the semiconductor substrate 11, a cell region and a core region are defined, and in the core region, an NMOS region and a PMOS region are defined.

Next, the gate pattern 13 is formed on the semiconductor substrate 11. In this case, although not shown, the gate pattern 13 is stacked on the semiconductor substrate 11 in the order of a gate oxide film, a polysilicon film, a tungsten silicide film, and a gate hard mask nitride film, and subsequently etched.

After the gate pattern 13 is formed, a gate light oxidation may be lightly performed to compensate for the deterioration of the gate oxide layer due to the etching process.

Next, n-type dopants are ion-implanted on the entire surface to form LDD regions 14a and 14b and pocket regions 14c. At this time, the LDD regions 14a and 14b are formed in the NMOS region of the cell region and the core region, and the pocket region 14c is formed in the PMOS region of the core region, and the LDD regions 14a and 14b and the pocket region ( 14c) is formed by ion implantation of an n-type dopant such as arsenic (As) or phosphorus (P). The process for forming the LDD regions 14a and 14b and the pocket region 14c is referred to as an NM1 process.

Hereinafter, the LDD regions 14a and 14b formed in the NMOS regions of the cell region and the core region will be abbreviated as 'nLDDs 14a and 14b'.

Subsequently, the first oxide film 15, the nitride film 16, and the second oxide film 17 are sequentially deposited on the entire surface including the gate pattern 13.

As shown in FIG. 1B, a photomask is coated on the entire surface and patterned by exposure and development to form a first mask layer 18 for selectively opening the core region. In this case, the first mask layer 38 serves as an ion implantation mask layer for forming N ⁺ S / D regions and P ⁺ S / D regions in the NMOS region and the PMOS region of the core region.

Next, before proceeding with the ion implantation process for forming the N ⁺ S / D region and the P ⁺ S / D region, the second oxide film 37 of the core region is formed using the first mask layer 38 as an etching barrier. Optionally dry etch. At this time, the nitride film 36 and the first oxide film 35 are also etched at the same time to form the gate spacer 100 in contact with both side walls of the gate pattern of the core region. In this case, the gate spacer 100 has a triple structure of oxide spacers 15a and 17a of the first oxide film and the second oxide film and nitride film spacer 16a of the nitride film.

After the gate spacer 100 is formed, the second oxide film 17b, the nitride film 16b, and the first oxide film 15b still remain in the cell region.

Subsequently, high concentration N-type dopants and P-type dopants are ion-implanted into the NMOS and PMOS regions of the core region using the first mask layer 18 as an ion implantation mask, respectively, to form the N ⁺ S / D regions 19a and P. ⁺ S / D region 19b is formed.

As shown in FIG. 1C, after the first mask layer 18 is removed, a second mask layer 20 is formed to open the cell region by applying a photoresist film and patterning it by exposure and development. The second mask layer 20 is commonly referred to as a cell open mask, and is formed in such a manner that all of the cell regions are opened and all of the core regions are covered.

Next, the second oxide film 17b remaining in the cell region opened by the second mask layer 20 is removed by wet etching. After the wet etching, some of the second oxide layer 17c may remain at the boundary between the cell region and the core region.

In the wet etching process, since the nitride film 16b under the second oxide film 17b serves as an etching barrier, the nitride film 16b is not removed. Therefore, after the wet etching, the nitride film 16b and the first oxide film 15b remain on the gate pattern 11 of the cell region and the core region.

Next, an ion implantation layer 21 in contact with the nLDD 14a is formed by ion implanting an n-type dopant on the entire surface in order to reduce the electric field of the cell region while the second mask layer 20 remains.

2 is a plan view illustrating an NMOS and a PMOS of a core region according to the related art.

Referring to FIG. 2, the NMOS and PMOS transistors formed in the core region have a ring-shaped gate pattern G, and source and drain regions S and D are formed on both sides of the gate pattern G. Referring to FIG. That is, the gate pattern G is formed in a 'ring' shape and is disposed up and down in a symmetrical form facing each other, and a source region S is formed between the gate patterns G facing each other. G) The drain region D is formed inside.

As described above, in the case of the transistor formed in the core region in the related art, since the gate spacer 100 is formed through the first mask layer 18, N ⁺ S / D in a state where the thickness of the gate spacer 100 is thick. The region 19a and the P ⁺ S / D region 19b are formed.

Therefore, the prior art forms the N ⁺ S / D region 19a and the P ⁺ S / D region 19b due to the lack of a space between the gate patterns G having a ring shape (see 'x' in FIG. 2). This is a bad drawback.

As described above, if the formation of the S / D region is poor, there is a problem that the I _op (Operation current) characteristics of the transistor is weak. Here, I _op is commonly _{referred to} as I _dsat (Drain current saturation).

3 is a graph comparing the I _op characteristics according to the thickness of the gate spacer according to the prior art. In FIG. 3, the horizontal axis represents the gate voltage Vg, and the vertical axis represents I _dsat .

Referring to FIG. 3, it can be seen that I _dsat is lower in the case where the thickness of the gate spacer is 650 ms compared with the case where the thickness of the gate spacer is 550 _ms . In other words, it can be seen that I _dsat increases rapidly as the thickness of the gate spacer decreases.

As can be seen in FIG. 3, when the thickness of the gate spacer increases between adjacent gate patterns, the I _op characteristic becomes weak due to lack of space.

In addition, in the case of the PMOS formed in the core region, the source and drain regions are formed only by NM1 (pocket region) and P ⁺ ion implantation (P ⁺ S / D region). It is difficult to secure stable PMOS characteristics due to a large variation in transistor characteristics. That is, if the thickness uniformity of the gate spacer is poor over the entire area of the wafer, the I _op changes by about 40%, which is the reason why the device characteristics become unstable.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device capable of securing stable transistor characteristics against process variations.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes forming a gate pattern on a core region of a semiconductor substrate in which a PMOS region and an NMOS region are defined, and ionizing a first N-type dopant on the entire surface of the core region. Forming a pocket region in the PMOS region by implantation, sequentially forming a first oxide film, a nitride film, and a second oxide film on the gate pattern, and selectively etching the second oxide film to contact both sidewalls of the gate pattern Forming a spacer, forming a P ⁺ S / D region in contact with the pocket region by ion implanting a high concentration P-type dopant with the spacer and the gate pattern as a barrier, removing the spacer, and by ion implantation to claim 2 N-type dopant to the nitride film as a barrier at the front form the LDD region between the P ⁺ S / D regions and the pocket regions It is characterized by including the steps:

In addition, in the method of manufacturing a semiconductor device of the present invention, forming a gate pattern on a semiconductor substrate having a core region and a cell region including a PMOS region and an NMOS region, and forming a first N-type dopant on the entire surface of the semiconductor substrate. Implanting ions to form a first LDD region in the NMOS region and simultaneously forming a pocket region in the PMOS region, sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on the gate pattern, and the second oxide layer Forming a spacer in contact with both sidewalls of the gate pattern by ion etching, and ionically implanting a high concentration of the second N-type dopant and a high concentration of the P-type dopant as a barrier to the first LDD region, respectively; N ⁺ S / D regions and forming a contact with P ⁺ S / D regions in the pocket region, removing said spacers, and of the core area By ion implantation to claim 3 N type dopant, the nitride film as a barrier to the surface between the first 1LDD region and the N ⁺ S / D regions and the step of forming the 2 LDD region between the P ⁺ S / D regions and the pocket regions It is characterized by including.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 4A, a field oxide film 32 is formed on the semiconductor substrate 31 for isolation between devices. Here, in the semiconductor substrate 31, a cell region and a core region are defined, and in the core region, an NMOS region and a PMOS region are defined.

Next, the gate pattern 33 is formed on the semiconductor substrate 31. In this case, although not shown, the gate pattern 33 is laminated on the semiconductor substrate 31 in the order of the gate oxide film, the polysilicon film, the tungsten silicide film, and the gate hard mask nitride film, and is sequentially formed by etching.

After the gate pattern 33 is formed, a gate light oxidation may be lightly performed to compensate for the deterioration of the gate oxide layer due to the etching process.

Next, n-type dopants are ion-implanted on the entire surface to form first LDD regions 34a and 34b and pocket regions 34c. In this case, the first LDD regions 34a and 34b are formed in the NMOS region of the cell region and the core region, and the pocket region 3c is formed in the PMOS region of the core region, and the LDD regions 34a and 34b and the pocket region are formed. 34c is formed by ion implantation of an n-type dopant such as arsenic (As) or phosphorus (P). The process for forming the first LDD regions 34a and 34b and the pocket region 34c is referred to as an NM1 process.

Hereinafter, the first LDD regions 34a and 34b formed in the NMOS regions of the cell region and the core region will be abbreviated as 'first nLDDs 34a and 34b'.

Next, the first oxide film 35, the nitride film 36, and the second oxide film 37 are sequentially deposited on the entire surface including the gate pattern 33.

As shown in FIG. 4B, a photomask is coated on the entire surface, and patterned by exposure and development to form a first mask layer 38 for selectively opening the core region. In this case, the first mask layer 38 serves as an ion implantation mask layer for forming N ⁺ S / D regions and P ⁺ S / D regions in the NMOS region and the PMOS region of the core region.

Next, before proceeding with the ion implantation process for forming the N ⁺ S / D region and the P ⁺ S / D region, the second oxide film 37 is selectively dry by using the first mask layer 38 as an etching barrier. Etch it. In this case, the target is adjusted to stop the etching in the nitride film 36 so that the nitride film 36 remains at least 70 kPa after the etching of the second oxide film 37.

After etching the second oxide film 37, an oxide film spacer 37a made of a second oxide film is formed on both side walls of the gate pattern 33 of the core region, and a second oxide film 37b remains in the cell region. In addition, the nitride film 36 and the first oxide film 35 remain on the core region.

Subsequently, high concentration N-type dopants and P-type dopants are ion-implanted into the NMOS and PMOS regions of the core region using the first mask layer 38 as an ion implantation mask, respectively, to form the N ⁺ S / D regions 39a and P. ⁺ S / D region 39b is formed.

As shown in FIG. 4C, after the first mask layer 38 is removed, the second mask layer 40 is formed by applying a photoresist film and patterning the light and developing to open the cell region. The second mask layer 40 is commonly referred to as a cell open mask. In the present invention, both the cell region is opened and the NMOS region and the PMOS region of the core region are selectively opened. Meanwhile, in the prior art, a mask layer was formed in such a manner that all cell regions were opened and all core regions were covered during the cell open mask process.

Next, the second oxide film 37b remaining in the cell region opened by the second mask layer 40 is removed by wet etching. At this time, since the core region is partially opened by the second mask layer 37b, the oxide spacer 37a formed of the second oxide film is also wet-etched at the same time, and after wet etching, the oxide spacer 37a is formed at the boundary between the cell region and the core region. A part of the dioxide oxide 37c may remain.

In the wet etching process, since the nitride layer 36 under the second oxide layer 37b serves as an etching barrier, the nitride layer 36 is not removed. Therefore, after the wet etching, the nitride layer 36 and the first oxide layer 35 remain on the gate patterns of the cell region and the core region.

As shown in FIG. 4D, the nitride barrier implant (NBN) 1/2 is an ion implantation process for reducing the electric field of the cell region on the front surface of the semiconductor substrate 31 using the second mask layer 40 as an ion implantation mask. Proceed with the ion implantation process. At this time, the ion implantation is ion implanted with Phosphorous (P). Here, NBN ion implantation refers to a process of ion implantation of phosphorus using a nitride film as a barrier, and NBN 1/2 ion implantation means that the ion implantation energy and the ion implantation dose are performed twice in the same ion implantation step. do.

Through the NBN 1/2 ion implantation as described above, the second nLDD 41a is formed in the cell region, and at the same time, the second nLDD 41b is formed in the NMOS region of the core region. In addition, the second nLDD 41c is formed in the PMOS region.

In detail, after NBN 1/2 ion implantation, a cell junction including a first nLDD 34a and a second nLDD 41a is formed, and a first nLDD 34a and an N ⁺ S / D region are formed in the NMOS region of the core region. A second nLDD 41b, which is another LDD region, is formed between 39a, and a second nLDD 41c, which is an LDD region, is formed between the pocket region 34b and the P ⁺ S / D region 39b in the PMOS region. do.

As described above, the second nLDD 41b, which is another LDD region, is formed between the first nLDD 34a and the N ⁺ S / D region 39a in the NMOS region of the core region, thereby reducing the electric field, thereby reducing I _op . Is improved.

In the PMOS region of the core region, different dopants have a counter-doping effect. That is, the N-type dopant injected into the second nLDD 41c and the P-type dopant injected into the P ⁺ S / D region 39b are counter doped.

As such, when counter-doped, the PMOS region, like the NMOS region, has LDD characteristics.

As described above, if the PMOS formed in the PMOS region has LDD characteristics similar to the NMOS, stable device characteristics against electric field reduction and process variation can be secured.

Meanwhile, in the prior art, the NBN 1/2 ion implantation process is performed only in the cell region, but in the present invention, the NBN 1/2 ion implantation process is also performed in the NMOS region and PMOS region of the core region.

According to the above-described embodiment, since the source / drain region of the PMOS of the core region is formed in a state where the thickness of the gate spacer is thin, it can be seen that I _dsat increases rapidly due to the decrease of the thickness of the gate spacer. This means that the I _op characteristic is improved.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of ensuring stable device characteristics against electric field reduction and process variation by performing NBN 1/2 ion implantation so that the PMOS formed in the core region has LDD characteristics similarly to NMOS.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

2 is a plan view showing an NMOS and a PMOS in a core region according to the prior art;

3 is a graph comparing the I _op characteristics according to the thickness of the gate spacer according to the prior art,

4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 field oxide film

33: gate patterns 34a, 34b: first nLDD

34c: pocket area 35: first oxide film

36 nitride film 37 second oxide film

38: first mask layer 39a: N ⁺ S / D region

39b: P ⁺ S / D area 40: second mask layer

41a, 41b, 41c: second nLDD

Claims (9)

Forming a gate pattern on the core region of the semiconductor substrate in which the PMOS region and the NMOS region are defined; Implanting a first N-type dopant in front of the core region to form a pocket region in the PMOS region; Sequentially forming a first oxide film, a nitride film, and a second oxide film on the gate pattern; Selectively etching the second oxide layer to form a spacer in contact with both sidewalls of the gate pattern; Ion implanting a high concentration P-type dopant with the spacer and the gate pattern as a barrier to form a P ⁺ S / D region in contact with the pocket region; Removing the spacers; And Forming an LDD region between the P ⁺ S / D region and the pocket region by ion implanting a second N-type dopant with the nitride film as a barrier on the front surface of the core region Method for manufacturing a semiconductor device comprising a. The method of claim 1, Selectively etching the second oxide layer to form a spacer in contact with both sidewalls of the gate pattern; The method of manufacturing a semiconductor device, characterized in that to proceed to stop the etching in the nitride film. The method of claim 1, The LDD region is A method of manufacturing a semiconductor device, characterized in that formed by implanting phosphorus ion. The method of claim 1, Removing the spacers, A method for manufacturing a semiconductor device, characterized in that it proceeds through wet etching. Forming a gate pattern on the semiconductor substrate including a core region and a cell region including a PMOS region and an NMOS region; Implanting a first N-type dopant on the entire surface of the semiconductor substrate to form a first LDD region in the NMOS region and a pocket region in the PMOS region; Sequentially forming a first oxide film, a nitride film, and a second oxide film on the gate pattern; Selectively etching the second oxide layer to form a spacer in contact with both sidewalls of the gate pattern; The N ⁺ S / D region in contact with the first LDD region and the P ⁺ S / D region in contact with the pocket region are ion-implanted with a high concentration of a second N-type dopant and a high-concentration P-type dopant using the spacer and the gate pattern as barriers. Forming; Removing the spacers; And A third LDD region is formed between the first LDD region and the N ⁺ S / D region and between the P ⁺ S / D region and the pocket region by ion implanting a third N-type dopant with the nitride layer as a barrier on the front surface of the core region. Forming steps Method for manufacturing a semiconductor device comprising a. The method of claim 5, Forming the spacers, Applying a photoresist to the entire surface of the semiconductor substrate; Patterning the photoresist with exposure and development to form a first mask layer covering the remaining portion of the semiconductor substrate except for the PMOS region and the NMOS region; And Dry etching the second oxide layer using the first mask layer as a barrier Method of manufacturing a semiconductor device comprising a. The method of claim 5, Removing the spacers, Applying a photoresist to the entire surface of the semiconductor substrate; Patterning the photoresist with exposure and development to form a second mask layer covering the semiconductor substrate except for the cell region, the PMOS region, and the NMOS region; And Wet etching the spacer and the second oxide layer using the second mask layer as a barrier Method of manufacturing a semiconductor device comprising a. The method of claim 5, The first LDD region and the second LDD region are also formed in the cell region. The method according to claim 5 or 8, The second LDD region is formed by ion implantation of a semiconductor device manufacturing method.