KR100313958B1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- KR100313958B1 KR100313958B1 KR1019990052472A KR19990052472A KR100313958B1 KR 100313958 B1 KR100313958 B1 KR 100313958B1 KR 1019990052472 A KR1019990052472 A KR 1019990052472A KR 19990052472 A KR19990052472 A KR 19990052472A KR 100313958 B1 KR100313958 B1 KR 100313958B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 230000005684 electric field Effects 0.000 abstract description 10
- 230000002040 relaxant effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
드레인영역에 인접한 게이트전극 하부에지에서의 전계(electric field)를 완화시켜서 소자의 동작을 안정화 시킬 수 있는 반도체소자 및 그의 제조방법을 제공하기 위한 것으로, 이와 같은 목적을 달성하기 위한 반도체소자는 반도체기판의 일영역에 형성된 버퍼절연막, 상기 버퍼절연막 상부를 덮고 일방향으로 더 연장되어 상기 반도체기판상에 형성된 게이트절연막, 상기 버퍼절연막상측을 포함한 상기 게이트절연막상에 형성된 게이트전극, 상기 버퍼절연막의 일측면과 상기 게이트절연막과 상기 게이트전극의 양측면에 형성된 측벽스페이서, 상기 측벽스페이서 하부 및 상기 버퍼절연막의 일측하부에 형성된 저농도 불순물영역, 상기 게이트절연막과 상기 게이트전극과 상기 측벽스페이서 하부를 제외한 그 양측의 상기 반도체기판에 형성된 고농도 불순물영역을 포함하여 구성됨을 특징으로 한다.To provide a semiconductor device and a method of manufacturing the semiconductor device that can stabilize the operation of the device by relaxing the electric field at the lower edge of the gate electrode adjacent to the drain region, the semiconductor device for achieving the above object is a semiconductor substrate A buffer insulating film formed in one region of the substrate, a gate insulating film covering the upper portion of the buffer insulating film and extending further in one direction, a gate electrode formed on the gate insulating film including an upper side of the buffer insulating film, and a side surface of the buffer insulating film. Sidewall spacers formed on both sides of the gate insulating film and the gate electrode, low concentration impurity regions formed under the sidewall spacer and one side of the buffer insulating film, and the semiconductors on both sides of the gate insulating film and the gate electrode and the lower side of the sidewall spacer High concentration formed on the substrate And an impurity region.
Description
본 발명은 반도체소자에 대한 것으로, 특히 드레인에 인접한 게이트전극 에지에서의 전계(electric field)효과를 완화시키기에 알맞은 반도체소자 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device suitable for mitigating the effect of an electric field at a gate electrode edge adjacent to a drain, and a manufacturing method thereof.
첨부 도면을 참조하여 종래 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a conventional semiconductor device is as follows.
도 1a 내지 도 1e는 종래 반도체소자의 제조방법을 나타낸 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
종래 반도체소자의 제조방법은 도 1a에 도시한 바와 같이 액티브영역과 필드영역이 정의된 반도체기판(1)의 액티브영역에 P웰(2)을 형성하고, LOCOS(Local Oxidation of Silicon) 공정으로 상기 필드영역에 필드산화막(3)을 형성한다.In the conventional method of manufacturing a semiconductor device, as shown in FIG. 1A, a P well 2 is formed in an active region of a semiconductor substrate 1 in which an active region and a field region are defined, and the LOCOS (Local Oxidation of Silicon) process is used. A field oxide film 3 is formed in the field region.
다음에 도 1b에 도시한 바와 같이 P웰(2)과 필드산화막(3)을 포함한 반도체기판(1)전면에 400Å정도 두께를 갖는 버퍼산화막(4)을 성장시킨다.Next, as shown in FIG. 1B, a buffer oxide film 4 having a thickness of about 400 microseconds is grown on the entire surface of the semiconductor substrate 1 including the P well 2 and the field oxide film 3.
이후에 P웰(2)표면에 문턱전압 조절이온을 주입하여서 도 1c와 같이 P웰(2) 표면에 +이온을 형성한다.Thereafter, a threshold voltage control ion is implanted into the surface of the P well 2 to form + ions on the surface of the P well 2 as shown in FIG.
다음에 버퍼산화막(4)을 제거한 후에 반도체기판(1) 전면에 제 1 산화막과 폴리실리콘층을 차례로 증착한다.Next, after the buffer oxide film 4 is removed, the first oxide film and the polysilicon layer are sequentially deposited on the entire surface of the semiconductor substrate 1.
그리고 폴리실리콘층 전면에 감광막(도면에는 도시되지 않았음)을 도포한 후에 노광 및 현상공정으로 게이트형성영역에만 감광막이 남도록 선택적으로 패터닝한다.After the photosensitive film (not shown in the drawing) is applied to the entire polysilicon layer, the photoresist film is selectively patterned so that the photoresist film remains only in the gate forming region by the exposure and development processes.
이후에 패터닝된 감광막을 마스크로 폴리실리콘층과 제 1 산화막을 이방성 식각해서 도 1d에 도시한 바와 같이 P웰(2)의 일영역에 게이트산화막(5)과 게이트전극(6)을 형성한다.Thereafter, the polysilicon layer and the first oxide film are anisotropically etched using the patterned photoresist as a mask to form the gate oxide film 5 and the gate electrode 6 in one region of the P well 2 as shown in FIG. 1D.
다음에 도 1e에 도시한 바와 같이 게이트전극(6)을 마스크로 상기 게이트전극(6) 양측의 P웰(2) 표면에 저농도 불순물영역(7)을 형성한다.Next, as shown in FIG. 1E, the low concentration impurity region 7 is formed on the surface of the P well 2 on both sides of the gate electrode 6 using the gate electrode 6 as a mask.
이후에 게이트전극(6)을 포함한 전면에 제 2 산화막을 증착하고 이방성 식각해서 게이트산화막(5)과 게이트전극(6)의 양측면에 측벽스페이서(8)를 형성한다.Thereafter, a second oxide film is deposited on the entire surface including the gate electrode 6 and anisotropically etched to form sidewall spacers 8 on both sides of the gate oxide film 5 and the gate electrode 6.
그리고 상기 게이트전극(6)과 측벽스페이서(8)를 마스크로 그 하부를 제외한 양측 P웰(2)내에 고농도 소오스/드레인영역(9)을 형성한다.A high concentration source / drain region 9 is formed in both side P wells 2 except the lower portion of the gate electrode 6 and the sidewall spacers 8 as a mask.
이때 점선으로 나타낸 부분 즉, 드레인영역에 인접한 게이트 전극(6) 하부에지부분에서 전계가 최대가 된다.At this time, the electric field is maximized at the portion indicated by the dotted line, that is, the lower edge portion of the gate electrode 6 adjacent to the drain region.
상기와 같은 종래 반도체소자의 제조방법은 다음과 같은 문제가 있다.The conventional method of manufacturing a semiconductor device as described above has the following problems.
드레인에 인접한 게이트전극의 하부 에지부분에서 전계가 제일 높고, 이로인하여 이부분에서의 충돌이온 전자쌍(Impact Ionization hole-electron pair)의 생성수가 최대가 되어 브레이크다운 전압(Breakdown voltage:BV)이 낮아지는 문제가 발생된다.The electric field is the highest at the lower edge of the gate electrode adjacent to the drain, which causes the maximum number of impact ion-electron pairs to be generated at this point, resulting in a lower breakdown voltage (BV). A problem arises.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 드레인영역에 인접한 게이트전극 하부에지에서의 전계(electric field)를 완화시켜서 소자의 동작을 안정화 시킬 수 있는 반도체소자 및 그의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and in particular, to provide a semiconductor device and a method of manufacturing the same that can stabilize the operation of the device by reducing the electric field (electric field) at the lower edge of the gate electrode adjacent to the drain region Its purpose is to.
도 1a 내지 도 1e는 종래 반도체소자의 제조방법을 나타낸 공정단면도1A through 1E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2는 본 발명 실시예에 따른 반도체소자의 구조단면도2 is a structural cross-sectional view of a semiconductor device according to an embodiment of the present invention.
도 3a 내지 도 3e는 본 발명 실시예에 따른 반도체소자의 제조방법을 나타낸 공정단면도3A through 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : P웰31: semiconductor substrate 32: P well
33 : 필드산화막 34 : 버퍼산화막33: field oxide film 34: buffer oxide film
35 : 게이트산화막 36 : 게이트전극35: gate oxide film 36: gate electrode
37 : 저농도 불순물영역 38 : 측벽스페이서37 low concentration impurity region 38 sidewall spacer
39 : 고농도 소오스/드레인영역39: high concentration source / drain area
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자는 반도체기판의 일영역에 형성된 버퍼절연막, 상기 버퍼절연막 상부를 덮고 일방향으로 더 연장되어 상기 반도체기판상에 형성된 게이트절연막, 상기 버퍼절연막상측을 포함한 상기 게이트절연막상에 형성된 게이트전극, 상기 버퍼절연막의 일측면과 상기 게이트절연막과 상기 게이트전극의 양측면에 형성된 측벽스페이서, 상기 측벽스페이서 하부 및 상기 버퍼절연막의 일측하부에 형성된 저농도 불순물영역, 상기 게이트절연막과 상기 게이트전극과 상기 측벽스페이서 하부를 제외한 그 양측의 상기 반도체기판에 형성된 고농도 불순물영역을 포함하여 구성됨을 특징으로 한다.The semiconductor device for achieving the above object includes a buffer insulating film formed in one region of a semiconductor substrate, a gate insulating film formed over the buffer insulating film and further extending in one direction on the semiconductor substrate, and including an upper side of the buffer insulating film. A gate electrode formed on a gate insulating film, a sidewall spacer formed on one side of the buffer insulating film and both sides of the gate insulating film and the gate electrode, a low concentration impurity region formed under the sidewall spacer and under a side of the buffer insulating film, and the gate insulating film And a high concentration impurity region formed in the semiconductor substrate on both sides of the gate electrode and the lower side of the sidewall spacer.
상기와 같은 구성을 갖는 본 발명 반도체소자의 제조방법은 반도체기판의 일영역에 버퍼절연막을 형성하는 공정, 상기 버퍼절연막 상부를 덮고 일방향으로 더 연장되도록 게이트절연막을 형성하는 공정, 상기 버퍼절연막 상측을 포함한 상기 게이트절연막 상에 적층되도록 게이트전극을 형성하는 공정, 상기 게이트전극 양측 및 상기 버퍼절연막의 일측하부의 상기 반도체기판에 저농도 불순물영역을 형성하는 공정, 상기 게이트절연막과 상기 게이트전극의 양측 및 상기 버퍼절연막의 일측면에 측벽스페이서를 형성하는 공정, 상기 게이트전극과 상기 측벽스페이서 하부를 제외한 그 양측의 상기 반도체기판에 고농도 불순물영역을 형성하는 공정을 포함함을 특징으로 한다.The method of manufacturing a semiconductor device having the above structure includes the steps of forming a buffer insulating film in one region of a semiconductor substrate, forming a gate insulating film covering the upper portion of the buffer insulating film and extending in one direction, and the upper side of the buffer insulating film. Forming a gate electrode to be stacked on the gate insulating film, including forming a low concentration impurity region in the semiconductor substrate on both sides of the gate electrode and one side of the buffer insulating film, and on both sides of the gate insulating film and the gate electrode and the Forming a sidewall spacer on one side of the buffer insulating film, and forming a high concentration impurity region on the semiconductor substrate on both sides of the semiconductor substrate except for the gate electrode and the lower side of the sidewall spacer.
첨부 도면을 참조하여 본 발명 반도체소자 및 그의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a semiconductor device of the present invention and a method of manufacturing the same will be described.
도 2는 본 발명 실시예에 따른 반도체소자의 구조단면도이고, 도 3a 내지 도 3e는 본 발명 실시예에 따른 반도체소자의 제조방법을 나타낸 공정단면도이다.2 is a structural cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention, and FIGS. 3A to 3E are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.
본 발명 반도체소자는 도 2에 도시한 바와 같이 액티브영역과 필드영역이 정의된 반도체기판(31)의 액티브영역의 일영역에 일정깊이를 갖는 P웰(32)이 형성되어 있고, 상기 필드영역에 필드산화막(33)이 형성되어 있으며, 상기 P웰(32)의 일영역에 일정폭을 갖고 버퍼산화막(34)이 형성되어 있다. 이때 버퍼산화막(34)은 400Å∼600Å정도 두께를 갖고 있다.In the semiconductor device of the present invention, as shown in FIG. 2, a P well 32 having a predetermined depth is formed in one region of an active region of a semiconductor substrate 31 in which an active region and a field region are defined. A field oxide film 33 is formed, and a buffer oxide film 34 is formed in a region of the P well 32 with a predetermined width. At this time, the buffer oxide film 34 has a thickness of about 400 to 600 microns.
그리고 상기 버퍼산화막(34) 상부를 포함하고 일방향으로 더 연장된 일영역에 게이트산화막(35)과 게이트전극(36)이 적층 형성되어 있다.In addition, a gate oxide layer 35 and a gate electrode 36 are stacked in one region including an upper portion of the buffer oxide layer 34 and extending further in one direction.
그리고 버퍼산화막(34)의 일측과 게이트산화막(35)과 게이트전극(36)의 양측면에 측벽스페이서(38)가 형성되어 있고, 상기 게이트전극(36) 일측 하부와 게이트전극(36) 양측의 측벽스페이서(38) 하부와 게이트전극(36) 타측에 인접한 버퍼산화막(34)의 일측 하부에 저농도 불순물영역(37)이 형성되어 있으며, 게이트산화막(35)과 게이트전극(36)과 측벽스페이서(38) 하부를 제외한 그 양측의 P웰(32)내에 고농도 소오스/드레인영역(39)이 형성되어 있다.The sidewall spacers 38 are formed on one side of the buffer oxide layer 34, on both sides of the gate oxide layer 35, and the gate electrode 36. The sidewalls of the lower side of the gate electrode 36 and both sidewalls of the gate electrode 36 are formed. A low concentration impurity region 37 is formed under one side of the buffer oxide layer 34 adjacent to the spacer 38 and the other side of the gate electrode 36. The gate oxide layer 35, the gate electrode 36, and the sidewall spacer 38 are formed. A high concentration source / drain region 39 is formed in the P wells 32 on both sides thereof except for the lower portion.
도면의 점선부분은 드레인영역에 인접한 게이트전극(36) 하부에지에 형성된 버퍼산화막(34)으로 인하여 드레인영역에 바이어스가 인가될 때 게이트전극(36) 하부에지에서의 수직전계(Vertical Electric Field)가 완화되고, 드레인영역에 의한 측면전계(Lateral Electric Field)도 완화된다.The dotted line in the figure shows that a vertical electric field at the lower edge of the gate electrode 36 is applied when a bias is applied to the drain region due to the buffer oxide film 34 formed on the lower edge of the gate electrode 36 adjacent to the drain region. The lateral electric field caused by the drain region is also relaxed.
상기와 같은 구성을 갖는 본 발명 반도체소자의 제조방법은 도 3a에 도시한 바와 같이 액티브영역과 필드영역이 정의된 반도체기판(31)의 액티브영역에 P웰(32)을 형성하고, LOCOS(Local Oxidation of Silicon) 공정으로 상기 필드영역에 필드산화막(33)을 형성한다.In the method of manufacturing a semiconductor device of the present invention having the above-described configuration, as shown in FIG. 3A, a P well 32 is formed in an active region of a semiconductor substrate 31 in which an active region and a field region are defined, and LOCOS (Local). A field oxide film 33 is formed in the field region by an Oxidation of Silicon process.
다음에 도 3b에 도시한 바와 같이 P웰(32)과 필드산화막(33)을 포함한 반도체기판(31)전면에 400Å∼600Å정도 두께를 갖는 버퍼산화막(34)을 성장시킨다.Next, as shown in FIG. 3B, a buffer oxide film 34 having a thickness of about 400 to 600 microseconds is grown on the entire surface of the semiconductor substrate 31 including the P well 32 and the field oxide film 33. As shown in FIG.
이후에 P웰(32)표면에 문턱전압 조절이온을 주입하여서 도 3c와 같이 P웰(32) 표면에 +이온주입영역을 형성한다. 그리고 감광막(도면에는 도시되지 않았음)을 도포한 후에 노광 및 현상공정으로 게이트전극의 고전압 인가 블록 즉, 드레인 에지영역에만 감광막이 남도록 선택적으로 패터닝한다.Thereafter, a threshold voltage control ion is implanted into the surface of the P well 32 to form a + ion implantation region on the surface of the P well 32 as shown in FIG. 3C. After the photoresist film (not shown) is applied, the photoresist film is selectively patterned so that the photoresist film remains only in the high voltage application block of the gate electrode, that is, the drain edge region, during the exposure and development processes.
이후에 패터닝된 감광막을 마스크로 버퍼산화막(34)을 이방성 식각해서 일영역에만 버퍼산화막(34)이 남도록 한다.Afterwards, the buffer oxide film 34 is anisotropically etched using the patterned photoresist as a mask so that the buffer oxide film 34 remains only in one region.
다음에 도 3d에 도시한 바와 같이 버퍼산화막(34)을 포함한 반도체기판(31) 전면에 제 1 산화막과 폴리실리콘층을 차례로 증착한다.Next, as illustrated in FIG. 3D, the first oxide film and the polysilicon layer are sequentially deposited on the entire surface of the semiconductor substrate 31 including the buffer oxide film 34.
그리고 폴리실리콘층 전면에 감광막(도면에는 도시되지 않았음)을 도포한 후에 노광 및 현상공정으로 게이트형성영역에만 감광막이 남도록 선택적으로 패터닝한다.After the photosensitive film (not shown in the drawing) is applied to the entire polysilicon layer, the photoresist film is selectively patterned so that the photoresist film remains only in the gate forming region by the exposure and development processes.
이후에 패터닝된 감광막을 마스크로 폴리실리콘층과 제 1 산화막을 이방성 식각해서 P웰(32) 상부의 버퍼산화막(34)을 포함하고 일방향으로 더 연장되는 영역에 게이트산화막(35)과 게이트전극(36)을 형성한다. 이에 따라서 실질적으로 차후에 드레인영역에 인접한 게이트전극 하부 에지의 게이트산화막(35)이 증가하는 효과가 나타난다.Afterwards, the polysilicon layer and the first oxide layer are anisotropically etched using the patterned photoresist mask as a mask to include the buffer oxide layer 34 on the P well 32 and further extend in one direction to form the gate oxide layer 35 and the gate electrode ( Form 36). As a result, the gate oxide film 35 at the lower edge of the gate electrode adjacent to the drain region is substantially increased later.
다음에 도 3e에 도시한 바와 같이 게이트전극(36)을 마스크로 상기 게이트전극(36) 양측의 P웰(32) 표면에 저농도 불순물영역(37)을 형성한다. 이때 저농도 불순물영역(37)은 버퍼산화막(34)일측 하부의 P웰(32) 표면에도 형성되도록 틸트이온주입공정으로 형성한다.Next, as shown in FIG. 3E, a low concentration impurity region 37 is formed on the surface of the P well 32 on both sides of the gate electrode 36 using the gate electrode 36 as a mask. In this case, the low concentration impurity region 37 is formed by a tilt ion implantation process so as to be formed on the surface of the P well 32 under one side of the buffer oxide film 34.
이후에 게이트전극(36)을 포함한 전면에 제 2 산화막을 증착하고 이방성 식각해서 게이트산화막(35)과 게이트전극(36)의 양측면에 측벽스페이서(38)를 형성한다.Thereafter, a second oxide film is deposited on the entire surface including the gate electrode 36 and anisotropically etched to form sidewall spacers 38 on both sides of the gate oxide film 35 and the gate electrode 36.
그리고 상기 게이트전극(36)과 측벽스페이서(38)를 마스크로 그 하부를 제외한 양측 P웰(32)내에 고농도 소오스/드레인영역(39)을 형성한다.A high concentration source / drain region 39 is formed in both P-wells 32 except the lower portion of the gate electrode 36 and the sidewall spacers 38 as a mask.
도면의 점선부분은 드레인영역에 인접한 게이트전극(36) 하부에지에 형성된 버퍼산화막(34)으로 인하여 드레인영역에 바이어스가 인가될 때 게이트전극(36) 하부에지에서의 수직전계가 완화되고, 드레인영역에 의한 측면전계도 완화된다.In the dotted line in the figure, the vertical field at the lower edge of the gate electrode 36 is relaxed when a bias is applied to the drain region due to the buffer oxide film 34 formed on the lower edge of the gate electrode 36 adjacent to the drain region. The lateral electric field is also relaxed.
상기와 같은 본 발명 반도체소자 및 그의 제조방법은 다음과 같은 효과가 있다.The semiconductor device of the present invention as described above and a method of manufacturing the same have the following effects.
드레인영역에 인접한 게이트전극 하부에지에 형성된 버퍼산화막으로 인하여 게이트전극 하부 에지에서의 수직전계와 측면전계가 완화되어서 고내압 소자에 구현할 수 있으므로 고전압 적용을 위한 제품설계에 유용하게 사용할 수 있다.Due to the buffer oxide film formed on the lower edge of the gate electrode adjacent to the drain region, the vertical and side electric fields at the lower edge of the gate electrode are alleviated so that they can be implemented in a high breakdown voltage device.
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