KR100383002B1 - Method for fabricating a semiconductor device - Google Patents
Method for fabricating a semiconductor device Download PDFInfo
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- KR100383002B1 KR100383002B1 KR10-2000-0047185A KR20000047185A KR100383002B1 KR 100383002 B1 KR100383002 B1 KR 100383002B1 KR 20000047185 A KR20000047185 A KR 20000047185A KR 100383002 B1 KR100383002 B1 KR 100383002B1
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- forming
- gate electrode
- semiconductor substrate
- semiconductor device
- drain region
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 230000005684 electric field Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
Abstract
본발명은 반도체 소자의 제조방법에 관한 것으로, 특히 게이트 전극에 의해 유도되는 드레인 누설전류를 저감할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of reducing a drain leakage current induced by a gate electrode.
본 발명에 따른 반도체 소자의 제조방법은 반도체 기판의 상면에 게이트 산화막을 형성하는 공정과, 상기 게이트 산화막 상면에 게이트 전극을 형성하는 공정과, 상기 게이트 전극 양측 반도체 기판에 리세스를 형성하는 공정과, 상기 리세스내의 상기 반도체 기판 표면근방에 저농도 드레인 영역을 형성하는 공정과, 상기 게이트전극의 양측벽에 측벽 스페이서를 형성하는 공정과, 상기 측벽 스페이서 양측의 반도체 기판내에 소스/드레인 영역을 형성하는 공정을 포함한다.A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate oxide film on the upper surface of the semiconductor substrate, forming a gate electrode on the upper surface of the gate oxide film, forming a recess in the semiconductor substrate on both sides of the gate electrode; Forming a low concentration drain region near the surface of the semiconductor substrate in the recess; forming sidewall spacers on both sidewalls of the gate electrode; and forming source / drain regions in the semiconductor substrates on both sidewall spacers. Process.
Description
본발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 게이트 전극의 수평방향의 전계에 의해 발생하는 드레인 누설전류를 저감할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of reducing the drain leakage current generated by the electric field in the horizontal direction of the gate electrode.
우선 종래의 반도체 소자의 제조방법을 살펴보면 다음과 같다.First, a manufacturing method of a conventional semiconductor device is as follows.
먼저 도1a에 도시한 바와 같이 반도체 기판(100)의 상면에 게이트 산화막(101)을 형성한다.First, as shown in FIG. 1A, a gate oxide film 101 is formed on the upper surface of the semiconductor substrate 100.
다음으로 상기 게이트 산화막(101)의 상면에 게이트 전극(102)을 형성한다.Next, the gate electrode 102 is formed on the upper surface of the gate oxide film 101.
다음으로 도1b에 도시한 바와 같이 상기 게이트 전극(102)의 양측 반도체 기판(100)내에 불순물 이온을 주입한 후 열처리 공정을 거쳐 저농도 드레인 영역(LDD; lightly doped drain)(103)을 형성한다.Next, as shown in FIG. 1B, lightly doped drain (LDD) 103 is formed by implanting impurity ions into both semiconductor substrates 100 of the gate electrode 102 and performing a heat treatment process.
다음으로 도1c에 도시한 바와 같이 상기 게이트 전극(102)의 양측벽에 측벽 스페이서(104)를 형성한다.Next, as shown in FIG. 1C, sidewall spacers 104 are formed on both sidewalls of the gate electrode 102.
다음으로 도1d에 도시한 바와 같이 상기 측벽 스페이서(104) 양측 반도체 기판(100)내에 불순물 이온주입을 실시한 후 열처리 공정을 수행하여 소스/드레인 영역(105)을 형성한다.Next, as shown in FIG. 1D, impurity ions are implanted into the semiconductor substrate 100 at both sides of the sidewall spacer 104, and a heat treatment is performed to form the source / drain regions 105.
그러나 상기와 같은 방법으로 제조된 반도체 소자는 게이트 전극의 수평방향의 전계(lateral electric field)에 의한 드레인 누설전류가 크다는 단점이 있었다. 즉 게이트전극에 저전압이 인가되고 드레인 영역에 고전압이 인가된 경우 게이트 전극과 저농도드레인영역(LDD)(103)이 중첩된 부분에서 밴드 투 밴드 터널링(band to band tunneling) 및 밴드 트랩 밴드 터널링(band trap band tunneling)에 의해 드레인과 반도체 기판사이에 누설전류가 발생한다.However, the semiconductor device manufactured by the above method has a disadvantage in that the drain leakage current due to the horizontal electric field of the gate electrode is large. That is, when a low voltage is applied to the gate electrode and a high voltage is applied to the drain region, band to band tunneling and band trap band tunneling at a portion where the gate electrode and the low concentration drain region (LDD) 103 overlap each other. Trap band tunneling causes leakage current between the drain and the semiconductor substrate.
종래에는 드레인 누설전류가 수직방향 전계(vertical electric field)에 의해 주로 발생하였다. 그러나 최근 반도체 소자의 집적도가 증가되면서, 게이트 길이가 매우 짧아졌다. 그로인하여, 수평방향 전계(lateral field)의 드레인 누설전류에 대한 영향이 크게 부각되고 있다.Conventionally, drain leakage current is mainly generated by a vertical electric field. However, with the recent increase in the degree of integration of semiconductor devices, the gate length has become very short. As a result, the influence on the drain leakage current of the lateral field is greatly highlighted.
상기와 같은 누설전류를 저감할 수 있는 방법은 저농도 드레인 영역(103)의 불순물 도핑 농도를 줄이거나 측벽 스페이서의 폭을 증가시켜 저농도 드레인 영역(103)을 확장시키는 방법이 있다. 그러나 도핑 농도를 줄이는 방법은 현재 개발된 장비에 의해 농도를 낮추는데는 한계가 있다. 또한 측벽스페이서의 폭을 증가시키는 방법은, 반도체 소자의 집적도를 저해하므로 채택하기 어려운 점이 있었다.A method of reducing the leakage current as described above may include reducing the impurity doping concentration of the low concentration drain region 103 or increasing the width of the sidewall spacers to expand the low concentration drain region 103. However, the method of reducing the doping concentration is limited to lowering the concentration by the currently developed equipment. In addition, the method of increasing the width of the sidewall spacers is difficult to adopt because it reduces the degree of integration of semiconductor elements.
본발명은 상기와 같은 문제점에 비추어 안출된 것으로, 반도체 소자의 집적도를 저해하지 않으면서 저농도 드레인 영역의 길이를 증가시키는 방법을 적용하여 게이트 전극의 수평방향 전계에 의한 드레인 누설전류를 저감할 수 있는 반도체 소자의 제조방법을 제공하는 것을 그 목적으로 한다.The present invention has been made in view of the above problems, and by applying a method of increasing the length of the low concentration drain region without inhibiting the integration of the semiconductor device, it is possible to reduce the drain leakage current by the horizontal electric field of the gate electrode. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
상기와 같은 본 발명의 목적을 달성하기 위하여 본 발명은, 반도체 기판의 상면에 게이트 산화막을 형성하는 공정과, 상기 게이트 산화막 상면에 게이트 전극을 형성하는 공정과, 상기 게이트 전극 양측 반도체 기판에 리세스를 형성하는 공정과,In order to achieve the object of the present invention as described above, the present invention, the process of forming a gate oxide film on the upper surface of the semiconductor substrate, the process of forming a gate electrode on the upper surface of the gate oxide film, and recessed in the semiconductor substrate on both sides of the gate electrode Forming a process,
상기 리세스내의 상기 반도체 기판 표면근방에 저농도 드레인 영역을 형성하는 공정과, 상기 게이트전극의 양측벽에 측벽 스페이서를 형성하는 공정과, 상기 측벽 스페이서 양측의 반도체 기판내에 소스/드레인 영역을 형성하는 공정을 순차 수행하는 것을 특징으로 하는 반도체 소자의 제조방법을 제공한다.Forming a low concentration drain region near the surface of the semiconductor substrate in the recess, forming a sidewall spacer on both sidewalls of the gate electrode, and forming a source / drain region in the semiconductor substrate on both sidewall spacers It provides a method for manufacturing a semiconductor device, characterized in that to perform sequentially.
상기 목적을 달성하기 위하여 본 발명은 상기 저농도 드레인 영역을 형성하는 공정이, 상기 게이트 전극 하방의 상기 반도체 기판내에도 저농도 드레인 영역이 형성되도록 하는 공정인 것을 특징으로 하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, characterized in that the step of forming the low concentration drain region is a step of forming a low concentration drain region in the semiconductor substrate below the gate electrode. .
상기 목적을 달성하기 위하여 본 발명은 상기 저농도 드레인 영역을 형성하는 공정이 경사각 이온주입법을 이용하여 상기 반도체 기판내에 불순물을 주입하는 공정인 것을 특징으로 하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, characterized in that the step of forming the low concentration drain region is a step of implanting impurities into the semiconductor substrate by using an oblique angle ion implantation method.
도1a 내지 도1d는 종래 반도체 소자의 제조공정 순서도이다.1A to 1D are flowcharts of a manufacturing process of a conventional semiconductor device.
도2a 내지 도2d는 본 발명에 따른 반도체 소자의 제조공정 순서도이다.2A to 2D are flowcharts of a manufacturing process of a semiconductor device according to the present invention.
***** 도면부호의 설명 ********** Explanation of Drawings *****
100 : 반도체 기판100: semiconductor substrate
101 : 게이트 산화막101: gate oxide film
102 : 게이트 전극102: gate electrode
103 : 저농도 드레인 영역103: low concentration drain region
104 : 측벽 스페이서104: sidewall spacer
105 : 소스/드레인 영역105: source / drain area
200 : 반도체 기판200: semiconductor substrate
201 : 게이트 산화막201: gate oxide film
202 : 도전층202: conductive layer
202a : 게이트 전극202a: gate electrode
203 : 절연층203: insulating layer
203a : 절연층 패턴203a: insulating layer pattern
204 : 리세스204 recess
205 : 저농도 드레인 영역205: low concentration drain region
206 : 측벽 스페이서206: sidewall spacer
본 발명에 따른 반도체 소자의 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
먼저 도2a에 도시한 바와 같이 반도체 기판(200)의 상면에 게이트 산화막(201)을 형성한다. 다음으로 상기 게이트 산화막(201)의 상면에 도핑된 폴리실리콘층과 같은 도전층(202)을 형성한다. 다음으로 상기 도전층(202)의 상면에 절연층(203)을 형성한다.First, as shown in FIG. 2A, a gate oxide film 201 is formed on the upper surface of the semiconductor substrate 200. Next, a conductive layer 202, such as a doped polysilicon layer, is formed on the top surface of the gate oxide film 201. Next, an insulating layer 203 is formed on the upper surface of the conductive layer 202.
다음으로 도2b에 도시한 바와 같이 상기 도전층(202) 및 상기 절연층(203)을 패터닝하여 게이트 전극(202a) 및 절연층 패턴(203a)을 형성한다.Next, as shown in FIG. 2B, the conductive layer 202 and the insulating layer 203 are patterned to form a gate electrode 202a and an insulating layer pattern 203a.
다음으로 도2c에 도시한 바와 같이 절연층 패턴(203a)을 식각 마스크로하여 상기 게이트 전극(202a) 양측의 반도체 기판을 식각하여 리세스(204)를 형성한다.Next, as shown in FIG. 2C, the semiconductor substrates on both sides of the gate electrode 202a are etched using the insulating layer pattern 203a as an etching mask to form a recess 204.
다음으로, 상기 리세스(204) 부의 상기 반도체 기판(200) 표면부 근방에 불순물 이온을 주입하여 저농도 드레인 영역(LDD)(205)을 형성한다. 이때, 불순물 이온을 주입하는 공정은 경사각 이온주입법(tilt ion implanting)을 적용하여 상기 게이트 전극(202) 하부의 반도체 기판(200)내에도 저농도 드레인 영역(205)이 형성되도록 한다.Next, impurity ions are implanted in the vicinity of the surface portion of the semiconductor substrate 200 in the recess 204 to form a low concentration drain region (LDD) 205. In this case, the implantation of impurity ions may be performed to form a low concentration drain region 205 in the semiconductor substrate 200 under the gate electrode 202 by applying a tilt ion implantation method.
다음으로 도2d에 도시한 바와 같이 게이트 전극(202a)의 양측 측벽 및 게이트 전극(202a) 하부의 반도체 기판(200)의 측벽에 측벽 스페이서(206)를 형성한다. 다음으로 상기 측벽 스페이서(206)의 양측 반도체 기판(200)내에 불순물 이온을 주입하여 소스/드레인 영역을 형성함으로써 반도체 소자의 제조공정을 완료한다.Next, as shown in FIG. 2D, sidewall spacers 206 are formed on both sidewalls of the gate electrode 202a and the sidewalls of the semiconductor substrate 200 under the gate electrode 202a. Next, impurity ions are implanted into both semiconductor substrates 200 of the sidewall spacers 206 to form source / drain regions, thereby completing the manufacturing process of the semiconductor device.
상기와 같은 본 발명의 반도체 소자 제조공정에 따르면, 반도체 소자의 집적도를 저해하지 않고 저농도 드레인 영역(LDD)의 길이를 종래에 비해 증가시켜 게이트 전극의 수평방향 전계를 줄일 수 있는 효과가 있다. 그로 인하여 게이트 전극의 전계에 의한 드레인 누설전류를 저감함으로써 반도체 소자의 신뢰성을 향상시키는 효과가 있다.According to the semiconductor device manufacturing process of the present invention as described above, it is possible to reduce the horizontal electric field of the gate electrode by increasing the length of the low concentration drain region (LDD) compared to the prior art without inhibiting the integration degree of the semiconductor device. Therefore, there is an effect of improving the reliability of the semiconductor device by reducing the drain leakage current by the electric field of the gate electrode.
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| KR10-2000-0047185A KR100383002B1 (en) | 2000-08-16 | 2000-08-16 | Method for fabricating a semiconductor device |
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| KR100383002B1 true KR100383002B1 (en) | 2003-05-09 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6348868A (en) * | 1986-08-19 | 1988-03-01 | Toshiba Corp | Manufacture of schottky gate type field effect transistor |
| JPH0645365A (en) * | 1992-07-22 | 1994-02-18 | Nec Corp | Semiconductor device and its manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6348868A (en) * | 1986-08-19 | 1988-03-01 | Toshiba Corp | Manufacture of schottky gate type field effect transistor |
| JPH0645365A (en) * | 1992-07-22 | 1994-02-18 | Nec Corp | Semiconductor device and its manufacture |
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| KR20020014097A (en) | 2002-02-25 |
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