KR20020011549A - Method of forming a contact plug in a high voltage semiconductor device - Google Patents
Method of forming a contact plug in a high voltage semiconductor device Download PDFInfo
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- KR20020011549A KR20020011549A KR1020000044885A KR20000044885A KR20020011549A KR 20020011549 A KR20020011549 A KR 20020011549A KR 1020000044885 A KR1020000044885 A KR 1020000044885A KR 20000044885 A KR20000044885 A KR 20000044885A KR 20020011549 A KR20020011549 A KR 20020011549A
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- Prior art keywords
- forming
- ion implantation
- contact plug
- contact
- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
Description
본 발명은 고전압 반도체 소자의 콘택 플러그 형성 방법에 관한 것으로, 특히 저전압 소자의 드레인에 인가되는 고전압을 강하시키므로써 고전압을 수용하기 위한 소자 구조 변경 공정 없이 고전압 소자와 저전압 소자가 one-chip 상에 존재하는 회로를 제조할 수 있는 고전압 반도체 소자의 콘택 플러그 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact plug of a high voltage semiconductor device. In particular, a high voltage device and a low voltage device exist on a single chip without a device structure change process for accommodating a high voltage by lowering a high voltage applied to a drain of the low voltage device. The contact plug formation method of the high voltage semiconductor element which can manufacture the circuit to make.
일반적으로 고전압 소자는 모터 구동등의 고전압 또는 고전류 출력을 필요로 하는 경우나, 외부 시스템에서 고전압 입력이 존재하는 경우에 주로 사용한다. 그리고, 내부 회로는 고전압이 필요없는 경우가 대부분이기 때문에 통상의 경우에 고전압구동 부분과 저전압 구동 부분이 one-chip 상에 동시에 존재한다. 저전압 구동 부분과 고전압 구동 부분을 동시에 형성하기 위해서는 저전압 소자 제조 공정에 기반을 두고 형성하면서 고전압을 수용할 수 있도록 소자 구조를 변경하게 된다.In general, a high voltage device is mainly used when a high voltage or high current output such as a motor driving light is required or when a high voltage input is present in an external system. And since the internal circuits do not need high voltages in most cases, the high voltage driving portion and the low voltage driving portion exist on the one-chip at the same time in the normal case. In order to simultaneously form the low voltage driving part and the high voltage driving part, the device structure is changed to accommodate the high voltage while forming based on the low voltage device manufacturing process.
대다수의 경우, 게이트 전극에는 저전압 입력이 가해지고, 드레인 쪽에만 고전압이 인가되는 구조를 가지고 있다. 이런 경우에 고전압 소자에서 졍선 도핑 구조(Junction dopping structure)를 변경해야 한다. 저농도 깊은 접합을 형성하여 전압강하를 유도하고, 이에 따라서 전압 양단에 가해지는 전기장의 크기를 임계값보다 작게 유지함으로써 높은 항복 전압을 얻게 된다. 여기서, 일반적인 임계전기장의 크기는 대략 1E5V/cm 정도이다. 이렇게 높은 항복 전압을 얻기 위하여 깊은 접합을 갖는 소오스/드레인을 형성하게 되면 소자의 면적이 증가하여 집적도를 감소시키는 요인이 된다.In many cases, a low voltage input is applied to the gate electrode, and a high voltage is applied only to the drain side. In this case, the junction doping structure must be changed in the high voltage device. By forming a low concentration deep junction to induce a voltage drop, a high breakdown voltage is obtained by keeping the magnitude of the electric field across the voltage less than the threshold. Here, the size of a typical critical electric field is about 1E5V / cm. Forming a source / drain having a deep junction in order to obtain such a high breakdown voltage increases the area of the device and decreases the degree of integration.
게이트 산화막의 경우에는 드레인 전극에 가해지는 전압과 게이트 전극에 가해지는 전압간의 GIDL(Gate-Induced Drain Leakage) 현상에 의한 브레이크 다운을 감소시키고, F-N 터널링(Fowler-Nordheim tunneling)이 발생하는 것을 방지하기 위하여 두꺼운 두께로 형성해야 한다. 즉, 저전압 소자 구조를 기초로 하여 소자를 형성할 경우, 동작 전압에 따라서 변화되는 정도는 다르지만, 웰구조 및 게이트 산화막의 두께로 두껍게 형성해야 한다. 또한, 서로 다른 웰을 구성하는 공정이 필요하며, 접합 파괴 전압을 최적화하기 위한 많은 시뮬레이션 및 실험이 필요하고, 게이트 산화막을 두 가지 이상의 두께로 형성해야 하기 때문에 2단계 게이트 산화막 형성(2-step gate oxidation) 기술을 사용해야 한다.In the case of the gate oxide film, the breakdown caused by the gate-induced drain leakage (GIDL) phenomenon between the voltage applied to the drain electrode and the voltage applied to the gate electrode is reduced, and the FN tunneling is prevented from occurring. In order to form a thick thickness. That is, when the element is formed based on the low voltage element structure, the degree of change depending on the operating voltage is different, but it must be formed thick with the thickness of the well structure and the gate oxide film. In addition, two-step gate formation is required because a process for constructing different wells, many simulations and experiments for optimizing a junction breakdown voltage, and a gate oxide layer having two or more thicknesses are required. oxidation technology should be used.
상기한 바와 같이, 고전압 구동 소자와 저전압 구동 소자가 한 칩 상에 존재하게 되면 상술한 방법으로 소자를 제조하야 하나, 이러한 방법은 공정의 난이도가 높고 너무 복잡하며, 소자의 신뢰성을 저하시키게 된다.As described above, when the high voltage driving device and the low voltage driving device are present on one chip, the device must be manufactured by the above-described method, but this method is difficult and too complicated in the process, and degrades the reliability of the device.
따라서, 본 발명은 콘택 플러그를 펀치쓰루(Punchthrough) 전압이 적절히 조절되는 베이스-오픈 바이폴라 트랜지스터(Base-open bipolar transistor) 구조로 형성하여 드레인에 인가되는 고전압을 강하시키므로써 고전압을 수용하기 위한 소자의 구조 변경 없이 용이하게 소자를 형성하면서 소자의 신뢰성을 향상시킬 수 있는 고전압 반도체 소자의 콘택 플러그 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention forms a contact plug with a base-open bipolar transistor structure in which a punchthrough voltage is appropriately adjusted, thereby lowering a high voltage applied to a drain, thereby providing a device for accommodating a high voltage. It is an object of the present invention to provide a method for forming a contact plug of a high voltage semiconductor device which can improve the reliability of the device while easily forming the device without changing the structure.
도 1은 본 발명에 따른 고전압 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위하여 도시한 소자의 단면도.1 is a cross-sectional view of a device shown for explaining a method for forming a contact plug of a high voltage semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판 2 : 필드 산화막1: semiconductor substrate 2: field oxide film
3 : 게이트 산화막 4 : 게이트 전극3: gate oxide film 4: gate electrode
5a, 6a : 저농도 불순물 영역 5b, 6a : 고농도 불순물 영역5a, 6a: low concentration impurity region 5b, 6a: high concentration impurity region
5 : 드레인 6 : 소오스5: drain 6: source
7 : 측벽 스페이서 8 : 층간 절연막7 side wall spacer 8 interlayer insulating film
9 : 감광막 패턴 10a : 제 1 도프트 폴리실리콘9: photosensitive film pattern 10a: first doped polysilicon
10b : 제 2 도프트 폴리실리콘 10 : 콘택 플러그10b: second doped polysilicon 10: contact plug
본 발명에 따른 고전압 반도체 소자의 콘택 플러그 형성 방법은 저전압 구동 소자가 형성되고, 층간 절연막에 형성된 제 1 콘택홀에 의해 상기 저전압 구동 소자의 제 1 접합부가 노출되는 반도체 기판이 제공되는 단계, 제 1 콘택홀을 폴리실리콘으로 매립한 후 평탄화하는 단계, 1차 이온 주입 공정으로 폴리실리콘에 제 1 불순물을 주입하는 단계, 2차 이온 주입 공정으로 폴리실리콘의 목표 높이에 1차 이온 주입 공정의 불순물과 반대되는 타입의 제 2 불순물을 주입하여 수직 방향의 바이폴라 트랜지스터 구조를 이루는 제 1 콘택 플러그를 형성하는 단계 및 제 2 접합부를 개방시키는 제 2 콘택홀을 형성한 후 제 2 콘택 플러그를 형성한 후 상부 금속 배선을 형성하는 단계를 포함하여 이루어진다.In the method of forming a contact plug of a high voltage semiconductor device according to the present invention, the method includes: forming a low voltage driving device, and providing a semiconductor substrate on which a first junction of the low voltage driving device is exposed by a first contact hole formed in an interlayer insulating film. Filling the contact hole with polysilicon and then flattening the first impurity implantation into the polysilicon using a primary ion implantation process and a second ion implantation process impurity from the primary ion implantation process at the target height of the polysilicon Forming a first contact plug forming a bipolar transistor structure in a vertical direction by implanting a second impurity of an opposite type, forming a second contact hole for opening the second junction, and then forming a second contact plug Forming a metal wiring.
상기의 단계에서, 제 1 접합부는 트랜지스터의 드레인이고, 제 2 접합부는 소오스이다.In the above step, the first junction is the drain of the transistor and the second junction is the source.
제 1 불순물은 제 1 접합부에 주입된 불순물과 동일한 타입의 것을 이용한다.The first impurity uses the same type as the impurity injected into the first junction.
2차 이온 주입 공정은 이온 주입 에너지에 따라 상기 제 2 불순물의 높이, 폭 및 농도를 조절하여 제 1 콘택 플러그의 전압 강하용 펀치쓰루 전압을 조절한다.The secondary ion implantation process adjusts the punch-through voltage for voltage drop of the first contact plug by adjusting the height, width and concentration of the second impurity according to the ion implantation energy.
1차 및 2차 이온 주입 공정은 제 1 콘택홀을 형성할 때 사용한 마스크를 이온 주입 마스크로 이용한다.In the primary and secondary ion implantation processes, masks used to form the first contact hole are used as ion implantation masks.
제 2 콘택 플러그는 텅스텐, 폴리실리콘 등을 이용하여 형성한다.The second contact plug is formed using tungsten, polysilicon, or the like.
금속 배선을 형성하기 전에 상기 제 1 및 제 2 콘택 플러그 상에 확산 방지막 및 콘택 저항을 낮추기 위한 오믹 콘택층을 형성한다.Before forming the metal wiring, an ohmic contact layer for lowering the diffusion barrier and the contact resistance is formed on the first and second contact plugs.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1a 내지 도 1c는 본 발명에 따른 고전압 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of devices sequentially illustrated to explain a method for forming a contact plug of a high voltage semiconductor device according to the present invention.
도 1a를 참조하면, 반도체 기판(1) 상에 필드 산화막(2)을 형성하고, 전체 상부에 게이트 산화막(3) 및 게이트 전극용 폴리실리콘층(4)을 형성한 후 게이트 마스크를 이용한 식각 공정으로 폴리실리콘층(4) 및 게이트 산화막(3)을 패터닝하여 게이트 전극을 형성한다. 1차 불순물 주입으로 저농도 불순물 영역(5a 및 6a)을 형성하고, 게이트 전극의 측벽에 질화막 스페이서(7)를 형성한다. 2차 불순물 주입으로 고농도 불순물 영역(5b 및 6b)을 형성하여 LDD 구조의 드레인(5) 및 소오스(6)를 형성하여 저전압 구동 소자를 제조한다. 이후, 상부 배선(도시되지 않음)과의 절연을 위하여 전체 상부에 층간 절연막(8)을 형성하고, 드레인 콘택홀 마스크를 이용해 감광막 패턴(9)을 형성한다. 감광막 패턴(9)을 이용한 식각 공정으로 층간 절연막(8)을 식각하여 드레인(5) 영역이 노출되는 드레인 콘택홀을 형성한다.Referring to FIG. 1A, a field oxide film 2 is formed on a semiconductor substrate 1, a gate oxide film 3 and a polysilicon layer 4 for a gate electrode are formed over the entire surface, and an etching process using a gate mask is performed. The polysilicon layer 4 and the gate oxide film 3 are then patterned to form a gate electrode. Low impurity impurity regions 5a and 6a are formed by primary impurity implantation, and nitride film spacers 7 are formed on sidewalls of the gate electrode. High concentration impurity regions 5b and 6b are formed by secondary impurity implantation to form a drain 5 and a source 6 of the LDD structure to fabricate a low voltage driving device. Subsequently, an interlayer insulating film 8 is formed over the entire upper portion to insulate the upper wiring (not shown), and the photosensitive film pattern 9 is formed using a drain contact hole mask. The interlayer insulating film 8 is etched by an etching process using the photosensitive film pattern 9 to form a drain contact hole in which the drain 5 region is exposed.
도 1b를 참조하면, 콘택홀 내부에 높은 저항체로 사용될 박막을 증착하여 저전압 구동 소자의 드레인 콘택홀을 매립하고, 1차 이온 주입 공정으로 불순물을 주입한다.Referring to FIG. 1B, a thin film to be used as a high resistor is deposited inside a contact hole to fill a drain contact hole of a low voltage driving device, and implant impurities into a primary ion implantation process.
본 발명에서는 드레인 콘택홀 내부를 매립할 박막으로 도핑 구조 변경이 용이하고, 이에 따른 전기적 특성 제거가 용이한 폴리실리콘으로 드레인 콘택홀을 매립한다. 이후, 화학적 기계적 연마 또는 에치백 공정등 공지의 기술로 불필요한 부분의 폴리실리콘을 제거해 드레인 콘택홀 내부에만 잔류하도록 한다. 제 1 이온 주입 공정은 콘택홀 형성 마스크를 이온 주입 마스크로 이용하여 폴리실리콘에 불순물을 주입하여 제 1 도프트 폴리실리콘(10a)을 형성하는 공정으로, 드레인(5)을 형성하기 위하여 주입한 불순물과 동일한 타입의 불순물을 주입하여 준다.In the present invention, the doping structure is easily changed into a thin film to fill the drain contact hole, and the drain contact hole is filled with polysilicon which is easy to remove electrical characteristics. Then, the polysilicon of the unnecessary portion is removed by a known technique such as chemical mechanical polishing or etch back process so as to remain only in the drain contact hole. The first ion implantation process is a process of injecting impurities into polysilicon using a contact hole forming mask as an ion implantation mask to form the first doped polysilicon 10a. The impurities implanted to form the drain 5 are formed. Inject impurities of the same type as.
도 1c를 참조하면, 2차 이온 주입 공정으로 1차 이온 주입시 주입했던 불순물과 반대되는 타입의 불순물을 제 1 도프트 폴리실리콘(10a)의 목표 높이에 주입한다. 2차 이온 주입 공정을 실시하므로써 형성된 제 2 도프트 폴리실리콘(10b)은 베이스 부분이 되어, 수직의 바이폴라 트랜지스터로 이루어진 콘택 플러그(10)가 형성된다.Referring to FIG. 1C, impurities of a type opposite to impurities implanted during primary ion implantation in a secondary ion implantation process are implanted into a target height of the first doped polysilicon 10a. The second doped polysilicon 10b formed by performing the secondary ion implantation process becomes a base portion, and a contact plug 10 made of a vertical bipolar transistor is formed.
2차 이온 주입 공정은 이온 주입 에너지를 조절하므로써, 트랜지스터의 베이스 부분을 이루는 제 2 도프트 폴리실리콘(10b)의 형성 깊이, 폭, 농도를 제어할 수 있다. 즉, 이온 주입 에너지를 조절하여 트랜지스터의 펀치쓰루(Punchthrough) 전압을 조절할 수 있다는 것을 의미하며, 이는 드레인(5)으로 인가되는 고전압을 얼마든지 원하는 전압으로 강하시킬 수 있다.The secondary ion implantation process controls the formation depth, width, and concentration of the second doped polysilicon 10b forming the base portion of the transistor by adjusting the ion implantation energy. That is, the punchthrough voltage of the transistor can be adjusted by adjusting the ion implantation energy, which can lower the high voltage applied to the drain 5 to a desired voltage.
상기의 공정에서 1차 및 2차 이온 주입 공정은 드레인 콘택홀을 형성할 때 사용한 마스크를 이온주입 마스크로 이용하여 실시한다. 1차 이온 주입 공정은 바이폴라 트랜지스터의 이미터(Emitter)와 콜렉터(Collector)를 형성하는 공정이고, 2차 이온 주입 공정은 바이폴라 트랜지스터의 베이스를 형성하는 공정이다.In the above process, the primary and secondary ion implantation processes are performed using the mask used to form the drain contact hole as the ion implantation mask. The primary ion implantation process is a process of forming an emitter and a collector of a bipolar transistor, and the secondary ion implantation process is a process of forming a base of a bipolar transistor.
도 1d를 참조하면, 소오스 콘택홀 마스크를 이용하여 소오스(6) 상부의 층간 절연막(8)을 제거해 소오스 콘택홀을 형성한다. 이후, 텅스텐 등을 이용하여 소오스 콘택홀을 매립하여 소오스 콘택 플러그(11)를 형성한다. 바이폴라 트랜지스터형 콘택 플러그(10)와 소오스 콘택 플러그(11) 상에 TiN막(12) 등을 형성하여 공지된 기술의 확산방지막 또는 오믹 콘택을 이루기 위한 오믹 콘택층을 형성한 후 금속 배선(13)을 형성한다.Referring to FIG. 1D, a source contact hole is formed by removing the interlayer insulating layer 8 on the source 6 using a source contact hole mask. Thereafter, the source contact hole 11 is embedded by using tungsten or the like to form the source contact plug 11. After forming the TiN film 12 or the like on the bipolar transistor type contact plug 10 and the source contact plug 11 to form an ohmic contact layer for forming a diffusion barrier film or ohmic contact of a known technique, the metal wiring 13 is formed. To form.
상기의 바이폴라 트랜지스터 구조의 콘택 플러그는 트랜지스터뿐만이 아니라 고전압을 인가받는 모든 저전압 구동 소자의 콘택 플러그로 사용할 수 있다.The contact plug of the bipolar transistor structure can be used not only as a transistor but also as a contact plug of all low voltage driving devices to which a high voltage is applied.
상술한 바와 같이, 본 발명은 바이폴라 트랜지스터를 수직으로 형성하여 콘택 플러그로 사용해 고전압을 강하시켜 저전압 구동 소자에 인가하므로써, 저전압 구동 소자의 구조를 변경하기 위한 공정이 필요없어 공정의 난이도가 감소하고, 소자의 신뢰성을 향상시켜 수율을 증가시키는 효과가 있다.As described above, according to the present invention, since the bipolar transistor is vertically formed and used as a contact plug, the high voltage is dropped and applied to the low voltage driving device, thereby eliminating the need for changing the structure of the low voltage driving device, thereby reducing the difficulty of the process. There is an effect of increasing the yield by improving the reliability of the device.
Claims (7)
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720518B1 (en) * | 2005-12-28 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating semiconductor device |
| KR100731061B1 (en) * | 2005-12-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating semiconductor device |
| KR100815956B1 (en) * | 2006-09-05 | 2008-03-21 | 동부일렉트로닉스 주식회사 | Method of Manufacturing Gate Contact of Semiconductor Device |
| US7585710B2 (en) | 2004-08-16 | 2009-09-08 | Samsung Electronics Co, Ltd. | Methods of forming electronic devices having partially elevated source/drain structures |
| US9318477B2 (en) | 2013-09-27 | 2016-04-19 | Samsung Electronics Co., Ltd. | Semiconductor device having dummy cell array |
-
2000
- 2000-08-02 KR KR1020000044885A patent/KR20020011549A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7585710B2 (en) | 2004-08-16 | 2009-09-08 | Samsung Electronics Co, Ltd. | Methods of forming electronic devices having partially elevated source/drain structures |
| KR100720518B1 (en) * | 2005-12-28 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating semiconductor device |
| KR100731061B1 (en) * | 2005-12-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating semiconductor device |
| KR100815956B1 (en) * | 2006-09-05 | 2008-03-21 | 동부일렉트로닉스 주식회사 | Method of Manufacturing Gate Contact of Semiconductor Device |
| US9318477B2 (en) | 2013-09-27 | 2016-04-19 | Samsung Electronics Co., Ltd. | Semiconductor device having dummy cell array |
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