JPH07273329A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device whose parasitic capacity in a junction part between a source region, a drain region and a well region is reduced and a manufacturing method thereof. CONSTITUTION:An insulation film 5 is formed on a surface of a semiconductor substrate 4 and a gate electrode 3 is formed in an upper part thereof. Then, a first sidewall 2 is formed in a side surface of the gate electrode 3 (Step 101). Ion implantation of impurities of reverse conductivity type of the semiconductor substrate 4 is carried out using the first sidewall 2 as an ion implantation mask and a first impurity region 6 of low impurity concentration is formed (Step 102). Then, a second sidewall 7 is formed in a side surface of the first sidewall 2 (Step 103). Ion implantation of impurities of reverse conductivity type of the semiconductor substrate 4 is further performed for a part of the impurity region 6 using the second sidewall 7 as an ion implantation mask and a second impurity region 8 of high impurity concentration is formed (Step 104).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to improvement of a semiconductor device and a method of manufacturing the same as a semiconductor device is miniaturized.

[0002]

Conventionally, various semiconductor devices have been proposed, in particular, MOS (M etal O xide S em
The one with a built-in transistor is often used. In such a semiconductor device, the element structure is being miniaturized in order to improve the degree of integration.

When the MOS transistor of such a semiconductor device is miniaturized, the length of the gate electrode, that is, the gate length becomes shorter. Along with this, when the drain voltage is increased, a short channel effect such as a punch-through current in which the drain depletion layer extends to near the potential barrier in the vicinity of the source region is generated.

Therefore, as a means for ensuring an effective channel length, it is necessary to suppress the impurities in the source region and the drain region from laterally spreading along the semiconductor substrate surface. In this case, it is possible to shorten the annealing treatment time after the impurity implantation.

[0005]

However, as a result, diffusion of impurities in the depth direction with respect to the semiconductor substrate surface is suppressed, and shallow source regions and drain regions are formed. On the other hand, it has been necessary to increase the impurity concentration in the well region (semiconductor substrate) in order to realize an element with low power consumption and low off current due to miniaturization.

Therefore, the junction capacitance between the source and drain regions and the well region increases, and the impurity profile of the junction between the source and drain regions and the well region becomes steep (see FIG. 5). As a result, the switching speed of the device is delayed and the operation speed of the product is slowed down.

Therefore, in order to suppress the short channel effect, not only the lateral extension of the source region and the drain region is suppressed, but also the impurity of the same conductivity type as that of the well region is implanted deep under the channel region. It is also possible.

However, also in this case, the amount of junction between the source region and the drain region and the well region increases, and the same problem as described above occurs.

The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a semiconductor device in which parasitic capacitance is reduced in a junction between a source region and a drain region and a well region, and a method for manufacturing the same. To provide.

[0010]

In order to achieve the above object, a semiconductor device according to the present invention has an element region formed on a semiconductor substrate, in which a source region, a drain region, and the source region are formed. And a channel region located between the drain region, and a semiconductor device having a field effect transistor having a gate electrode that exerts an electric field on the channel region through an insulator film, wherein the source region and the drain region are: The impurity concentration gradually increases as the distance from the vicinity of the channel region increases in the horizontal direction with respect to the substrate surface of the semiconductor substrate.

Further, in the method of manufacturing a semiconductor device according to the present invention, there is provided a first insulating film step of forming a first insulating film on a semiconductor substrate, and at least a part of the first insulating film is formed into a gate insulating film. A gate electrode forming step of forming a gate electrode thereabove, and a first sidewall forming step of forming a first sidewall made of a second insulating film so as to cover both side walls of the gate electrode, A first impurity introduction step of forming an impurity implantation region as an element operating region;
Second impurity forming step of forming a second sidewall made of a third insulating film so as to cover both outer side walls of the first sidewall after the impurity introducing step of A second impurity implantation step of implanting impurities deeper than the first impurity introduction step.

Further, in the method of manufacturing a semiconductor device according to the present invention, a first insulating film step of forming a first insulating film on a semiconductor substrate, and at least a part of the first insulating film is a gate insulating film. A gate electrode forming step of forming a gate electrode thereabove, and a first sidewall forming step of forming a first sidewall made of a second insulating film so as to cover both side walls of the gate electrode, A first impurity introduction step of forming an impurity implantation region as an element operating region;
After the impurity introduction step, the resist patterning step of patterning a resist so as to cover both the upper end portion of the gate electrode and both outer side walls of the first sidewall, and the impurity injection region further than the first impurity introduction step. A second impurity implantation step of deeply implanting impurities.

[0013]

In the semiconductor device according to the present invention having the above-described structure, the impurity concentration gradually decreases as the source region and the drain region are moved away from the vicinity of the channel region in the horizontal direction with respect to the substrate surface of the semiconductor substrate. Since it increases, the impurity profile of the junction between the source region and the drain region and the well region becomes gentle. Therefore, the junction capacitance between the source region and the drain region and the well region is reduced.

In the method of manufacturing a semiconductor device according to the present invention, after the first impurity introduction step, the second sidewall made of the third insulating film is formed so as to further cover both outer sidewalls of the first sidewall. Is formed, and the impurities are further implanted into the impurity-implanted regions formed earlier than in the first impurity introduction step. Therefore, the depth and the concentration of the impurities are ensured and the lateral regions of the source region and the drain region are secured. The spread of impurities in the direction can be suppressed. In addition, the impurity implantation is divided into two steps, and the sidewall is formed to form the second
Since the impurity implantation is performed as described above, the impurity concentration in the vicinity of the channel region can be made lower than the impurity concentration in the portion distant therefrom. Therefore, the impurity profile of the junction between the source region and the drain region and the well region can be made gentle, and the impurity concentration of the entire device can be increased.

Further, in the method of manufacturing a semiconductor device according to the present invention, after the first impurity introduction step, the resist is patterned so as to cover the upper end portion of the gate electrode and both outer side walls of the first side wall, and thereafter. Since the impurities are further implanted into the impurity-implanted region formed in the first step than in the first impurity-introducing step, the impurity diffusion in the lateral direction of the source region and the drain region is ensured while ensuring the depth and concentration of the impurity. Can be suppressed. In addition, since the impurity implantation is divided into two steps and the second impurity implantation is performed after the resist is patterned, the impurity concentration in the vicinity of the channel region can be made lower than the impurity concentration in the portion distant therefrom. Therefore, the impurity profile of the junction between the source region and the drain region and the well region can be made gentle, and the impurity concentration of the entire device can be increased.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described with reference to the following drawings.

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. In the structure of the semiconductor device of the present invention, the surface of the semiconductor substrate (or well region) 4 is covered with an insulating film 5 formed of SiO ₂ or the like. The gate electrode 3 is formed on the insulating film 5, and the insulating film immediately below the gate electrode 3 functions as the gate oxide film 1.

Immediately below the insulating film 5, first impurity regions 6a and 6b and second impurity regions 8a and 8b in which impurities of a conductivity type different from those of the semiconductor substrate 4 are implanted are formed. . Then, the second impurity regions 8a and 8b
Has a higher impurity concentration than the first impurity regions 6a and 6b, and is formed deeper in the depth direction with respect to the semiconductor substrate 4. Then, the first impurity region 6a and the second impurity region 6a
The impurity region 8a, and the first impurity region 6b and the second impurity region 8b respectively operate as a source region or a drain region.

On the other hand, in the region sandwiched between the source region and the drain region, a channel region of the same conductivity type as that of the semiconductor substrate 4 is formed.

Therefore, as shown in FIG. 1, the first impurity regions 6a and 6b in the vicinity of the channel region have a small impurity concentration and thus the depletion layer spreads little in this portion. Therefore, even if the element is miniaturized and the gate length is shortened as compared with the conventional one, the channel threshold voltage of the gate voltage hardly changes. Thereby, the short channel effect can be suppressed.

On the other hand, outside the first impurity regions 6a and 6b, the second impurity regions 8a and 8b having a higher impurity concentration and deeper impurity diffusion than the first impurity regions 6a and 6b are formed. The impurity concentration of the impurity region as the semiconductor device increases. Therefore, the element can be miniaturized.

Next, a method for manufacturing the above-mentioned semiconductor device will be described with reference to the drawings with reference to two embodiments. Figure 2
It is a figure explaining the 1st manufacturing process of a semiconductor device. FIG. 3 is a diagram for explaining the second manufacturing process of the semiconductor device. FIG. 4 shows the source / drain region and the well region 4.
It is a figure which shows the impurity profile of the depth direction of and.

First, the first embodiment will be described with reference to FIG. First, the insulating film 5 made of a SiO ₂ film is formed on the surface of the semiconductor substrate 4, and the gate electrode 3 is formed on the insulating film 5. As a result, the insulating film immediately below the gate electrode 5 functions as the gate oxide film 1. Then, the first sidewall 2 is formed on the side surface of the gate electrode 3. The first sidewall 2 is formed by, for example, low pressure CVD.
After depositing the oxide layer, it is formed by anisotropic etching (step 101). Reduced pressure CV used in this example
As the D oxide film, for example, LT formed at a growth temperature of 400 to 500 ° C. under a pressure of several hundred mTorr or less.
O (L ow T emperature O xide ),
Or HTO growth temperature under reduced pressure of the same is formed at 700~800 ℃ (H igh T emperature
O xide) is listed. The well region 4 is preliminarily implanted with a high concentration of impurities. For example, P
When forming a MOS transistor, the well region is
In this embodiment, phosphorus ions (P ⁺ ) of phosphorus, which is an n ⁺ type impurity, are ion-implanted at 125 keV and 2 × 10 ¹³ cm ⁻² .

Next, using the first sidewall 2 as an ion implantation mask, ion implantation of impurities of the opposite conductivity type to the semiconductor substrate 4 is performed. The ion implantation amount at this time is set to be small, and the first impurity region 6 having a low impurity concentration is formed (step 102). For example, when forming a PMOS transistor, the implanted ions are BF ₂ ⁺ which is a p ⁺ -type impurity ion, 40 keV, 2 × 10 ^15.
Ion implantation is performed at cm ^-2 .

After that, the second sidewall 7 is formed on the side surface of the first sidewall 2. The second side wall 7 is formed by anisotropic etching by depositing an oxide film layer by low pressure CVD as described above (step 103).

Further, using the second sidewall 7 as an ion implantation mask, ion implantation of an impurity having a conductivity type opposite to that of the semiconductor substrate 4 is performed on a part of the first impurity region 6. The ion implantation amount at this time is the same as or lower than the previous ion implantation amount, and the second impurity region 8 having a high impurity concentration is formed (step 104). For example,
When forming a PMOS transistor, the ions to be implanted are boron ions (B ⁺ ) which are p ⁺ type impurities, and in the case of this embodiment, the ions are implanted at 30 keV and 2 × 10 ¹⁵ cm ^-2 .

As described above, the ion implantation for forming the source and drain regions is performed twice after the formation of the first side wall 2 and the second side wall 7, so that the gate electrodes of the source and drain regions are formed. It is possible to obtain an LDD structure in which the impurity concentration on the 3 side (channel region side) is reduced.

After that, heat treatment is performed at 900 ° C. for 30 minutes, for example.

Next, a second embodiment will be described with reference to FIG. Since step 201 and step 202 of this embodiment are the same as step 101 and step 102 of the above-described first embodiment, the description thereof will be omitted.

In the case of the present embodiment, after forming the first impurity region 6, the resist 9 is patterned so as to cover the upper surface of the gate electrode 3 and the side surface of the first sidewall 2 (step 203).

Then, using the resist 9 as an ion implantation mask, ions of an impurity having a conductivity type opposite to that of the semiconductor substrate 4 are ion-implanted into a part of the first impurity region 6. The ion implantation amount at this time is the same as or lower than the previous ion implantation amount, and the second impurity region 8 having a high impurity concentration is formed (step 204). For example, PMO
When forming an S-transistor, the implanted ions are
It is a boron ion (B ⁺ ) which is a p ⁺ type impurity, and is ion-implanted at 30 keV and 2 × 10 ¹⁵ cm ⁻² in this embodiment.

Then, heat treatment is performed at 900 ° C. for 30 minutes, and the resist 9 is removed by dry etching or the like.

According to the manufacturing methods of the above-described two embodiments, the impurities in the second impurity region 8 diffuse in the depth direction with almost no lateral spread. Therefore, as shown in FIG. 5, in the formation of the PMOS transistor, the source / drain regions are formed by performing the heat treatment only once in the ion implantation (BF ₂ ⁺ is ion implantation at 40 keV and 2 × 10 ¹⁵ cm ⁻² ). While the impurity profile of the junction with the well region 4 (in the depth direction) is steep, in the case of the present embodiment, the impurity profile of the junction (in the depth direction) is gentle as shown in FIG. . This significantly reduces the junction capacitance.

Further, in the case of this embodiment, the depth of the impurity diffusion layer can be controlled only by changing the ion implantation amount and the heat treatment condition of the second time regardless of the lateral expansion. Therefore, since the depth of the diffusion layer can be sufficiently secured, it is possible to reduce the leakage current and the like due to the abrasion of the diffusion layer at the time of forming the contact hole, and to secure the yield of the element sufficiently.

In this embodiment, the PMOS transistor has been described as an example, but it goes without saying that the same applies to the NMOS transistor.

[0036]

As described above, in the semiconductor device according to the present invention, the impurity profile of the junction between the source region and the drain region and the well region becomes gentle. Therefore, the junction capacitance between the source and drain regions and the well region can be reduced.

Further, the semiconductor device manufacturing method according to the present invention can suppress the lateral spread of impurities in the source region and the drain region while ensuring the depth and concentration of the impurities. In addition, since the impurity implantation is performed twice and the second impurity implantation is performed after the sidewall formation or resist patterning, the impurity concentration in the vicinity of the channel region can be made lower than the impurity concentration in a portion distant therefrom. it can. Therefore, the impurity profile of the junction between the source region and the drain region and the well region can be made gentle, and the impurity concentration of the entire device can be increased.

Further, since the above manufacturing method is carried out by self-alignment, the lateral diffusion of impurities in the source region and the drain region can be efficiently suppressed by the second sidewall.

On the other hand, since the resist pattern can arbitrarily overlap the gate region, it is possible to efficiently suppress the lateral diffusion of impurities in the source region and the drain region.

As a result, according to the semiconductor device and the method for manufacturing the same, it is possible to provide an element having excellent transistor characteristics in which the short channel effect, which is a particular problem in the miniaturization of the element, is suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram illustrating a first manufacturing process of a semiconductor device.

FIG. 3 is a diagram illustrating a second manufacturing process of the semiconductor device.

FIG. 4 is a diagram showing an impurity profile of a junction between a source / drain region and a well region of a semiconductor device according to this example.

FIG. 5 is a diagram showing an impurity profile of a junction between a source / drain region and a well region in one-time ion implantation.

[Explanation of symbols]

 1 Gate Electrode 2 First Sidewall 3 Gate Electrode 4 Semiconductor Substrate (Well Region) 5 Insulating Film 6 First Impurity Region 7 Second Sidewall 8 Second Impurity Region 9 Resist

Claims (3)

[Claims] 1. A device region is formed on a semiconductor substrate, a source region and a drain region, and a channel region located between the source region and the drain region are provided therein, and an insulating film is interposed in the channel region. A semiconductor device having a field-effect transistor provided with a gate electrode that exerts an electric field, wherein the source region and the drain region are separated from the channel region in the horizontal direction with respect to the substrate surface of the semiconductor substrate, and the impurity A semiconductor device having a gradual increase in concentration. 2. A first insulating film step of forming a first insulating film on a semiconductor substrate, and a gate in which at least a part of the first insulating film is used as a gate insulating film, and a gate electrode is formed above the gate insulating film. An electrode forming step, a first side wall forming step of forming a first side wall made of a second insulating film so as to cover both side walls of the gate electrode, and an impurity implantation area as an element operating area First impurity introduction step, and second sidewall formation is performed after the first impurity introduction step to further form a second sidewall made of a third insulating film so as to cover both outer sidewalls of the first sidewall. And a second impurity implantation step of further implanting impurities into the impurity implantation region deeper than the first impurity introduction step. 3. A first insulating film step of forming a first insulating film on a semiconductor substrate, and a gate in which at least a part of the first insulating film is a gate insulating film and a gate electrode is formed above the gate insulating film. An electrode forming step, a first side wall forming step of forming a first side wall made of a second insulating film so as to cover both side walls of the gate electrode, and an impurity implantation area as an element operating area 1. An impurity introducing step, a resist patterning step of patterning a resist so as to cover the upper end portion of the gate electrode and both outer side walls of the first sidewall after the first impurity introducing step, and A second impurity implantation step of implanting impurities deeper than the first impurity introduction step, and a method of manufacturing a semiconductor device.