KR20020002918A - Method for fabricating transistor of semiconductor memory device - Google Patents
Method for fabricating transistor of semiconductor memory device Download PDFInfo
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- KR20020002918A KR20020002918A KR1020000037285A KR20000037285A KR20020002918A KR 20020002918 A KR20020002918 A KR 20020002918A KR 1020000037285 A KR1020000037285 A KR 1020000037285A KR 20000037285 A KR20000037285 A KR 20000037285A KR 20020002918 A KR20020002918 A KR 20020002918A
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- ion implantation
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 66
- 125000005843 halogen group Chemical group 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 125000004429 atom Chemical group 0.000 claims description 2
- 229910021478 group 5 element Inorganic materials 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 abstract 3
- 239000007924 injection Substances 0.000 abstract 3
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000002955 isolation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체메모리장치의 트랜지스터 제조방법에 관한 것으로, 특히 STI(Shallow Trench Isolation) 방법을 이용하여 소자분리공정을 실시하는 경우, 트랜치의 측벽에 비스듬히 이온주입하여 추가적인 마스크 공정없이 국부적으로 웰(well) 농도를 높이므로써 트랜지스터의 문턱전압을 조절할 수 있는 반도체메모리장치의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor memory device. In particular, when a device isolation process is performed by using a shallow trench isolation (STI) method, an ion is implanted at an angle to a sidewall of a trench at a local well without additional mask process. The present invention relates to a transistor manufacturing method of a semiconductor memory device capable of adjusting the threshold voltage of a transistor by increasing the concentration thereof.
일반적으로 메모리소자의 고집적화를 위해서는 우수한 특성을 갖는 작은 소자의 개발과 더불어 소자와 소자을 서로 전기적으로 분리시키는 기술이 필요하다. 따라서, 현재 회로선폭이 0.25㎛이하인 미세기술에서는 소자와 소자간의 전기적 분리를 위하여 버저비크(bird's beak)가 거의 없는 STI 공정기술을 개발하여 모스 트랜지스터 제조에 적용하고 있다.In general, in order to achieve high integration of memory devices, there is a need for development of small devices having excellent characteristics and a technique for electrically separating devices from devices. Therefore, in the micro technology having a circuit line width of 0.25 μm or less, an STI process technology having little bird's beak has been developed and applied to manufacturing MOS transistors for electrical separation between devices.
그러나, 소자의 채널 폭(channel width)이 점점 작아짐에 따라, 트랜지스터의 문턱전압이 작아지는 RNWE(Reverse Narrow Width Effect)가 발생하는 문제점이 대두되었다. 이러한, 문제점을 해결하기 위하여 트랜치의 측벽에 이온주입하여 웰의 이온농도를 증가시키는 기술이 사용되고 있e.However, as the channel width of the device becomes smaller, a problem arises in that a reverse narrow width effect (RNWE) occurs in which the threshold voltage of the transistor becomes smaller. In order to solve this problem, a technique of increasing the ion concentration of the well by ion implantation into the sidewall of the trench is used.
도 1 내지 도 4는 STI 공정을 이용한 종래의 반도체메모리장치의 트랜지스터 제조방법을 나타는 단면도로서, 트랜치의 측벽에 이온주입하는 기술에 관한 것이다.1 to 4 are cross-sectional views illustrating a method of fabricating a transistor of a conventional semiconductor memory device using an STI process, and related to a technique of implanting ions into sidewalls of trenches.
도 1을 참조하면, 반도체기판(10) 위에 패드(pad) 산화막(11) 및 질화막(12)을 형성한 후, 상기 질화막(12)을 선택식각하여 소자분리용 패턴을 형성한다. 그 다음, 상기 질화막(12)을 마스크로 하여 상기 반도체기판(10)의 노출된 부분을 식각하여 얕은 깊이의 트랜치(13)를 형성한다.Referring to FIG. 1, after forming a pad oxide film 11 and a nitride film 12 on a semiconductor substrate 10, the nitride film 12 is selectively etched to form a device isolation pattern. Next, the exposed portion of the semiconductor substrate 10 is etched using the nitride film 12 as a mask to form a trench 13 having a shallow depth.
그 다음, 도 2에 도시된 바와 같이, NMOS 트랜지스터와 PMOS 트랜지스터를 구별하는 마스크 공정으로서, 상기 트랜치(13)가 형성된 결과물에 포토레지스터막(14)을 패터닝한다. 이어서, 상기 트랜치(13)내에 비스듬한 방향으로 경사(tilt)를 주어 이온주입을 실시한다.Next, as shown in FIG. 2, as a mask process for distinguishing the NMOS transistor and the PMOS transistor, the photoresist film 14 is patterned on a resultant in which the trench 13 is formed. Subsequently, ion implantation is performed by tilting the trench 13 in an oblique direction.
이에 따라, 도 3에 도시된 바와 같이, 트랜치의 측벽(13a) 일부에만 이온주입이 이루어진다.Accordingly, as illustrated in FIG. 3, ion implantation is performed only on a portion of the sidewall 13a of the trench.
그 다음, 상기 포토레지스터막(14)를 제거하고, 상기 트랜치 내부에 산화막(15)을 증착함과 아울러 트랜치 코너를 둥글게 하기 위한 산화공정을 실시하고, 이어서 상기 산화막(11) 및 질화막(12)을 에치백(etchback)한다.Next, the photoresist film 14 is removed, an oxide film 15 is deposited inside the trench, and an oxidation process is performed to round the trench corners, followed by the oxide film 11 and the nitride film 12. Etch back
그 다음, 도 4에 도시된 바와 같이, 상기 반도체기판(10) 위에 이온주입에 의한 웰을 형성한 후, 게이트산화막(16)을 증착하고 상기 게이트산화막(16) 위에 폴리실리콘막(17)을 증착하여 게이트전극을 형성한다. 이어서, LDD 이온주입층(18)과 Halo 이온주입층(19)을 형성한다.Next, as shown in FIG. 4, after forming a well by ion implantation on the semiconductor substrate 10, a gate oxide layer 16 is deposited and a polysilicon layer 17 is deposited on the gate oxide layer 16. Deposition forms a gate electrode. Next, the LDD ion implantation layer 18 and the Halo ion implantation layer 19 are formed.
그 다음, 상기와 같은 결과물 전면에 산화막 및 절연막을 적층한 후 등방성의 건식식각을 진행하여 상기 게이트전극의 측면에 버퍼 산화막(17a) 및 스페이서(spacer)(17b)를 형성한다.Next, an oxide film and an insulating film are stacked on the entire surface of the resultant material, and isotropic dry etching is performed to form a buffer oxide film 17a and a spacer 17b on the side of the gate electrode.
그 다음, 소오스/드레인 영역에 이온주입을 실시한 후 RTP(Rapid ThermalProcess) 어닐링을 실시하여 소오스/드레인 접합층(17c)을 형성한다.Next, ion implantation is performed in the source / drain region, followed by RTP (Rapid Thermal Process) annealing to form the source / drain junction layer 17c.
그러나, 상기와 같은 종래의 방법으로 공정을 진행할 경우, 트랜치의 측벽에 비스듬한 방향으로 이온주입하기 위해서는 추가적인 포토레지스터 마스크 공정이 필요하기 때문에, 제품원가의 상승 및 수율의 저하가 초래될 수 있었다. 또한, 종래의 방법에 있어서, 트랜치내에 산화막을 증착하기 전에 실시하는 트랜치 고너에 대한 라운딩(rounding) 공정에 의하여 활성영역이 감소될 수 있는 단점이 있었다.However, when the process is performed by the conventional method as described above, an additional photoresist mask process is required for ion implantation in an oblique direction to the sidewalls of the trench, resulting in an increase in product cost and a decrease in yield. In addition, in the conventional method, there is a disadvantage that the active area may be reduced by a rounding process for the trench goner which is performed before depositing an oxide film in the trench.
따라서, 상기와 같은 종래의 문제점을 해결하기 위하여, 본 발명은 트랜치의 측벽에 비스듬히 이온주입하여 추가적인 마스크 공정없이 국부적으로 웰 농도를 높이므로써 트랜지스터의 문턱전압을 조절할 수 있는 반도체메모리장치의 트랜지스터 제조방법을 제공하는 것을 목적으로 한다.Accordingly, in order to solve the above-mentioned problems, the present invention provides a method of fabricating a transistor of a semiconductor memory device which can adjust the threshold voltage of a transistor by locally implanting the ion at an angle to the sidewall of the trench and locally increasing the well concentration without an additional mask process. The purpose is to provide.
도 1 내지 도 4는 종래의 반도체메모리장치의 트랜지스터 제조방법을 나타낸 단면도이다.1 to 4 are cross-sectional views illustrating a transistor manufacturing method of a conventional semiconductor memory device.
도 5 내지 도 9는 본 발명에 따른 반도체메모리장치의 트랜지스터 제조방법을 나타낸 단면도이다.5 through 9 are cross-sectional views illustrating a method of manufacturing a transistor in a semiconductor memory device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10,20: 반도체기판 11,21: 패드산화막10,20: semiconductor substrate 11,21: pad oxide film
12,22: 질화막 15,23: 산화막12,22 nitride film 15,23 oxide film
16,24: 게이트산화막 17,25: 폴리실리콘막16, 24: gate oxide film 17, 25: polysilicon film
18,26: LDD 이온주입층 19,27: Halo 이온주입층18, 26: LDD ion implantation layer 19, 27: Halo ion implantation layer
28: 이온주입영역 17a,29: 버퍼산화막28: ion implantation region 17a, 29: buffer oxide film
17b,30: 스페이서 17c,31: 소오스/드레인접합층17b, 30: spacer 17c, 31: source / drain bonding layer
이와 같은 목적을 달성하기 위한 본 발명은 반도체기판 위에 소정부분을 식각하여 복수개의 얕은 깊이의 트랜치를 형성하는 단계; 상기 트랜치 내부에 산화막을 각각 증착하는 단계; 상기 트랜치들 사이의 반도체기판의 활성영역에 이온주입하여 웰을 형성하는 단계; 상기 웰 영역에 게이트산화막 및 폴리실리콘막을 증착한 후 패터닝하여 게이트전극을 형성하는 단계; 상기 웰 영역에 이온주입을 수행하여 LDD 이온주입층 및 Halo 이온주입층을 형성하는 단계; 상기 게이트전극의 옆면 방향으로 틸트 및 트위스트를 주어 상기 산화막을 통하여 이온주입을 실시하여, 상기 산화막이 증착된 트랜치의 측벽에는 이온주입 영역을 형성하는 단계; 상기 게이트전극의 양옆에 버퍼 산화막 및 스페이서를 형성하는 단계; 및 소오스/드레인 영역에 이온주입을 실시한 후, RTP 어닐링을 실시하여 소오스/드레인 접합층을 형성하는 단계로 구성되는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming a plurality of shallow depth trenches by etching a predetermined portion on the semiconductor substrate; Depositing an oxide film in each of the trenches; Implanting ions into an active region of the semiconductor substrate between the trenches to form a well; Depositing and patterning a gate oxide film and a polysilicon film in the well region to form a gate electrode; Performing ion implantation into the well region to form an LDD ion implantation layer and a Halo ion implantation layer; Performing ion implantation through the oxide layer by tilting and twisting the gate electrode in a lateral direction of the gate electrode to form an ion implantation region on the sidewall of the trench on which the oxide layer is deposited; Forming a buffer oxide layer and a spacer on both sides of the gate electrode; And ion implantation into the source / drain region, followed by RTP annealing to form a source / drain junction layer.
이하, 본 발명의 실시예를 첨부 도면을 참조하여 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
도 5 내지 도 9는 본 발명에 따른 반도체메모리장치의 트랜지스터 제조방법을 나타낸 단면도이다.5 through 9 are cross-sectional views illustrating a method of manufacturing a transistor in a semiconductor memory device according to the present invention.
도 5를 참조하면, 반도체기판(20) 위에 패드 산화막(21) 및 질화막(22)을 형성한 후, 상기 질화막(22)을 선택식각하여 소자분리용 패턴을 형성한다. 그 다음, 상기 질화막(22)을 마스크로 하여 상기 반도체기판(20)의 노출된 부분을 식각하여 얕은 깊이의 트랜치를 형성한다. 그 다음, 트랜치의 끝을 라운딩시키기 위하여 산화공정을 실시하고, 이어서 상기 트랜치내에 산화막(23)을 증착한다.Referring to FIG. 5, after the pad oxide film 21 and the nitride film 22 are formed on the semiconductor substrate 20, the nitride film 22 is selectively etched to form a device isolation pattern. Next, the exposed portion of the semiconductor substrate 20 is etched using the nitride film 22 as a mask to form a trench having a shallow depth. Then, an oxidation process is performed to round the end of the trench, and then an oxide film 23 is deposited in the trench.
그 다음, 도 6에 도시된 바와 같이, 상기 산화막(21) 및 질화막(22)을 에치백하고, 상기 반도체기판(20)에 이온주입하여 웰을 형성하므로써 소자가 형성될 영역을 확보한다. 그 다음, 상기 웰 영역에 게이트산화막(24) 및 폴리실리콘막(25)을 적정 두께로 성장 및 증착한 후 패터닝하여 게이트전극을 형성한다.Next, as shown in FIG. 6, the oxide film 21 and the nitride film 22 are etched back, and ion implanted into the semiconductor substrate 20 to form a well, thereby securing a region where a device is to be formed. Thereafter, the gate oxide film 24 and the polysilicon film 25 are grown and deposited to an appropriate thickness in the well region and then patterned to form a gate electrode.
그 다음, 도 7에 도시된 바와 같이, 상기 웰 영역에 이온주입을 수행하여 LDD 이온주입층(26)과 Halo 이온주입층(27)을 형성한다. 이 LDD 이온주입층(26)과 Halo 이온주입층(27)은 소오스와 드레인 사이에 흐르는 캐리어들의 필드를 조절함과 아울러 소오스와 드레인 사이의 펀치스루(punch through)현상을 방지하는 역할을 한다.Next, as shown in FIG. 7, ion implantation is performed in the well region to form the LDD ion implantation layer 26 and the Halo ion implantation layer 27. The LDD ion implantation layer 26 and the Halo ion implantation layer 27 serve to control the field of carriers flowing between the source and the drain, and to prevent punch through between the source and the drain.
그 다음, 도 8에 도시된 바와 같이, 상기 LDD 이온주입층(26)과 Halo 이온주입층(27)의 형성시 적용한 동일한 마스크를 이용하여, 상기 게이트전극의 옆면 방향으로 비스듬하게 틸트(tilt) 및 트위스트(twist)를 주어 상기 산화막(23)을 통하여 이온주입을 실시한다. 따라서, 상기 산화막(23)이 증착된 트랜치의 측벽에는 이온주입 영역(28)이 형성되고, 상기 웰 농도가 국부적으로 증가되어 채널 폭의 감소로 인한 트랜스터 문턱전압의 감소를 방지할 수 있게 된다.Next, as shown in FIG. 8, the tilt is obliquely tilted in the lateral direction of the gate electrode by using the same mask applied when the LDD ion implantation layer 26 and the Halo ion implantation layer 27 are formed. And giving a twist to perform ion implantation through the oxide film 23. Accordingly, an ion implantation region 28 is formed on the sidewall of the trench in which the oxide layer 23 is deposited, and the well concentration is locally increased to prevent a decrease in the transmitter threshold voltage due to a decrease in the channel width. .
이때, 이온주입 영역(28)을 형성하기 위한 이온주입 원(source)으로는 NMOS트랜지스터의 경우 B, BF2, In 등의 3족 원소를 이용하고, PMOS 트랜지스터의 경우에는 P, As, Sb 등의 5족 원소를 이용한다. 그리고, 이온주입시 이온주입 에너지조건은 1~150KeV 범위로 하고, 이온주입 도스(dose)조건은 1 ×1011~ 5 ×1013~atoms/cm3의 범위로 하며, 이온주입 틸트 조건은 0°~ 60°의 범위로 하고, 이온주입 트위스트 조건은 0°~ 360°의 범위로 하며, 이온주입 로테이션(rotation) 조건을 2회 또는 4회로 한다.In this case, as an ion implantation source for forming the ion implantation region 28, a group III element such as B, BF2, In, etc. is used for an NMOS transistor, and P, As, Sb, etc., for a PMOS transistor. Use Group 5 elements. In the ion implantation, the ion implantation energy condition is in the range of 1 to 150 KeV, the ion implantation dose condition is in the range of 1 × 10 11 to 5 × 10 13 to atoms / cm 3 , and the ion implantation tilt condition is 0. The ion implantation twist condition is in the range of 0 ° to 360 °, and the ion implantation rotation condition is twice or four times.
그 다음, 도 9에 도시된 바와 같이, 상기와 같은 결과물 전면에 산화막 및 절연막을 적층한 후 등방성의 건식식각을 진행하여, 상기 게이트산화막(24) 및 폴리실리콘막(25)의 양옆에 버퍼 산화막(29) 및 스페이서(30)를 형성한다. 그 다음, 소오스/드레인 영역에 이온주입을 실시한 후 RTP 어닐링을 실시하여 소오스/드레인접합층(31)을 형성한다.Next, as shown in FIG. 9, after the oxide film and the insulating film are stacked on the entire surface of the resultant product, isotropic dry etching is performed, and buffer oxide films are formed on both sides of the gate oxide film 24 and the polysilicon film 25. 29 and the spacer 30 are formed. Next, ion implantation is performed in the source / drain regions, followed by RTP annealing, to form the source / drain junction layer 31.
한편, 상기 산화막(23)의 측벽에 형성되는 이온주입 영역(28)은 추가적인 이온주입 공정없이 전술한 Halo 이온주입 공정을 이용하여 형성될 수도 있다. 또한, 상기 이온주입 영역(28)을 형성하는 공정은 소오스/드레인 접합층(31)을 형성하기 위한 이온주입 공정과 함께 진행될 수도 있다.Meanwhile, the ion implantation region 28 formed on the sidewall of the oxide film 23 may be formed using the aforementioned Halo ion implantation process without an additional ion implantation process. In addition, the process of forming the ion implantation region 28 may be performed along with the ion implantation process for forming the source / drain junction layer 31.
이상에서 살펴 본 바와 같이, 종래에는 소자와 소자간의 전기적인 부리목적 수행되는 STI 공정기술 적용에 따라 발생되는 RNWE 특성을 개선시키기 위하여 얕은 깊이의 트랜치내에 산화막을 증착하기 전에 트랜치 측벽에 이온주입 영역을 형성하기 때문에, 마스크 공정의 추가진행에 따른 제품원가 상승이라는 문제점이 있었다. 이에 비하여, 본 발명은 게이트전극의 형성 후 LDD 이온주입 공정 및 Halo 이온주입 공정과 함께 게이트전극의 측면방향으로 비스듬하게 트랜치내의 산화막을 통하여 이온주입을 수행함으로써, 추가적인 마스크 공정없이 국부적으로 웰 농도를 높일 수 있게 되어 STI 공정기술 적용에 따라 발생되는 RNWE 특성을 개선시킴과 아울러 제조공정의 단순화를 통한 제품원가를 낮출 수 있다.As described above, in order to improve the RNWE characteristics generated by the STI process technology, which is performed electrically and purposely between the devices, the ion implantation region is formed on the trench sidewalls before the oxide film is deposited in the shallow trench. Because of the formation, there was a problem in that the cost of the product increased due to the further progress of the mask process. In contrast, the present invention performs ion implantation through the oxide film in the trench obliquely in the lateral direction of the gate electrode together with the LDD ion implantation process and the Halo ion implantation process after formation of the gate electrode, thereby increasing the well concentration locally without additional mask process. It is possible to improve the RNWE characteristics generated by applying the STI process technology and to lower the product cost by simplifying the manufacturing process.
Claims (6)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040001792A (en) * | 2002-06-28 | 2004-01-07 | 주식회사 하이닉스반도체 | Method for forming of semiconductor device |
| KR100596881B1 (en) * | 2004-09-03 | 2006-07-05 | 주식회사 하이닉스반도체 | Transistor of semiconductor device and method for manufacturing the same |
| KR101022672B1 (en) * | 2003-12-29 | 2011-03-22 | 주식회사 하이닉스반도체 | Semiconductor device with trench type isolation and method for making the same |
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2000
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040001792A (en) * | 2002-06-28 | 2004-01-07 | 주식회사 하이닉스반도체 | Method for forming of semiconductor device |
| KR101022672B1 (en) * | 2003-12-29 | 2011-03-22 | 주식회사 하이닉스반도체 | Semiconductor device with trench type isolation and method for making the same |
| KR100596881B1 (en) * | 2004-09-03 | 2006-07-05 | 주식회사 하이닉스반도체 | Transistor of semiconductor device and method for manufacturing the same |
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