KR100343469B1 - Fabricating method of transistor - Google Patents
Fabricating method of transistor Download PDFInfo
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- KR100343469B1 KR100343469B1 KR1020000043062A KR20000043062A KR100343469B1 KR 100343469 B1 KR100343469 B1 KR 100343469B1 KR 1020000043062 A KR1020000043062 A KR 1020000043062A KR 20000043062 A KR20000043062 A KR 20000043062A KR 100343469 B1 KR100343469 B1 KR 100343469B1
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- gate
- oxide film
- forming
- nitride film
- side wall
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- 238000000034 method Methods 0.000 title abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 10
- 230000000903 blocking effect Effects 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 230000006866 deterioration Effects 0.000 abstract description 3
- 239000002784 hot electron Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 트랜지스터 제조방법에 관한 것으로, 일반적인 엘디디구조의 엔모스 트랜지스터는 저농도영역 및 헤일로영역이 열처리로 인해 게이트 하부로 파고들어 게이트와 중첩됨에 따라 최적의 소자특성을 갖는 짧은 채널길이의 게이트를 형성하는데 한계가 있고, 또한 펀치-쓰루 및 열 전자에 의한 영향으로 트랜지스터의 특성열화가 발생하는 문제점이 있었다. 본 발명에서는 제1질화막측벽을 통해 펀치-쓰루 저지 및 문턱전압 조절을 위한 불순물 이온주입을 해당영역에 선택적으로 실시한 다음 인버티드 게이트를 형성하는 공정과; 상기 제1질화막측벽을 제거한 해당영역에 불순물이온을 선택적으로 깊게 주입하여 헤일로영역을 형성하는 공정과; 하부 게이트산화막이 상대적으로 두껍게 형성되도록 상기 인버티드 게이트의 측면에 폴리실리콘측벽을 형성하는 공정들을 포함하는 트랜지스터 제조방법을 제공하여 짧은 채널길이의 게이트를 용이하게 형성함과 아울러 펀치-쓰루 저지 및 문턱전압 조절을 효과적으로 실시하고, 게이트와 드레인의 중첩 여유도를 높여 특성을 향상시킬 수 있는 효과가 있다.The present invention relates to a transistor manufacturing method, in which the NMOS transistor of the general LED structure has a short channel length gate having an optimal device characteristic as the low concentration region and the halo region penetrate the gate and overlap with the gate. There is a limitation in forming, and there is a problem in that the characteristics deterioration of the transistor occurs due to the influence of punch-through and hot electrons. The present invention provides a method for forming an inverted gate after selectively performing impurity ion implantation for punch-through blocking and threshold voltage control through a first nitride film side wall. Forming a halo region by selectively implanting impurity ions into the corresponding region from which the first nitride film side wall is removed; A method of fabricating a transistor including a process of forming a polysilicon sidewall on a side surface of the inverted gate so that a lower gate oxide layer is formed relatively thick can easily form a gate having a short channel length, as well as punch-through blocking and thresholding. The voltage can be effectively controlled and the characteristics of the gate and drain can be improved by increasing the overlap margin of the gate and the drain.
Description
본 발명은 트랜지스터 제조방법에 관한 것으로, 특히 짧은 채널길이(short channel)의 게이트를 용이하게 형성함과 아울러 펀치-쓰루 저지(punch-through stop) 및 문턱전압 조절(Vt control)을 효과적으로 실시하고, 게이트와 드레인의 중첩(overlap)에 대한 여유도를 높여 특성을 향상시키기에 적당하도록 한 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor, and in particular, to form a gate of short channel easily, and to perform punch-through stop and threshold voltage control effectively. The present invention relates to a transistor manufacturing method suitable for improving characteristics by increasing the margin of overlap between the gate and the drain.
종래의 기술로, 일반적인 엘디디(lightly doped drain : LDD) 구조의 엔모스 트랜지스터 제조방법을 첨부한 도1a 내지 도1e에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.In the prior art, a detailed cross-sectional view shown in FIGS. 1A to 1E to which an NMOS transistor manufacturing method of a general lightly doped drain (LDD) structure is attached will be described in detail.
먼저, 도1a에 도시한 바와같이 반도체기판(1) 상에 펀치쓰루 저지 및 문턱전압 조절을 위한 이온주입을 실시하여 이온주입층(2)을 형성한다.First, as shown in FIG. 1A, ion implantation for punch-through blocking and threshold voltage regulation is performed on the semiconductor substrate 1 to form the ion implantation layer 2.
그리고, 도1b에 도시한 바와같이 상기 반도체기판(1)의 상부에 게이트 산화막(3)을 형성하고, 그 게이트 산화막(3) 상부에 폴리실리콘(4), WSi2(5) 및 캡절연막(6)을 순차적으로 적층한 다음 패터닝하여 게이트를 형성한다.As shown in FIG. 1B, a gate oxide film 3 is formed on the semiconductor substrate 1, and a polysilicon 4, WSi 2 , 5, and a cap insulating film are formed on the gate oxide film 3, respectively. 6) are sequentially stacked and then patterned to form a gate.
그리고, 도1c에 도시한 바와같이 상기 게이트를 마스크로 적용하여 반도체기판(1) 내에 저농도의 불순물이온을 주입함으로써, 저농도영역(7)을 형성하고, 계속해서 경사(tilt) 이온주입을 실시하여 헤일로(halo)영역(8)을 형성한다. 이때, 상기 저농도영역(7) 및 헤일로영역(8)은 소자가 고집적화됨에 따라 채널길이가 감소하여 이로 인해 발생되는 문제들을 완화시키기 위해서 형성한다.As shown in FIG. 1C, by applying the gate as a mask and injecting a low concentration of impurity ions into the semiconductor substrate 1, a low concentration region 7 is formed, followed by tilt ion implantation. A halo region 8 is formed. In this case, the low concentration region 7 and the halo region 8 are formed in order to alleviate the problems caused by the decrease in the channel length as the device is highly integrated.
그리고, 도1d에 도시한 바와같이 상기 결과물의 상부전면에 질화막을 형성한 다음 선택적 식각을 통해 질화막측벽(9)을 형성한다.As shown in FIG. 1D, a nitride film is formed on the upper surface of the resultant, and then the nitride film side wall 9 is formed through selective etching.
그리고, 도1e에 도시한 바와같이 상기 게이트 및 질화막측벽(9)을 마스크로 적용하여 반도체기판(1) 내에 고농도의 불순물이온을 주입함으로써, 고농도의 소스/드레인(10)을 형성한다.As shown in FIG. 1E, a high concentration of source / drain 10 is formed by injecting a high concentration of impurity ions into the semiconductor substrate 1 by applying the gate and the nitride film side wall 9 as a mask.
그러나, 상기한 바와같이 형성되는 일반적인 엘디디구조의 엔모스 트랜지스터는 저농도영역 및 헤일로영역이 열처리로 인해 게이트 하부로 파고들어 게이트와 중첩됨에 따라 최적의 소자특성을 갖는 짧은 채널길이의 게이트를 형성하는데 한계가 있고, 또한 펀치-쓰루 및 열 전자(hot carrier)에 의한 영향으로 트랜지스터의 특성열화가 발생하는 문제점이 있었다.However, the NMOS transistor of the general LED structure formed as described above forms a gate having a short channel length having optimal device characteristics as the low concentration region and the halo region penetrate into the gate due to heat treatment and overlap with the gate. There is a limitation, and there is a problem in that deterioration of transistor characteristics occurs due to the influence of punch-through and hot carriers.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 짧은 채널길이의 게이트를 용이하게 형성함과 아울러 펀치-쓰루 저지 및 문턱전압 조절을 효과적으로 실시하고, 게이트와 드레인의 중첩 여유도를 높여 특성을 향상시킬 수 있는 트랜지스터 제조방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to easily form a gate having a short channel length, and to effectively perform punch-through blocking and threshold voltage adjustment, It is to provide a transistor manufacturing method that can improve the characteristics by increasing the overlap margin of the drain.
도1a 내지 도1e는 일반적인 엘디디 구조의 엔모스 트랜지스터 제조방법을 보인 수순단면도.1A to 1E are cross-sectional views showing a method of manufacturing a NMOS transistor having a general LED structure.
도2a 내지 도2n은 본 발명의 일 실시예를 보인 수순단면도.2a to 2n are cross-sectional views showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
21:반도체기판 22:패드산화막21: semiconductor substrate 22: pad oxide film
23:고온저압산화막 24:질화막23: high temperature low pressure oxide film 24: nitride film
25:질화막측벽 26:펀치-쓰루 저지층25: nitride film side wall 26: punch-through blocking layer
27:문턱전압 조절층 28,33:게이트산화막27: threshold voltage control layer 28, 33: gate oxide film
29:도핑된 폴리실리콘 30:WSix29: doped polysilicon 30: WSix
31:헤일로영역 32:저농도영역31: halo zone 32: low concentration zone
34:폴리실리콘측벽 35:질화막34: polysilicon side wall 35: nitride film
36:소스/드레인36: source / drain
상기한 바와같은 본 발명의 목적을 달성하기 위한 트랜지스터 제조방법은 반도체기판 상부에 패드산화막(pad oxide)과 고온저압산화막(high temperature low density oxide : HLD)을 형성한 다음 사진식각을 통해 고온저압산화막의 일부를 식각하는 공정과; 상기 결과물의 상부전면에 질화막을 형성하고, 상기 고온저압산화막이 식각된 영역의 패드산화막이 노출되며, 고온저압산화막의 식각된 측면에 제1질화막측벽이 잔류하도록 선택적 식각을 실시한 다음 반도체기판 내에 펀치-쓰루 저지 및 문턱전압 조절을 위한 순차적인 불순물 이온주입을 실시하는 공정과; 상기 노출된 패드산화막을 제거한 다음 그 영역에 제1게이트산화막을 형성하는 공정과; 상기 결과물의 상부전면에 도핑된 게이트전극을 형성한 다음 고온저압산화막과 제1질화막측벽 상부가 노출되도록 평탄화하여 게이트를 형성하는 공정과; 상기 노출된 제1질화막측벽을 제거한 다음 고온저압산화막과 게이트를 마스크로 적용하여 헤일로 불순물 이온을 주입하는 공정과; 상기 고온저압산화막을 제거한 다음 게이트를 마스크로 적용하여 저농도의 불순물이온을 주입하는 공정과; 상기 결과물 상에 산화를 실시하여 잔류하는 패드산화막을 제2게이트산화막으로 적용하고, 상부전면에 폴리실리콘을 형성한 다음 선택적으로 식각하여 게이트 측면에 폴리실리콘측벽을 형성하고, 계속해서 상부전면에 질화막을 형성한 다음 선택적으로 식각하여 게이트의 상부 및 폴리실리콘측벽의 측면에 잔류하는 제2질화막측벽을 형성하는 공정과; 상기 제2질화막측벽을 마스크로 적용하여 고농도의 불순물이온을 주입하는 공정을 구비하여 이루어지는 것을 특징으로 한다.Transistor manufacturing method for achieving the object of the present invention as described above to form a pad oxide film (pad oxide) and a high temperature low density oxide (HLD) on the semiconductor substrate and then a high temperature low pressure oxide film through photolithography Etching a portion of the; A nitride film is formed on the upper surface of the resultant, the pad oxide film of the region where the high temperature low pressure oxide film is etched is exposed, and selective etching is performed so that the first nitride film side wall remains on the etched side of the high temperature low pressure oxide film, and then punched in the semiconductor substrate. Performing sequential impurity ion implantation for through blocking and threshold voltage control; Removing the exposed pad oxide film and forming a first gate oxide film in the region; Forming a gate by forming a doped gate electrode on the upper surface of the resultant, and then planarizing the gate to expose the upper portion of the high temperature low pressure oxide film and the first nitride film side wall; Removing the exposed first nitride film sidewalls and applying a high temperature low pressure oxide film and a gate as a mask to implant halo impurity ions; Removing the high temperature low pressure oxide film and then implanting a low concentration of impurity ions by applying a gate as a mask; The pad oxide film remaining by oxidation on the resultant is applied as the second gate oxide film, polysilicon is formed on the upper front surface, and then selectively etched to form a polysilicon sidewall on the side of the gate. Forming a second nitride film side wall remaining on the upper side of the gate and on the sidewalls of the polysilicon side wall by forming an etch and then selectively etching; And applying a high concentration of impurity ions by applying the second nitride film side wall as a mask.
상기한 바와같은 본 발명에 의한 트랜지스터 제조방법을 첨부한 도2a 내지 도2n에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.Referring to the procedure cross-sectional view shown in Figures 2a to 2n attached to the transistor manufacturing method according to the present invention as described above in detail as follows.
먼저, 도2a에 도시한 바와같이 반도체기판(21) 상부에 순차적으로 패드산화막(22)과 고온저압산화막(23)을 형성한다.First, as shown in FIG. 2A, a pad oxide film 22 and a high temperature low pressure oxide film 23 are sequentially formed on the semiconductor substrate 21.
그리고, 도2b에 도시한 바와같이 상기 고온저압산화막(23)의 일부를 사진식각하여 패드산화막(22)이 노출되도록 한다.As shown in FIG. 2B, a part of the high temperature low pressure oxide film 23 is photographed to expose the pad oxide film 22.
그리고, 도2c에 도시한 바와같이 상기 고온저압산화막(23)의 식각된 영역이 채워지도록 상부전면에 질화막(24)을 형성한다.As illustrated in FIG. 2C, a nitride film 24 is formed on the upper surface of the substrate so that the etched region of the high temperature low pressure oxide film 23 is filled.
그리고, 도2d에 도시한 바와같이 상기 고온저압산화막(23)이 식각된 영역의 패드산화막(22)이 노출되며, 고온저압산화막(23)의 식각된 측면에 질화막측벽(25)이 잔류하도록 상기 질화막(24)을 선택적으로 식각한 다음 순차적으로 불순물이온을 주입하여 펀치-쓰루 저지층(26)과 문턱전압 조절층(27)을 형성한다. 이때, 질화막측벽(25)을 최적으로 형성하기 위해서 질화막(24)을 과도식각함에 따라 패드산화막(22)의 노출된 영역은 소정의 두께로 손실이 발생할 수 있다.As illustrated in FIG. 2D, the pad oxide film 22 in the region where the high temperature low pressure oxide film 23 is etched is exposed, and the nitride film side wall 25 remains on the etched side of the high temperature low pressure oxide film 23. After the nitride film 24 is selectively etched, impurity ions are sequentially implanted to form the punch-through blocking layer 26 and the threshold voltage adjusting layer 27. In this case, as the nitride film 24 is excessively etched to optimally form the nitride film side wall 25, the exposed region of the pad oxide film 22 may be lost to a predetermined thickness.
그리고, 도2e에 도시한 바와같이 상기 노출된 패드산화막(22)을 제거한다.Then, the exposed pad oxide film 22 is removed as shown in FIG. 2E.
그리고, 도2f에 도시한 바와같이 상기 패드산화막(22)이 제거된 영역에 얇은 두께의 게이트산화막(28)을 형성한다.As shown in FIG. 2F, a thin gate oxide film 28 is formed in the region where the pad oxide film 22 is removed.
그리고, 도2g에 도시한 바와같이 상기 결과물의 상부전면에 도핑된 폴리실리콘(29)과 WSix(30)를 적층시켜 게이트전극을 형성한다.As shown in FIG. 2G, the doped polysilicon 29 and the WSix 30 are stacked on the upper surface of the resultant to form a gate electrode.
그리고, 도2h에 도시한 바와같이 상기 WSix(30)와 도핑된 폴리실리콘(29)을 화학기계적 연마(chemical mechanical polishing : CMP)를 통해 상기 고온저압산화막(23)과 질화막측벽(25)이 노출되도록 평탄화하여 게이트를 형성한다.As shown in FIG. 2H, the high temperature low pressure oxide film 23 and the nitride film side wall 25 are exposed through chemical mechanical polishing (CMP) of the WSix 30 and the doped polysilicon 29. Planarize to form a gate.
그리고, 도2i에 도시한 바와같이 상기 노출된 질화막측벽(25)을 제거한 다음 고온저압산화막(23)과 게이트를 마스크로 적용하여 불순물이온을 주입함으로써, 헤일로영역(31)을 형성한다.As shown in FIG. 2I, the exposed nitride film side wall 25 is removed, and then the halo region 31 is formed by applying impurity ions by applying the high temperature low pressure oxide film 23 and the gate as a mask.
그리고, 도2j에 도시한 바와같이 상기 고온저압산화막(23)을 제거한 다음 게이트를 마스크로 적용하여 저농도의 불순물이온을 주입함으로써, 저농도영역(32)을 형성한다.As shown in FIG. 2J, the low concentration region 32 is formed by removing the high temperature low pressure oxide film 23 and then implanting a low concentration of impurity ions using a gate as a mask.
그리고, 도2k에 도시한 바와같이 상기 결과물 상에 산화를 실시하여 반도체기판(21) 상부에 잔류하는 패드산화막(22)을 두꺼운 두께의 게이트산화막(33)으로 적용한다.As shown in FIG. 2K, the pad oxide film 22 remaining on the semiconductor substrate 21 by oxidation is applied to the gate oxide film 33 having a thick thickness.
그리고, 도2l에 도시한 바와같이 상기 결과물 상에 폴리실리콘을 형성한 다음 상기 게이트가 노출되도록 선택적으로 식각하여 게이트의 측면에 폴리실리콘측벽(34)을 형성한다. 이때, 폴리실리콘의 식각으로 인해 상기 게이트산화막(33)은 식각되어 얇아지지만, 폴리실리콘측벽(34) 하부에서는 두꺼운 두께를 유지한다.As shown in FIG. 2L, polysilicon is formed on the resultant, and then selectively etched to expose the gate to form a polysilicon sidewall 34 on the side of the gate. At this time, the gate oxide layer 33 is etched and thinned due to the etching of the polysilicon, but maintains a thick thickness under the polysilicon side wall 34.
그리고, 도2m에 도시한 바와같이 상기 결과물 상에 질화막(35)을 형성한 다음 상기 게이트의 상부 및 폴리실리콘측벽(34)의 측면에만 잔류하도록 식각을 실시한다.As shown in FIG. 2M, the nitride film 35 is formed on the resultant and then etched so as to remain only on the upper side of the gate and the side surface of the polysilicon side wall 34.
그리고, 도2n에 도시한 바와같이 상기 잔류하는 질화막(35)을 마스크로 적용하여 고농도의 불순물이온을 주입함으로써, 소스/드레인(36)을 형성한다.As shown in Fig. 2N, the remaining nitride film 35 is applied as a mask to inject a high concentration of impurity ions to form a source / drain 36.
상기한 바와같은 본 발명에 의한 트랜지스터 제조방법은 다음과 같은 효과를 갖는다.The transistor manufacturing method according to the present invention as described above has the following effects.
먼저, 제1질화막측벽을 통해 펀치-쓰루 저지 및 문턱전압 조절을 위한 불순물 이온주입을 해당영역에 선택적으로 실시함에 따라 이후에 형성되는 소스/드레인과의 카운터 도핑(counter doping)을 방지할 수 있고, 또한 인버티드(inverted) 게이트를 형성할 수 있게 되어 짧은 채널길이를 갖는 게이트를 구현할 수 있는 효과가 있다.First, impurity ion implantation for punch-through blocking and threshold voltage control is selectively performed in the corresponding region through the first nitride film side wall, thereby preventing counter doping with a source / drain formed later. In addition, it is possible to form an inverted gate, which has the effect of realizing a gate having a short channel length.
그리고, 상기 제1질화막측벽을 제거한 해당영역에 불순물이온을 선택적으로 깊게 주입하여 헤일로영역을 형성함에 따라 짧은 채널길이에 따른 영향을 효과적으로 완화할 수 있는 효과가 있다.As the halo region is formed by selectively implanting impurity ions deeply into the corresponding region from which the first nitride film side wall is removed, the effect of short channel length can be effectively alleviated.
그리고, 폴리실리콘측벽을 형성하여 게이트와 드레인간의 중첩 자유도를 높임에 따라 수직전계에 의해 저농도영역의 저항값이 감소되어 트랜지스터의 구동능력을 향상시킴과 아울러 수직전계가 상대적으로 감소되어 열전자에 의한 트랜지스터의 특성열화를 최소화할 수 있는 효과가 있으며, 또한 저농도영역의 저항값이 감소됨에 따라 저농도영역을 보다 저농도화 할 수 있고, 아울러 게이트와 드레인의 중첩길이를 증가시키기 위한 추가적인 확산 열처리가 요구되지 않아 짧은 채널길이의 마진을 상대적으로 향상시킬 수 있는 효과가 있다.As the polysilicon side wall is formed to increase the degree of overlap between the gate and the drain, the resistance value in the low concentration region is reduced by the vertical electric field, which improves the driving capability of the transistor, and the vertical electric field is relatively decreased, thereby reducing the transistor by the hot electron It has the effect of minimizing the deterioration of characteristics, and as the resistance value of the low concentration region is reduced, the low concentration region can be reduced more, and additional diffusion heat treatment is not required to increase the overlap length of the gate and drain. There is an effect that can relatively improve the margin of the short channel length.
그리고, 폴리실리콘측벽 하부의 게이트산화막을 상대적으로 두껍게 형성하여 게이트와 드레인간의 중첩 자유도가 높아짐에 따른 커패시턴스 증가를 방지할 수 있는 효과가 있다.In addition, the gate oxide film under the polysilicon side wall is formed relatively thick, thereby preventing an increase in capacitance as the degree of overlap between the gate and the drain increases.
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