KR101038308B1 - Method for manufacturing transistor in semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a transistor of a semiconductor device capable of increasing data retention time. The method includes providing a substrate having a device isolation film defining an active region; Etching a portion of the active region of the substrate to form a groove; Forming a first gate conductive film on the substrate including the groove; Performing impurity ion implantation on the resultant to form source and drain regions on both substrates of the groove; Sequentially forming a second gate conductive film and a hard mask film on the substrate resultant having the source and drain regions formed thereon; And selectively etching the hard mask layer, the second gate conductive layer, and the first gate conductive layer to form a gate over the groove.

Description

Method for manufacturing transistor in semiconductor device

1 is a cross-sectional view for explaining a transistor manufacturing method of a semiconductor device according to the prior art.

2 is a cross-sectional view illustrating a state in which a conventional gate is misaligned with a groove.

3 and 4 are diagrams illustrating a state in which source and drain regions are asymmetrically distributed as a conventional gate is misaligned with a groove.

5A to 5C are cross-sectional views of processes for explaining a method of manufacturing a transistor of a semiconductor device according to the present invention.

6 is a cross-sectional view illustrating a misaligned gate of a transistor according to the present invention.

Explanation of symbols on the main parts of the drawings

30: silicon substrate 31: device isolation film

32: groove 33: gate oxide film

34: conductive film for first gate 35: source and drain regions

34a: conductive film for first gate remaining after etching 36: conductive film for second gate

36a: conductive film for second gate remaining after etching 37: hard mask film                 

37a: hard mask remaining after etching 38: gate

39: spacer

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a transistor of a semiconductor device capable of increasing data retention time.

Recently, as the design rule of the device is reduced to 100 nm or less, the channel length of the corresponding cell transistor is also greatly reduced. As a result, in implementing the Vt target of the cell transistor required by a specific device, the conventional planar transistor structure is facing its limitations. Accordingly, a method of forming the transistor in a so-called recess channel structure has been proposed.

In the transistor having the recess channel structure, the channel length is secured by selectively etching and recessing an active region of the substrate corresponding to the region where the gate is to be formed.

1 is a cross-sectional view illustrating a transistor manufacturing method of a semiconductor device according to the prior art. First, an active region and a field region are defined, and the silicon substrate 10 having the device isolation layer 11 in the field region is provided. Next, a groove (recess channel structure) 12 is formed by selectively etching and recessing a portion corresponding to the gate formation region of the substrate 10. Then, a gate oxide film (not shown), a first gate conductive film (not shown), a second gate conductive film (not shown), and a hard mask film (not shown) are formed on the substrate 10 including the grooves 12. ) In turn. The first gate conductive film is made of polycrystalline silicon, and the second gate conductive film is made of tungsten silicide.

 Next, the films are selectively etched to form a gate 17 over the groove 12. In this case, reference numerals 13, 14, 15, and 16 not described with reference to FIG. 1 indicate the gate oxide film, the first gate conductive film, the second gate conductive film, and the hard mask film remaining after etching, respectively. Subsequently, LDD regions (not shown) are formed on the substrates on both sides of the gate 17 through low concentration impurity ion implantation. Thereafter, spacers 18 are formed on both side walls of the gate 17, and source and drain regions 19 are formed on both sides of the gate 17 including the spacer 18 through high concentration impurity ion implantation.

2, 3 and 4 are views for explaining a problem according to the prior art, Figure 2 is a cross-sectional view showing a state in which the conventional gate misaligned with the groove, Figure 3 and Figure 4 and the conventional gate is a groove and FIG. 2 shows a state in which source and drain regions are asymmetrically distributed as misalignment. In the transistor manufacturing method of a semiconductor device according to the prior art, as shown in FIG. 2, when the gate 17 is formed, the gate 17 may be misaligned with the groove 12. In this case, the source and drain regions 19 are formed asymmetrically with respect to the groove 12. That is, the gate 17 is aligned to the right or left side of the groove 12 so that the source and drain regions 19 are asymmetric with respect to the groove 12 as shown in FIGS. 3 and 4, respectively. Since the electric field is changed, the uniformity of the cell transistor characteristics is lowered. Accordingly, there is a problem that the junction leakage current is increased and the data retention time is reduced.

Accordingly, the present invention was created to solve the above problems inherent in the transistor manufacturing method of the semiconductor device according to the prior art, and an object of the present invention is that the source and drain regions are formed asymmetrically with respect to the groove. The present invention provides a method of fabricating a transistor of a semiconductor device that can prevent occurrence of changes in an electric field, improve uniformity of cell transistor characteristics, and increase data retention time.

In order to achieve the above object, according to one aspect of the present invention, there is provided a method of forming a gate of a semiconductor device, the method comprising: providing a substrate having a device isolation film defining an active region; Etching a portion of the active region of the substrate to form a groove; Forming a first gate conductive film on the substrate including the groove; Performing impurity ion implantation on the resultant to form source and drain regions on both substrates of the groove; Sequentially forming a second gate conductive film and a hard mask film on the substrate resultant having the source and drain regions formed thereon; And selectively etching the hard mask layer, the second gate conductive layer, and the first gate conductive layer to form a gate over the groove.

According to another aspect of the invention, the first gate conductive film is made of any one selected from the group consisting of polycrystalline silicon, TiSix, MoSix and CoSix.                     

According to another aspect of the invention, the first gate conductive film is formed to a thickness of 500 to 1,000 GPa.

According to another aspect of the present invention, the impurity ion implantation process is performed using any one selected from the group consisting of P and As as an ion implantation source.

According to another aspect of the present invention, the impurity ion implantation step is performed with an ion implantation energy of 10 to 100 KeV and an ion implantation dose of 1E11 to 2E13 atoms / cm 2.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5A through 5C are cross-sectional views illustrating processes of manufacturing a transistor of a semiconductor device according to the present invention.

As shown in FIG. 5A, a silicon substrate 30 is provided in which an active region and a field region are defined, and the device isolation layer 31 is provided in the field region. Subsequently, a portion of the substrate 30 corresponding to the active region is etched and recessed to form the groove 32. Then, the gate oxide film 33 and the first gate conductive film 34 are sequentially deposited on the substrate 30 including the grooves 32. The first gate conductive film 34 is deposited to a thickness of 500 to 1,000 mW using any one selected from the group consisting of polycrystalline silicon, TiSix, MoSix, and CoSix.

Then, a high concentration of impurity ion implantation is performed on the resultant to form source and drain regions 35 on both substrates of the groove 32. In this case, in the high concentration impurity ion implantation process for forming the source and drain regions 35, any one selected from the group consisting of P and As is used as the ion implantation source, and the ion implantation energy is 10 to 100 KeV, The ion implantation dose is set to 1E11 to 2E13 atoms / cm 2. Since the source and drain regions 35 are formed before the subsequently formed gates, even if the gates are misaligned with the grooves 32, the source and drain regions 35 may be formed asymmetrically with respect to the grooves 32. There is no.

As shown in FIG. 5B, the second gate conductive film 36 and the hard mask film 37 are sequentially formed on the substrate resultant having the source and drain regions formed thereon. The second gate conductive film 36 is made of tungsten silicide.

As shown in FIG. 5C, the hard mask film 37, the second gate conductive film 36, and the first gate conductive film 34 are selectively etched to form a gate 38 on the groove 32. ). In this case, reference numerals 34a, 36a, and 37a, which are not described with reference to FIG. 5C, denote polycrystalline silicon films, tungsten silicide films, and hard mask films remaining after etching, respectively. Subsequently, spacers 39 are formed on both side walls of the gate 38. The spacer 39 has a thickness of about 200 to 500 mm 3.

6 is a cross-sectional view illustrating a misaligned gate of a transistor according to the present invention. As described above, in the present invention, since the source and drain regions 35 are formed before the gate 38 is formed, even when the gate 38 is misaligned with the grooves 32 at the time of the gate 38 formation, the source And there is no fear that the drain region 35 is formed asymmetrically with respect to the groove 32. In the prior art, the source and drain regions are formed after the spacers are formed, but in the present invention, the source and drain regions 35 are formed before the gate 38 and the spacers 39 are formed. Compared to the method, the source and drain regions 35 can be formed with higher ion implantation energy. As a result, since the junction of the source and drain regions 35 can be formed more smoothly than before, the electric field can be reduced. Therefore, the junction leakage current can be reduced, thereby increasing the data holding time.

While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not so limited and it is intended that the invention be limited without departing from the spirit or the scope of the invention as defined by the following claims. It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.

As described above, the present invention can prevent the source and drain regions from being asymmetrically formed with respect to the grooves even if the gates are misaligned with the grooves by forming the source and drain regions before forming the gates. As a result, the occurrence of changes in the electric field can be prevented, so that the uniformity of the cell transistor characteristics can be improved. In addition, when the source and drain regions are formed, ion implantation energy can be increased, so that the junction of the source and drain regions can be formed more smoothly than before. As a result, the electric field can be reduced, so that the junction leakage current can be reduced, thereby increasing the data holding time.

Claims (5)

In the transistor manufacturing method of a semiconductor element, Providing a substrate having an isolation layer defining an active region; Etching a portion of the active region of the substrate to form a groove; Forming a first gate conductive film on the substrate including the groove; Performing impurity ion implantation on the resultant to form source and drain regions on both substrates of the groove; Sequentially forming a second gate conductive film and a hard mask film on the substrate resultant having the source and drain regions formed thereon; And And etching the hard mask film, the second gate conductive film, and the first gate conductive film to form a gate over the groove. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And the first gate conductive film is made of any one selected from the group consisting of polycrystalline silicon, TiSix, MoSix and CoSix. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The first gate conductive film is formed to a thickness of 500 to 1,000 GPa. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The impurity ion implantation process is a transistor manufacturing method of a semiconductor device, characterized in that performed using any one selected from the group consisting of P and As as an ion implantation source. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, The impurity ion implantation process is performed with ion implantation energy of 10 to 100 KeV and ion implantation dose of 1E11 to 2E13 atoms / cm 2.

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