KR101169684B1 - Transister of semiconductor device and method of manufacturing the same - Google Patents

Abstract

The present invention discloses a transistor of a semiconductor device capable of effectively improving a Hot Electron Induced Punchthrough (HEIP) phenomenon of a PMOS transistor and at the same time securing a desired current. A transistor of the disclosed semiconductor device includes a semiconductor substrate; An isolation layer defining an active region in the semiconductor substrate; A gate formed on an active region of the substrate; A first source / drain region formed on a portion of the substrate where the active region on both sides of the gate and the isolation layer are in contact; A second source / drain region formed in portions of the substrate active region on both sides of the remaining gate other than the first source / drain region; Spacers formed on both sidewalls of the gate; An interlayer insulating layer formed on the entire surface of the substrate to cover the gate including the spacer and the first and second source / drain regions; And a contact formed to expose the first and second source / drain regions in the interlayer insulating layer, wherein the first source / drain region extends a channel length of a portion where the active region and the device isolation layer are in contact with each other. The gate is formed on the substrate is formed (Elevated) characterized in that it is formed.

Description

Transistor of semiconductor device and manufacturing method therefor {TRANSISTER OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

1 is a plan view for explaining a transistor of a semiconductor device according to an embodiment of the present invention.

2A to 2E are cross-sectional views for each process for explaining a method of manufacturing a transistor of a semiconductor device according to the line AA ′ of FIG. 1.

* Description of the symbols for the main parts of the drawings *

21 semiconductor substrate 22 device isolation film

23: gate insulating film 24: gate conductive film

25 metal layer 26 hard mask layer

27: gate 28: light oxide film

29: first source / drain region 30: oxide film

31 spacer 32 interlayer insulating film

33: contact

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same, and more particularly, to a transistor of a semiconductor device and a method of manufacturing the same, which can effectively improve the HEIP phenomenon of a PMOS transistor and ensure a desired current.

In forming a transistor of a semiconductor device, hot electrons are injected into a gate insulating layer or a device isolation layer, and the channel is conducted by the injected electrons, thereby shortening the channel length. As a result, a hot electron induced punchthrough (HEIP) phenomenon occurs at a gate edge of the PMOS transistor, a threshold voltage of the transistor decreases, and an off current increases, thereby degrading device characteristics.

Accordingly, a method of increasing the effective channel length at the interface portion by forming a tab in an interface portion where the active region of the gate edge and the device isolation layer is in contact with each other has been proposed. Formation of the tab somewhat improves the HEIP phenomenon occurring at the gate edge of the PMOS transistor.

However, in the case of forming the tab, since the bit line contact formed on the tab of the gate edge portion must be removed, there is a disadvantage in terms of current.

Accordingly, the present invention has been made to solve the above-described conventional problems, and provides a semiconductor device transistor and a method of manufacturing the same, which can effectively improve the HEIP phenomenon of a PMOS transistor and secure a desired current. The purpose is to provide.

The transistor of the semiconductor device of the present invention for achieving the above object is a semiconductor substrate; An isolation layer defining an active region in the semiconductor substrate; A gate formed on an active region of the substrate; A first source / drain region formed on a portion of the substrate where the active region on both sides of the gate and the isolation layer are in contact; A second source / drain region formed in portions of the substrate active region on both sides of the remaining gate other than the first source / drain region; Spacers formed on both sidewalls of the gate; An interlayer insulating layer formed on the entire surface of the substrate to cover the gate including the spacer and the first and second source / drain regions; And a contact formed to expose the first and second source / drain regions in the interlayer insulating layer, wherein the first source / drain region extends a channel length of a portion where the active region and the device isolation layer are in contact with each other. The gate is formed on the substrate is formed (Elevated) characterized in that it is formed.

Here, the light oxide film is disposed between the gate and the spacer.

The contact is characterized in that consisting of tungsten, or tungsten silicide.

In addition, the transistor manufacturing method of the semiconductor device of the present invention for achieving the above object comprises the steps of forming a device isolation film defining an active region in the semiconductor substrate; Forming a gate on an active region of the substrate; Forming a light oxide film on both sidewalls of the gate; Forming a raised first source / drain region on a portion of the substrate where the active region on both sides of the gate and the isolation layer are in contact with each other; Forming a second source / drain region in a portion of the substrate active region on both sides of the remaining gate other than the first source / drain region; Forming spacers on both sidewalls of the gate where the first and second source / drain regions are formed; Forming an interlayer insulating film on the entire surface of the substrate to cover the gate including the spacer and the first and second source / drain regions; And forming a contact in the interlayer insulating layer to expose first and second source / drain regions.

The forming of the light oxide film on both sidewalls of the gate may include forming a light oxide film on the entire surface of the substrate including the gate; Performing light doped drain (LDD) implantation into the substrate on which the light oxide film is formed; And dry etching the light oxide film to remain only at both sidewalls of the gate.

The elevated first source / drain region is formed by using a selective epitaxial growth (SEG) process.

Forming a raised first source / drain region on a portion of the substrate where the active regions on both sides of the gate and the device isolation layer are in contact with each other includes: forming a raised first source drain region on the substrate on both sides of the gate; Etching the first source / drain region so that the first source / drain region remains only on a portion of the substrate where the active region on both sides of the gate and the device isolation layer are in contact with each other.

Forming an oxide film on the light oxide films on both sides of the gate after forming the second source / drain region and before forming spacers on both sides of the gate; .

The contact is formed of tungsten or tungsten silicide.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described. According to the present invention, an elevated source / drain region is formed at an interface portion where an active region of a gate edge and a device isolation layer contact each other in the manufacture of a PMOS transistor.

In this case, since the effective channel length at the interface portion is increased, it is possible to effectively improve the Hot Electron Induced Punchthrough (HEIP) phenomenon of the gate edge portion and to secure a desired current. .

In detail, FIG. 1 is a plan view illustrating a transistor of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an isolation layer 11 defining an active region 12 is provided on a semiconductor substrate, and a gate line 13 is formed in an active region defined by the isolation layer 11.

An elevated first source / drain region 14 is formed at an interface portion where the device isolation layer 11 and the active region 12 on both sides of the gate line 13 contact each other, and on both sides of the remaining gate line 13. The second source / drain region 15 is formed. In addition, a plurality of contacts 16 are disposed on the first and second source / drain regions 14 and 15 at both sides of the gate line 13.

Hereinafter, a transistor manufacturing method of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2A to 2E. 2A to 2E are cross-sectional views for each process corresponding to line AA ′ of FIG. 1.

Referring to FIG. 2A, a device isolation layer 22 defining the active region is formed in a semiconductor substrate 21 having an active region and an isolation region, and then on the resultant substrate 21 on which the device isolation layer 22 is formed. The gate insulating film 23, the gate conductive film 24, the metal based film 25 and the hard mask film 26 are deposited on the substrate.

The gate insulating film 23 is usually formed of an oxide film, and the gate conductive film 24 is usually formed of a polysilicon film. The metal based film 25 is usually formed of a tungsten film or a tungsten silicide film, and the hard mask film 26 is usually formed of a nitride film.

Referring to FIG. 2B, the hard mask layer 26, the metal layer 25, the gate conductive layer 24, and the gate insulating layer 23 are sequentially etched to form the gate 27 on the active region of the substrate 21. Form. Subsequently, a light oxide film 28 is formed on the entire surface of the substrate 21 including the gate 27, and then LDD (Light Doped Drain) ion implantation is performed in the substrate 21 on which the light oxide film 28 is formed. . In this case, the light oxide layer 28 is formed on both side walls of the gate 27 except for the hard mask layer 26 and the surface of the substrate 21.

Referring to FIG. 2C, a dry etching process is performed on a resultant of the substrate 21 such that the light oxide layer 28 remains only on both sidewalls of the gate 27. Subsequently, an elevated first source / drain region 29 is formed on both substrates 21 of the gate 27.

The elevated first source / drain region 29 grows a silicon layer on a portion of the substrate 21 on both sides of the gate 27 through a selective epitaxial growth (SEG) process, and then forms a source / drain layer in the grown silicon layer. It is formed by performing drain ion implantation.

Subsequently, the first source / drain region 29 may be left on the portion of the substrate 21 where the active region on both sides of the gate 27 and the device isolation layer 22 contact each other. Etch it. Next, ion implantation is performed in portions of the substrate active region on both sides of the remaining gate 27 from which the first source / drain region 29 is removed to form a second source / drain region (not shown).

In this case, an elevated first source / drain region 29 is formed on a portion of the substrate 21 where the active region on both sides of the gate 27 and the device isolation layer 22 contact each other, and the first source / drain region 29 is formed. A second source / drain region (not shown) is formed in the active region portion of the substrate 21 on both sides of the remaining gate 27, so that the gate 27 is formed at the portion where the active region and the device isolation layer 22 are in contact with each other. The effective channel length is extended. Therefore, it is possible to effectively improve the Hot Electron Induced Punchthrough (HEIP) phenomenon induced at the edge of the gate 27.

Referring to FIG. 2D, an oxide film 30 is formed on both sidewalls of the hard mask layer 26 of the gate 27, and then on the oxide film 30 and the light oxide layer 28 on both sidewalls of the gate 27. The spacer 31 is formed. Next, an interlayer insulating layer 32 is deposited to completely cover the gate 27 including the spacer 31, the first source / drain region 29, and the second source / drain region.

Referring to FIG. 2E, a contact hole is formed in the interlayer insulating layer 32 to expose the first source / drain region 29 and the second source / drain region. Next, tungsten or tungsten silicide is deposited to fill the contact hole to form a contact 33 exposing the first source / drain region 29 and the second source / drain region.

Here, the present invention forms an elevated first source / drain region on a portion of the substrate where the active region on both sides of the gate and the device isolation layer contact each other, and is formed in the portion of the substrate active region on both sides of the remaining gate other than the first source / drain region. Two source / drain regions are formed. Accordingly, the effective channel length of the gate is extended at the interface between the active region and the device isolation layer, thereby effectively improving the HEIP phenomenon. In addition, by forming an elevated first source / drain region instead of the conventional tab in order to extend the channel length, a contact may be formed on the first source / drain region, thereby providing a desired current. (Current) can be obtained.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention forms the source / drain region of the portion where the active region in which the gate is formed and the portion of the device isolation layer in contact with each other in the form of an elevated form, thereby producing a HEIP phenomenon. It can be improved effectively.

In addition, the present invention can secure a desired current by forming a contact on the raised source / drain region.

Claims (9)

Semiconductor substrates; An isolation layer defining an active region in the semiconductor substrate; A gate formed on an active region of the substrate; A first source / drain region formed on a portion of the substrate where the active region on both sides of the gate and the isolation layer are in contact; A second source / drain region formed in portions of the substrate active region on both sides of the remaining gate other than the first source / drain region; Spacers formed on both sidewalls of the gate; An interlayer insulating layer formed on the entire surface of the substrate to cover the gate including the spacer and the first and second source / drain regions; And A contact formed to expose first and second source / drain regions in the interlayer insulating film; Wherein the first source / drain region is formed in an elevated shape on the substrate on which the gate is formed such that a channel length of a portion where the active region and the device isolation layer contact each other is extended; Transistor of the device. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Claim 3 has been abandoned due to the setting registration fee. The method of claim 1, And the contact is made of tungsten or tungsten silicide. Forming an isolation layer defining an active region in the semiconductor substrate; Forming a gate on an active region of the substrate; Forming a light oxide film on both sidewalls of the gate; Forming a raised first source / drain region on a portion of the substrate where the active region on both sides of the gate and the isolation layer are in contact with each other; Forming a second source / drain region in a portion of the substrate active region on both sides of the remaining gate other than the first source / drain region; Forming spacers on both sidewalls of the gate where the first and second source / drain regions are formed; Forming an interlayer insulating film on the entire surface of the substrate to cover the gate including the spacer and the first and second source / drain regions; And Forming a contact in the interlayer insulating film to expose first and second source / drain regions; Transistor manufacturing method of a semiconductor device comprising a. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein Forming a light oxide film on both side walls of the gate, Forming a light oxide film on an entire surface of the substrate including the gate; Performing light doped drain (LDD) implantation into the substrate on which the light oxide film is formed; And Dry etching such that the light oxide layer remains only on both sidewalls of the gate; Transistor manufacturing method of a semiconductor device comprising a. Claim 6 has been abandoned due to the setting registration fee. The method of claim 4, wherein The elevated first source / drain region is formed using a Selective Epitaxial Growth (SEG) process. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 4, wherein Forming a raised first source / drain region on a portion of the substrate where the active region on both sides of the gate and the device isolation layer are in contact with each other, Forming a raised first source drain region on both of the gate substrates; Transistor manufacturing method of a semiconductor device comprising a. Claim 8 was abandoned when the registration fee was paid. The method of claim 4, wherein After forming the second source / drain region, and before forming a spacer on both side walls of the gate, Forming an oxide film on the light oxide films on both sidewalls of the gate; Transistor manufacturing method of a semiconductor device further comprising. Claim 9 has been abandoned due to the setting registration fee. The method of claim 4, wherein And said contact is formed of tungsten or tungsten silicide.

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