KR20010054168A - Contact of semiconductor device and method for forming the same - Google Patents
Contact of semiconductor device and method for forming the same Download PDFInfo
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- KR20010054168A KR20010054168A KR1019990054839A KR19990054839A KR20010054168A KR 20010054168 A KR20010054168 A KR 20010054168A KR 1019990054839 A KR1019990054839 A KR 1019990054839A KR 19990054839 A KR19990054839 A KR 19990054839A KR 20010054168 A KR20010054168 A KR 20010054168A
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- 239000004065 semiconductor Substances 0.000 title claims description 42
- 238000000034 method Methods 0.000 title claims description 29
- 239000010410 layer Substances 0.000 claims abstract description 74
- 239000011229 interlayer Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 15
- 238000002955 isolation Methods 0.000 abstract description 14
- 239000012535 impurity Substances 0.000 abstract description 10
- 150000002500 ions Chemical class 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자에 대한 것으로, 특히 보더리스 콘택(Borderless contact)을 형성하기 위한 반도체소자의 콘택홀 및 그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a contact hole and a method of forming the semiconductor device for forming a borderless contact.
첨부 도면을 참조하여 종래 반도체소자의 콘택홀 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method for forming a contact hole in a conventional semiconductor device is as follows.
도 1a 내지 도 1d는 종래 반도체소자의 콘택홀 형성방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.
종래 반도체소자의 콘택홀 형성방법은 도 1a에 도시한 바와 같이 격리영역과 활성영역이 정의된 반도체기판(1)의 격리영역에 트렌치 격리막(2)을 형성한다.In the conventional method of forming a contact hole in a semiconductor device, as shown in FIG. 1A, a trench isolation layer 2 is formed in an isolation region of a semiconductor substrate 1 in which isolation regions and active regions are defined.
이후에 반도체기판(1) 전면에 게이트산화막(3)을 형성하고, 활성영역의 일영역의 게이트산화막(3)상에 게이트전극(4)을 형성한다.Thereafter, the gate oxide film 3 is formed on the entire surface of the semiconductor substrate 1, and the gate electrode 4 is formed on the gate oxide film 3 in one region of the active region.
그리고 게이트전극(4)양측의 반도체기판(1)에 저농도 불순물이온을 주입해서 저농도 불순물영역(5)을 형성하고, 게이트전극(4)을 포함한 전면에 산화막이나 질화막을 증착한 후에 에치백 공정으로 게이트전극(4)양측면에 측벽스페이서(6)를 형성한다.Then, low concentration impurity ions are implanted into the semiconductor substrate 1 on both sides of the gate electrode 4 to form the low concentration impurity region 5, and an oxide film or a nitride film is deposited on the entire surface including the gate electrode 4, followed by an etch back process. Sidewall spacers 6 are formed on both sides of the gate electrode 4.
다음에 게이트전극(3)과 측벽스페이서(6) 양측의 반도체기판(1)에 고농도 불순물이온을 주입해서 고농도 소오스/드레인영역(7)을 형성한다.Next, a high concentration source / drain region 7 is formed by implanting high concentration impurity ions into the semiconductor substrate 1 on both sides of the gate electrode 3 and the sidewall spacers 6.
상기와 같은 공정을 통하여 게이트산화막과 게이트전극과 소오스/드레인영역을 구비한 단위 트랜지스터를 완성한다.Through the above process, a unit transistor including a gate oxide film, a gate electrode, and a source / drain region is completed.
이후에 트랜지스터를 포함한 반도체기판(1)전면에 질화막(8)을 증착한다.Thereafter, the nitride film 8 is deposited on the entire surface of the semiconductor substrate 1 including the transistor.
그리고 질화막(8)상에 층간절연막(9)을 증착한 후에 화학적 기계적 연마(Chemical Mechanical Polishing)법으로 층간절연막(9)의 표면을 평탄하게 한다.After the interlayer insulating film 9 is deposited on the nitride film 8, the surface of the interlayer insulating film 9 is flattened by chemical mechanical polishing.
그리고 층간절연막(9)상에 감광막(10)을 도포한 후에, 노광 및 현상공정으로 콘택을 형성할 부분만 제거되도록 감광막(10)을 선택적으로 패터닝한다.Then, after the photosensitive film 10 is applied on the interlayer insulating film 9, the photosensitive film 10 is selectively patterned so that only a portion for forming a contact is removed by an exposure and development process.
이후에 도 1b에 도시한 바와 같이 상기 패터닝된 감광막(10)을 마스크로 질화막(8)이 드러날 때까지 층간절연막(9)을 식각한다.Subsequently, as shown in FIG. 1B, the interlayer insulating layer 9 is etched using the patterned photosensitive layer 10 as a mask until the nitride layer 8 is exposed.
다음에 도 1c에 도시한 바와 같이 패터닝된 감광막(10)을 마스크로 게이트전극(4) 일측의 고농도 소오스/드레인영역(7)이 드러나도록 질화막(8)을 식각해서 고농도 소오스/드레인영역(7)에 콘택홀(11)을 형성한다. 이후에 감광막(10)을 제거한다.Next, as illustrated in FIG. 1C, the nitride film 8 is etched using the patterned photoresist film 10 as a mask so that the high concentration source / drain region 7 on one side of the gate electrode 4 is exposed, thereby increasing the high concentration source / drain region 7. The contact hole 11 is formed. Thereafter, the photosensitive film 10 is removed.
그리고 도 1d에 도시한 바와 같이 콘택홀(11)을 포함한 층간절연막(9)상에 베리어 메탈층(12)과 배선형성을 위한 메탈층을 증착한다.As shown in FIG. 1D, a barrier metal layer 12 and a metal layer for wiring formation are deposited on the interlayer insulating film 9 including the contact hole 11.
그리고 도면에는 나타나 있지 않지만 메탈층상에 감광막을 도포한 후에 일영역의 감광막만 남도록 노광 및 현상공정으로 선택적으로 감광막을 패터닝한다. 이때 감광막이 남는 일영역은 콘택홀 및 그에 인접하여 더 연장된 층간절연막 상측 부분이다. 이후에 패터닝된 감광막을 마스크로 메탈층과 베리어 메탈층(12)을 이방성 식각해서 콘택홀(11)내의 층간절연막(9) 표면 및 그에 인접한 층간절연막(9)상에는 베리어 메탈층(12)과 배선층(13)을 형성한다.Although not shown in the drawing, after the photoresist is applied onto the metal layer, the photoresist is selectively patterned by an exposure and development process so that only one photoresist remains. In this case, one region in which the photoresist film remains is a contact hole and an upper portion of the interlayer insulating film further extended adjacent thereto. Subsequently, the metal layer and the barrier metal layer 12 are anisotropically etched using the patterned photosensitive film as a mask, and the barrier metal layer 12 and the wiring layer are formed on the surface of the interlayer insulating film 9 and the adjacent interlayer insulating film 9 in the contact hole 11. (13) is formed.
상기와 같은 종래 반도체소자의 콘택홀 형성방법은 다음과 같은 문제가 있다.The conventional method for forming a contact hole in a semiconductor device as described above has the following problems.
첫째, 종래의 콘택홀 형성공정을 보더리스 콘택(Borderless contact) 공정에 이용하여 에스램소자에 적용할 경우에, 격리영역상으로 미스 얼라인(Mis-Align)된 콘택홀이 형성되어서 격리막이 손실되어서 이 부분으로 정션 누설전류가 유발될 수 있고, 이에 따라서 에스램 스텐바이(Stand-by) 특성에 열화가 발생된다.First, when the conventional contact hole forming process is applied to an SRAM device using a borderless contact process, a misaligned contact hole is formed on the isolation region, and thus the isolation layer is lost. This can lead to junction leakage currents, thereby degrading the SRAM standby-by characteristics.
둘째, 트랜지스터를 포함한 상부에 질화막을 증착한 후에 콘택홀을 형성할 경우에 트랜지스터 특성 변화 및 누설전류가 유발될 수 있고, 이에 따라서 트랜지스터의 스텐바이(Stand-by) 특성에 열화가 발생된다.Second, in the case where the contact hole is formed after the nitride film is deposited on the upper portion of the transistor including the transistor, a change in transistor characteristics and a leakage current may be induced, thereby degrading a stand-by characteristic of the transistor.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 보더리스 콘택(Borderless contact) 마진을 높여서 안정된 제품을 만들어내기에 알맞은 반도체소자의 콘택홀 및 그 형성방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a contact hole of a semiconductor device suitable for producing a stable product by increasing a borderless contact margin and a method of forming the same.
도 1a 내지 도 1d는 종래 반도체소자의 콘택홀 형성방법을 나타낸 공정단면도1A through 1D are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.
도 2는 본 발명 실시예에 따른 반도체소자의 콘택홀을 나타낸 구조단면도2 is a structural cross-sectional view showing a contact hole of a semiconductor device according to an embodiment of the present invention.
도 3a 내지 도 3f는 본 발명 실시예에 따른 반도체소자의 콘택홀 형성방법을 나타낸 공정단면도3A through 3F are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 :트렌치 격리막31 semiconductor substrate 32 trench isolation film
33 : 게이트산화막 34 : 게이트전극33: gate oxide film 34: gate electrode
35 : 저농도 불순물영역 36 : 측벽스페이서35 low concentration impurity region 36 sidewall spacer
37 : 고농도 소오스/드레인영역 38 : 층간절연막37: high concentration source / drain region 38: interlayer insulating film
39 : 질화막 40 : 감광막39: nitride film 40: photosensitive film
41 : 폴리실리콘층 41a : 폴리 측벽스페이서41 polysilicon layer 41a poly sidewall spacer
42 : 콘택홀 43 : 베리어메탈층42: contact hole 43: barrier metal layer
44 : 배선층44: wiring layer
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 콘택홀은 게이트전극과 소오스/드레인영역으로 구성된 트랜지스터가 구비된 반도체기판에 있어서, 상기 트랜지스터를 포함한 상기 반도체기판에 평탄하게 형성된 층간절연막, 상기 게이트전극 일측의 소오스/드레인영역이 드러나도록 상기 층간절연막 사이에 상,하부가 서로 다른폭을 갖고 단차를 이루도록 형성된 콘택홀과, 상기 단차를 이루는 콘택홀과 그에 인접한 상기 층간절연막의 표면상에 형성된 베리어메탈층, 상기 단차를 이루는 콘택홀을 채우도록 상기 베리어메탈층상에 형성된 배선층을 포함하여 구성됨을 특징으로 한다.The contact hole of the semiconductor device of the present invention for achieving the above object is a semiconductor substrate having a transistor comprising a gate electrode and a source / drain region, an interlayer insulating film formed on the semiconductor substrate including the transistor, the gate A contact hole formed between the interlayer insulating layer so that the source / drain regions on one side of the electrode are exposed, and having a different width between the interlayer insulating layer and a barrier formed on the surface of the stepped contact hole and the interlayer insulating layer adjacent thereto; And a wiring layer formed on the barrier metal layer to fill a metal layer and the contact hole forming the step.
상기와 같은 구성을 갖는 본 발명 반도체소자의 콘택홀 형성방법은 게이트전극과 소오스/드레인영역으로 구성된 트랜지스터가 구비된 반도체기판에 있어서, 상기 트랜지스터를 포함한 반도체기판에 평탄하게 층간절연막을 형성하는 공정,상기 층간절연막상에 베리어절연막을 형성하는 공정, 상기 게이트전극 일측의 상기 소오스/드레인영역 상부의 상기 베리어절연막과 상기 층간절연막을 일정깊이 식각하여 제 1 홀을 형성하는 공정, 상기 제 1 홀이 형성된 층간절연막의 측면에 폴리 측벽스페이서를 형성하는 공정, 상기 폴리 측벽스페이서와 상기 베리어절연막을 마스크로 상기 층간절연막을 식각하여 상기 소오스/드레인영역상에 상기 제 1 홀보다 좁은폭을 갖는 제 2 홀을 형성하는 공정, 상기 베리어절연막을 제거하는 공정, 상기 폴리 측벽스페이서를 제거하여서 최종적으로 단차를 갖는 콘택홀을 형성하는 공정, 상기 단차를 갖는 콘택홀과 그에 인접한 상기 층간절연막 상에 베리어메탈층과 배선층을 형성하는 공정을 포함함을 특징으로 한다.A method of forming a contact hole in a semiconductor device according to the present invention having the above structure includes the steps of: forming an interlayer insulating film on a semiconductor substrate including the transistor in a semiconductor substrate including a transistor including a gate electrode and a source / drain region; Forming a barrier insulating layer on the interlayer insulating layer, etching the barrier insulating layer and the interlayer insulating layer on the source / drain region on one side of the gate electrode to a predetermined depth to form a first hole, and forming the first hole Forming a poly sidewall spacer on a side surface of the interlayer insulating layer; etching the interlayer insulating layer using the poly sidewall spacer and the barrier insulating layer as a mask to form a second hole having a narrower width than the first hole on the source / drain region; Forming, removing the barrier insulating film, the poly sidewalls By removing the document finally a step of forming a contact hole having a step, and on the interlayer insulating film a contact hole having a step adjacent thereto, characterized in that it comprises a step of forming a barrier metal layer and the wiring layer.
첨부 도면을 참조하여 본 발명 반도체소자의 콘택홀 및 그 형성방법에 대하여 설명하면 다음과 같다.A contact hole and a method of forming the semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2는 본 발명 실시예에 따른 반도체소자의 콘택홀을 나타낸 구조단면도이고, 도 3a 내지 도 3f는 본 발명 실시예에 따른 반도체소자의 콘택홀 형성방법을 나타낸 공정단면도이다.2 is a structural cross-sectional view showing a contact hole of a semiconductor device according to an embodiment of the present invention, Figures 3a to 3f is a process cross-sectional view showing a method for forming a contact hole of a semiconductor device according to an embodiment of the present invention.
본 발명 반도체소자의 콘택홀은 도 2에 도시한 바와 같이 격리영역과 활성영역이 정의된 반도체기판(31)의 격리영역에 트렌치 격리막(32)이 형성되어 있고, 활성영역에 게이트산화막(33)이 형성되어 있고, 게이트산화막(33)의 일영역에 게이트전극(34)이 형성되어 있다. 그리고 게이트전극(34) 양측면에 측벽스페이서(36)가 형성되어 있고, 측벽스페이서(36) 하부의 반도체기판(31)표면에 저농도 불순물영역(35)이 형성되어 있으며, 게이트전극(34)과 측벽스페이서(36) 하부를 제외한 측벽스페이서(36) 양측의 반도체기판(31)내에 고농도 소오스/드레인영역(37)이 형성되어 있다.As shown in FIG. 2, the trench isolation layer 32 is formed in the isolation region of the semiconductor substrate 31 in which the isolation region and the active region are defined, and the gate oxide layer 33 is formed in the active region of the semiconductor device. Is formed, and the gate electrode 34 is formed in one region of the gate oxide film 33. Sidewall spacers 36 are formed on both sides of the gate electrode 34, and low concentration impurity regions 35 are formed on the surface of the semiconductor substrate 31 below the sidewall spacers 36. High concentration source / drain regions 37 are formed in the semiconductor substrate 31 on both sides of the sidewall spacers 36 except for the lower portion of the spacers 36.
상기와 같이 게이트전극(34)과 LDD 구조의 소오스/드레인을 구비한 트랜지스터가 있다.As described above, there is a transistor having a gate electrode 34 and a source / drain having an LDD structure.
그리고 트랜지스터를 포함한 반도체기판(31) 전면에 층간절연막(38)이 평탄하게 형성되어 있고, 게이트전극(34) 일측의 고농도 소오스/드레인영역(37)이 드러나도록 층간절연막(38)에 상,하부가 서로 다른 폭을 갖는(단차를 갖는) 콘택홀(11)이 형성되어 있다. 이때 콘택홀(11)은 하부의 폭이 상부의 폭보다 좁다.The interlayer insulating film 38 is formed on the entire surface of the semiconductor substrate 31 including the transistor, and the upper and lower portions of the interlayer insulating film 38 are exposed so that the high concentration source / drain region 37 on one side of the gate electrode 34 is exposed. Are formed with contact holes 11 having different widths (with steps). At this time, the contact hole 11 has a lower width than the upper width.
그리고 상기와 같이 단차를 갖는 콘택홀(11) 및 이에 인접한 층간절연막(38) 표면상에 베리어메탈층(43)이 형성되어 있고, 콘택홀(11)을 채우도록 상기 베리어메탈층(43)상에 배선층(44)이 형성되어 있다.The barrier metal layer 43 is formed on the contact hole 11 having the step difference and the interlayer insulating film 38 adjacent thereto as described above, and the barrier metal layer 43 is formed to fill the contact hole 11. The wiring layer 44 is formed in this.
상기와 같이 구성된 본 발명 반도체소자의 콘택홀 형성방법은 도 3a에 도시한 바와 같이 격리영역과 활성영역이 정의된 반도체기판(31)의 격리영역에 트렌치 격리막(32)을 형성한다.In the method for forming a contact hole of the semiconductor device of the present invention configured as described above, as shown in FIG. 3A, the trench isolation layer 32 is formed in the isolation region of the semiconductor substrate 31 in which the isolation region and the active region are defined.
이후에 반도체기판(31) 전면에 게이트산화막(33)을 형성하고, 활성영역의 일영역의 게이트산화막(33)상에 게이트전극(34)을 형성한다.Thereafter, the gate oxide film 33 is formed on the entire surface of the semiconductor substrate 31, and the gate electrode 34 is formed on the gate oxide film 33 in one region of the active region.
그리고 게이트전극(34)양측의 반도체기판(31)에 저농도 불순물이온을 주입해서 저농도 불순물영역(35)을 형성하고, 게이트전극(34)을 포함한 전면에 산화막이나 질화막을 증착한 후에 에치백 공정으로 게이트전극(34)양측면에 측벽스페이서(36)를 형성한다.Then, the low concentration impurity ions are implanted into the semiconductor substrate 31 on both sides of the gate electrode 34 to form the low concentration impurity region 35, and an oxide film or a nitride film is deposited on the entire surface including the gate electrode 34, followed by an etch back process. Sidewall spacers 36 are formed on both sides of the gate electrode 34.
다음에 게이트전극(34)과 측벽스페이서(36) 양측의 반도체기판(31)에 고농도 불순물이온을 주입해서 고농도 소오스/드레인영역(37)을 형성한다.Next, a high concentration source / drain region 37 is formed by implanting high concentration impurity ions into the semiconductor substrate 31 on both sides of the gate electrode 34 and the sidewall spacers 36.
상기와 같은 공정을 통하여 게이트산화막과 게이트전극과 소오스/드레인영역을 구비한 단위 트랜지스터를 완성한다.Through the above process, a unit transistor including a gate oxide film, a gate electrode, and a source / drain region is completed.
이후에 상기 트랜지스터를 포함한 반도체기판(31) 전면에 층간절연막(38)을 증착한 후에 화학적 기계적 연마(Chemical Mechanical Polishing)법으로 층간절연막(38)의 표면을 평탄하게 한다.Subsequently, after the interlayer insulating film 38 is deposited on the entire surface of the semiconductor substrate 31 including the transistor, the surface of the interlayer insulating film 38 is flattened by chemical mechanical polishing.
다음에 평탄화된 층간절연막(38)상에 질화막(39)을 증착한다.Next, a nitride film 39 is deposited on the planarized interlayer insulating film 38.
그리고 질화막(39)상에 감광막(40)을 도포한 후에, 노광 및 현상공정으로 콘택을 형성할 부분만 제거되도록 감광막(40)을 선택적으로 패터닝한다.After the photoresist film 40 is applied onto the nitride film 39, the photoresist film 40 is selectively patterned so that only a portion for forming a contact is removed by an exposure and development process.
이후에 도 3b에 도시한 바와 같이 상기 패터닝된 감광막(40)을 마스크로 질화막(39)을 식각하고, 이후에 드러난 층간절연막(38)을 일정깊이 식각한다. 이때 층간절연막(38)의 부분식각은 게이트전극(34) 상측에는 도달되지 않도록 식각한다.(즉, 식각되고 남은 층간절연막(38)이 게이트전극(34)의 두께 보다는 두껍게 남도록 한다.)Thereafter, as illustrated in FIG. 3B, the nitride film 39 is etched using the patterned photosensitive film 40 as a mask, and the interlayer insulating film 38 subsequently exposed is etched to a certain depth. At this time, the partial etching of the interlayer insulating film 38 is etched so as not to reach the upper side of the gate electrode 34 (that is, the etched and remaining interlayer insulating film 38 remains thicker than the thickness of the gate electrode 34).
다음에 도 3c에 도시한 바와 같이 감광막(40)을 제거하고, 질화막(39)상부 및 층간절연막(38)상에 도핑이 되지 않은 폴리실리콘층(41)을 증착한다.Next, as shown in FIG. 3C, the photosensitive film 40 is removed and an undoped polysilicon layer 41 is deposited on the nitride film 39 and the interlayer insulating film 38.
그리고 도 3d에 도시한 바와 같이 도핑이 되지 않은 폴리실리콘층(41)을 에치백하여 폴리 측벽스페이서(41a)를 형성한다.As shown in FIG. 3D, the undoped polysilicon layer 41 is etched back to form a poly sidewall spacer 41a.
이후에 도 3e에 도시한 바와 같이 폴리 측벽스페이서(41a)와 질화막(39)을 블로킹막으로 이용해서 층간절연막(38)과 게이트산화막(33)을 순차적으로 식각해서 게이트전극(34) 일측의 고농도 소오스/드레인영역(37)에 콘택홀(42)를 형성한다.Subsequently, as shown in FIG. 3E, the interlayer insulating film 38 and the gate oxide film 33 are sequentially etched using the poly sidewall spacer 41a and the nitride film 39 as a blocking film, thereby high concentration of one side of the gate electrode 34. The contact hole 42 is formed in the source / drain region 37.
다음에 도 3f에 도시한 바와 같이 층간절연막(38)상의 질화막(39)과, 층간절연막(38) 상부 양측벽의 폴리 측벽스페이서(41a)를 제거하여서 층간절연막(38)내에 폭이 다른 계단형의 콘택홀이 형성된다.Next, as shown in FIG. 3F, the nitride film 39 on the interlayer insulating film 38 and the poly sidewall spacers 41a on both side walls of the interlayer insulating film 38 are removed to form a stepped structure having a different width in the interlayer insulating film 38. Contact holes are formed.
이후에 콘택홀(42)을 포함한 층간절연막(38)상에 베리어 메탈층(43)과, 배선형성을 위한 메탈층을 증착한다.Thereafter, a barrier metal layer 43 and a metal layer for wiring formation are deposited on the interlayer insulating film 38 including the contact hole 42.
그리고 도면에는 나타나 있지 않지만 메탈층상에 감광막을 도포한 후에 일영역의 감광막만 남도록 노광 및 현상공정으로 선택적으로 감광막을 패터닝한다. 이때 감광막이 남는 일영역은 콘택홀 및 그에 인접하여 더 연장된 층간절연막 상측 부분이다. 이후에 패터닝된 감광막을 마스크로 메탈층과 베리어 메탈층(43)을 이방성 식각해서 단차를 갖는 콘택홀(42)내의 층간절연막(38) 표면 및 그에 인접한 층간절연막(43)상에는 베리어 메탈층(43)과 배선층(44)을 형성한다.Although not shown in the drawing, after the photoresist is applied onto the metal layer, the photoresist is selectively patterned by an exposure and development process so that only one photoresist remains. In this case, one region in which the photoresist film remains is a contact hole and an upper portion of the interlayer insulating film further extended adjacent thereto. Subsequently, the metal layer and the barrier metal layer 43 are anisotropically etched using the patterned photoresist as a mask, and the barrier metal layer 43 is disposed on the surface of the interlayer insulating film 38 in the stepped contact hole 42 and the interlayer insulating film 43 adjacent thereto. ) And the wiring layer 44 are formed.
상기에서와 같이 콘택홀을 두단계의 공정을 통하여 상,하부가 다른 폭을 갖도록 형성하므로써(콘택홀의 하부가 상부보다 좁은폭을 갖도록 형성하므로써) 베리어메탈층과 배선층(44)이 콘택홀을 통해서 소오스/드레인영역에 정확하게 콘택된다. 즉, 배선층이 소오스/드레인영역에 형성될 콘택마진이 높아진다.As described above, the barrier metal layer and the wiring layer 44 are formed through the contact hole by forming the contact hole so that the upper and lower parts have different widths through the two-step process (by forming the lower part of the contact hole having a narrower width than the upper part). Correct contact is made to the source / drain regions. In other words, the contact margin at which the wiring layer is formed in the source / drain regions is increased.
특히, 경계가 없는 콘택(보더리스 콘택(Borderless contact))영역의 콘택마진을 향상시킬 수 있다.In particular, it is possible to improve the contact margin of the borderless contact (borderless contact) region.
상기와 같은 본 발명 반도체소자의 콘택홀 및 그 형성방법은 다음과 같은 효과가 있다.The above-described contact hole and method of forming the semiconductor device of the present invention have the following effects.
첫째, 콘택홀 하부의 폭을 상부의 폭보다 좁게 형성시키는 공정을 보더리스(Borderless) 콘택공정에 구현하여 콘택 마진을 높일 수 있다.First, the contact margin may be increased by implementing the process of forming the width of the contact hole lower than the width of the upper portion in the borderless contact process.
이에 따라서 콘택 미스-얼라인(Mis-Align)에 따른 졍션 리퀴지 전류의 증가 및 스텐바이(Stand-by) 전류 증가를 억제시킬 수 있다.Accordingly, it is possible to suppress an increase in cushion liquid current and an increase in stand-by current due to contact miss-alignment.
둘째, 층간절연막 상에 질화막을 증착하므로써, 종래에 트랜지스터상에 질화막을 형성하였을 경우에 발생되었던 트랜지스터 특성 열화 및 누설전류가 증가하는 것을 방지할 수 있다.Second, by depositing a nitride film on the interlayer insulating film, it is possible to prevent the transistor characteristics deterioration and leakage current, which have been generated when a nitride film is formed on the transistor in the related art, can be prevented.
셋째, 보더리스(Borderless) 콘택공정에 적용할 경우에 안정된 제품을 만들 수 있으므로 제품의 특성을 향상시킬 수 있고, 또한 제품의 수율을 안정화 시킬 수 있다.Third, when applied to a borderless contact process can make a stable product can improve the characteristics of the product, and also can stabilize the yield of the product.
Claims (5)
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| KR1019990054839A KR20010054168A (en) | 1999-12-03 | 1999-12-03 | Contact of semiconductor device and method for forming the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101005737B1 (en) * | 2003-07-09 | 2011-01-06 | 매그나칩 반도체 유한회사 | Method for forming a metal line in semiconductor device |
| CN102263055A (en) * | 2010-05-28 | 2011-11-30 | 无锡华润上华半导体有限公司 | Semiconductor structure and forming method of contact holes |
| US10686073B2 (en) | 2015-03-02 | 2020-06-16 | Samsung Electronics Co., Ltd. | FinFETs having step sided contact plugs and methods of manufacturing the same |
-
1999
- 1999-12-03 KR KR1019990054839A patent/KR20010054168A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101005737B1 (en) * | 2003-07-09 | 2011-01-06 | 매그나칩 반도체 유한회사 | Method for forming a metal line in semiconductor device |
| CN102263055A (en) * | 2010-05-28 | 2011-11-30 | 无锡华润上华半导体有限公司 | Semiconductor structure and forming method of contact holes |
| US10686073B2 (en) | 2015-03-02 | 2020-06-16 | Samsung Electronics Co., Ltd. | FinFETs having step sided contact plugs and methods of manufacturing the same |
| US11211490B2 (en) | 2015-03-02 | 2021-12-28 | Samsung Electronics Co., Ltd. | FinFETs having step sided contact plugs and methods of manufacturing the same |
| US11764299B2 (en) | 2015-03-02 | 2023-09-19 | Samsung Electronics Co., Ltd. | FinFETs having step sided contact plugs and methods of manufacturing the same |
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