KR19980050429A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- KR19980050429A KR19980050429A KR1019960069252A KR19960069252A KR19980050429A KR 19980050429 A KR19980050429 A KR 19980050429A KR 1019960069252 A KR1019960069252 A KR 1019960069252A KR 19960069252 A KR19960069252 A KR 19960069252A KR 19980050429 A KR19980050429 A KR 19980050429A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- forming
- semiconductor device
- nitride film
- field oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000003860 storage Methods 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 239000010410 layer Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 spacer nitride Chemical class 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조 방법.Semiconductor device manufacturing method.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
콘택 식각시 필드산화막이 식각되어 접합 누설이 발생되는 것을 방지하여 접합 누설에 의한 소자 특성 저하를 방지하고자 함.This is to prevent deterioration of device characteristics due to junction leakage by preventing field leakage from etching the contact oxide.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
LDD(Lightly Doped Drain) 구조의 접합을 형성하기 위해 트랜지스터의 게이트 측벽에 형성되는 스페이서를 산화막이 아닌 질화막으로 형성함으로써, 이후의 계속되는 반도체 제조 공정인 콘택 식각시 필드산화막 상부에 질화막이 남게하여 필드산화막이 식각되는 것을 방지한다.To form a junction of a lightly doped drain (LDD) structure, a spacer formed on a gate sidewall of a transistor is formed of a nitride film instead of an oxide film, so that a nitride film remains on the field oxide film during contact etching, which is a subsequent semiconductor manufacturing process. Prevent it from being etched.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치의 제조 공정.Manufacturing process of semiconductor device.
Description
본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 전하저장전극 콘택 식각시 발생할 수 있는 필드산화막의 식각으로 인한 접합 누설을 미연에 방지하고자 하는 반도체 장치의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device which is intended to prevent junction leakage due to etching of a field oxide film which may occur during etching of a charge storage electrode contact.
도 1A 내지 도 1C를 통해 종래기술 및 그 문제점을 살펴본다.It looks at the prior art and its problems through Figures 1A to 1C.
먼저, 도 1A는 실리콘기판(11)상에 필드산화막(12)을 형성하고, 게이트 전극(도시안됨)을 형성한 다음, 인(P)를 소오스로 한 이온주입을 실시하여 저농도(N-) 접합층(13)을 형성하고, 전체구조 상부에 게이트 측벽에 형성될 스페이서용 산화막(14)을 증착한 후의 단면도이고, 도 1B는 상기 공정 진행후 산화막(14)를 전면 건식 식각한 다음, 상부에 배선막(도시안됨) 등을 형성한 후, 층간절연용 산화막(15)을 증착하고 전하저장 전극 콘택 마스크인 포토레지스트 패턴(16)을 형성한 후의 단면도이다.First, FIG. 1A shows that the field oxide film 12 is formed on the silicon substrate 11, the gate electrode (not shown) is formed, and ion implantation using phosphorus (P) as a source is performed to form a low concentration (N − ). After forming the bonding layer 13 and depositing an oxide film 14 for spacers to be formed on the sidewall of the gate on the entire structure, Figure 1B is a top dry etching of the oxide film 14 after the process proceeds, After the formation of a wiring film (not shown) or the like, the cross-sectional view after the deposition of the interlayer insulating oxide film 15 and the formation of the photoresist pattern 16 serving as the charge storage electrode contact mask is performed.
이어서, 도 1C는 포토레지스트 패턴(16)을 식각 장벽으로 층간절연 산화막(15)을 실리콘기판(1)까지 식각한 후, 포토레지스트 패턴을 제거한 후의 단면도로써, 전하저장 전극 콘택 마스크의 크기가 활성영역 보다 클 경우 또는 전하저장 전극 콘택 마스크의 오정렬이 발생하였을 경우, 활성영역에 비해 미약하게 형성된 필드산화막 하부의 저농도 접합이 깎여 나가 실리콘-서브(통상적으로 웰 지역임)가 노출되어 있음을 알 수 있다.1C is a cross-sectional view of the interlayer insulating oxide film 15 being etched to the silicon substrate 1 by using the photoresist pattern 16 as an etch barrier and then removing the photoresist pattern, and the size of the charge storage electrode contact mask is active. When larger than the region or when misalignment of the charge storage electrode contact mask occurs, the low-concentration junction under the field oxide film, which is weaker than the active region, is cut off, and thus the silicon-sub (usually the well region) is exposed. have.
이와같이, 필드산화막의 가장자리가 깎여나가 노출되는 실리콘-서브에 전하저장전극이 집적 콘택될 경우, 전하의 누설 소오스로 작용하여 반도체 DRAM 장치의 리프레쉬(Refresh) 특성을 저하시키는 문제점이 발생하게 된다.As such, when the charge storage electrode is integrated in the silicon sub-sub with the edge of the field oxide film being exposed, a problem occurs that acts as a leakage source of the charge and degrades the refresh characteristics of the semiconductor DRAM device.
본 발명은 콘택 식각시 필드산화막의 가장자리가 깎여나가 발생되는 소자 특성 저하, 특히 DRAM의 리프레쉬 특성 저하를 방지하는 반도체 장치 제조 방법을 제공함을 그 목적으로 한다.It is an object of the present invention to provide a method of manufacturing a semiconductor device which prevents deterioration of device characteristics, in particular, deterioration of refresh characteristics of DRAM, in which edges of field oxide films are cut off during contact etching.
도 1A 내지 도 1C는 종래기술에 따른 전하저장전극 콘택홀 형성 공정도,1A to 1C are process charts for forming a charge storage electrode contact hole according to the prior art;
도 2A 내지 도 2D는 본 발명의 일실시예에 따른 전하저장전극 콘택홀 형성 공정도.2A through 2D are diagrams illustrating a process of forming a charge storage electrode contact hole according to an exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21: 실리콘 기판 22: 필드산화막21: silicon substrate 22: field oxide film
23: 저농도 접합 24: 질화막23: low concentration bonding 24: nitride film
25: 층간절연용 산화막25: oxide film for interlayer insulation
26: 콘택 마스크인 포토레지스트 패턴26: photoresist pattern that is a contact mask
27: 질화막 마스크인 포토레지스트 패턴27: photoresist pattern that is a nitride film mask
본 발명은 반도체 기판 상에 필드산화막을 형성하는 단계; 활성영역 상에 소정 크기의 게이트 전극을 형성하고, 저농도 접합을 형성하는 단계; 및 전체구조 상부에 질화막을 형성하고, 상기 게이트 전극의 측벽 및 상기 필드산화막 상부에 질화막이 잔류하도록 선택적으로 식각하는 단계를 포함하여 이루어진다.The present invention comprises the steps of forming a field oxide film on a semiconductor substrate; Forming a gate electrode having a predetermined size on the active region and forming a low concentration junction; And forming a nitride film over the entire structure, and selectively etching the nitride film to remain on the sidewall of the gate electrode and the field oxide film.
반도체 DRAM 소자의 리프레쉬 특성을 저하시키는 요인은 여러 가지가 있는데, 그 중에서도 전하저장전극 콘택 식각시 필드산화막의 하부의가장자리까지 깎임으로써 발생되는 전하저장전극의 누설로 인한 것이 매우 많은 부분을 차지한다. 따라서, 본 발명의 일실시예에서는 전하저장전극 콘택 식각시 필드산화막을 보호하도록 질화막을 그 상부에 형성하는 공정 방법을 제시하고 있다.There are a number of factors that lower the refresh characteristics of the semiconductor DRAM device. Among them, the leakage of the charge storage electrode generated by cutting the edge of the field oxide layer to the edge of the field oxide layer during the etching of the charge storage electrode is a very large part. Accordingly, an embodiment of the present invention provides a process method of forming a nitride layer thereon to protect a field oxide layer during etching of a charge storage electrode contact.
도 2A 내지 도 2D는 본 발명의 일실시예에 따른 콘택홀 형성 공정도로서, 이를 통해 본 발명을 상세히 살펴본다.2A to 2D illustrate a process chart for forming a contact hole according to an embodiment of the present invention.
먼저 도 2A는 실리콘기판(21)상에 필드산화막(22)을 형성하고, 게이트 전극(도시안됨)을 형성한 다음, 인(P)를 소오스로 한 이온주입을 실시하여 저농도(N-) 접합층(23)을 형성하고, 전체구조 상부에 게이트 측벽에 형성될 스페이서용 산화막(14)을 증착한 상태에서, 스페이서 마스크인 제1 포토레지스트 패턴(27)을 형성한 후의 단면도이다. 스페이서 마스크는 필드산화막 상부에 오버랩되어 패턴이 형성되도록 한다. 그리고, 여기서 스페이서용 질화막은 단일막 또는 산화막과 같이 적층하여 사용할 수 있다.First, FIG. 2A illustrates the formation of a field oxide film 22 on a silicon substrate 21, a gate electrode (not shown), and then ion implantation using a source of phosphorus (P) to form a low concentration (N − ) junction. It is sectional drawing after forming the 1st photoresist pattern 27 which is a spacer mask in the state which formed the layer 23 and deposited the oxide film 14 for spacers to be formed in a gate sidewall on the whole structure. The spacer mask is overlapped on the field oxide layer to form a pattern. In this case, the spacer nitride film can be laminated and used as a single film or an oxide film.
이어서, 도 2B는 상기 공정 진행후 질화막(24)을 포토레지스트 패턴(27)을 식각 장벽으로하여 선택적으로 건식식각한 다음 포토레지스트 패턴을 제거한 후의 단면도로써, 필드산화막 상부에 질화막(24)이 남아 있는 것을 알 수 있다.FIG. 2B is a cross-sectional view of the nitride film 24 selectively dry-etched using the photoresist pattern 27 as an etch barrier after the process and then removing the photoresist pattern. The nitride film 24 remains on the field oxide layer. I can see that there is.
도 2C는 상기 공정 진행후 상부에 배선막(도시안됨) 등을 형성후 층간절연용 산화막(25)을 증착하고 전하저장 전극 콘택 마스크인 포토레지스트 패턴(26)을 형성한 후의 단면도이다.FIG. 2C is a cross-sectional view after the formation of a wiring film (not shown) and the like, followed by depositing an interlayer insulating oxide film 25 and forming a photoresist pattern 26 serving as a charge storage electrode contact mask.
도 2D는 상기 전하저장 전극 콘택 마스크인 포토레지스트 패턴(26)을 식각 장벽으로 산화막(25)을 실리콘 기판(21)까지 선택적으로 건식 식각한 후, 포토레지스트 패턴(26)을 제거한 후의 단면도로써, 상기 콘택 건식 식각시 질화막에 대한 산화막의 선택비가 10:1이상이므로 전하저장 전극 콘택의 크기가 활성영역 영역보다 클 경우 또는 전하저장 전극 콘택 마스크 패턴 형성시 오정렬이 발생하였을 경우에도, 필드산화막은 상부의 질화막이 식각 장벽 역할을하여 가장자리가 식각되지 않아서, 저농도 접합(23) 형성이 안된 실리콘 기판은 노출되지 않는다.FIG. 2D is a cross-sectional view after the photoresist pattern 26, which is the charge storage electrode contact mask, is selectively etched with the oxide film 25 to the silicon substrate 21 using an etch barrier, and then the photoresist pattern 26 is removed. Since the selectivity ratio of the oxide layer to the nitride layer during the dry etching of the contact is greater than or equal to 10: 1, even when the size of the charge storage electrode contact is larger than the active region or when misalignment occurs when the charge storage electrode contact mask pattern is formed, Since the nitride film serves as an etching barrier and the edge is not etched, the silicon substrate on which the low-concentration junction 23 is not formed is not exposed.
상기와 같이 이루어지는 본 발명의 일실시예에서는 저농도 접합이 형성되지 않았거나 미약하게 형성된 필드산화막 하부 지역에는 전하저장 전극 콘택이 형성되지 않게 함으로써, 반도체 DRAM 소자의 리프레쉬 특성을 향상시킬 수 있는 이점이 있다.According to the exemplary embodiment of the present invention, the charge storage electrode contact is not formed in the lower region where the low concentration junction is not formed or is weakly formed, thereby improving the refresh characteristics of the semiconductor DRAM device. .
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.
본 발명은 반도체 장치를 제조함에 있어, LDD 구조의 트랜지스터를 형성하기 위해 게이트의 측벽에 형성되는 스페이서를 질화막으로 사용하고, 이 질화막의 스페이서 형성시 선택적으로 건식식각을 통해 필드산화막 상부에 질화막이 남게하는 방법으로, 저농도 도핑이 이루어지지 않거나 미약하게 형성된 필드산화막 하부의 실리콘 기판은 콘택 형성이 안되게 함으로써, 반도체 장치의 특성, 특히 DRAM 소자의 리프레쉬 특성과 수율을향상시킬수있다.The present invention uses a spacer formed on the sidewall of the gate as a nitride film to form a transistor of the LDD structure in the manufacture of a semiconductor device, and when the spacer of the nitride film is formed, the nitride film is left over the field oxide film through selective dry etching. In this way, the silicon substrate under the field oxide film, which is not lightly doped or weakly doped, can be prevented from forming a contact, thereby improving the characteristics of the semiconductor device, particularly the refresh characteristics and the yield of the DRAM device.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960069252A KR19980050429A (en) | 1996-12-20 | 1996-12-20 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960069252A KR19980050429A (en) | 1996-12-20 | 1996-12-20 | Semiconductor device manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980050429A true KR19980050429A (en) | 1998-09-15 |
Family
ID=66384396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960069252A Withdrawn KR19980050429A (en) | 1996-12-20 | 1996-12-20 | Semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980050429A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100478479B1 (en) * | 2002-07-30 | 2005-03-22 | 동부아남반도체 주식회사 | Method for manufacturing MOS transistor |
-
1996
- 1996-12-20 KR KR1019960069252A patent/KR19980050429A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100478479B1 (en) * | 2002-07-30 | 2005-03-22 | 동부아남반도체 주식회사 | Method for manufacturing MOS transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100278273B1 (en) | A method for forming contact holes in semiconductor device | |
| KR100223832B1 (en) | Semiconductor device and manufacturing method | |
| KR960011664B1 (en) | Capacitor Formation Method of Semiconductor Device | |
| KR0135690B1 (en) | Fabrication method of contact in semiconductor device | |
| KR19980050429A (en) | Semiconductor device manufacturing method | |
| KR100411232B1 (en) | Method of manufacturing transistor in semiconductor device | |
| KR100486120B1 (en) | Method for forming of mos transistor | |
| KR100265370B1 (en) | A method for fabricating dram device | |
| KR100477786B1 (en) | Method for forming contact in semiconductor device | |
| KR100273685B1 (en) | Method for forming semiconductor device | |
| KR20050071020A (en) | Method for fabricating the mos field effect transistor | |
| KR100340884B1 (en) | Method for forming transistor in semiconductor device | |
| KR20010054168A (en) | Contact of semiconductor device and method for forming the same | |
| KR101012438B1 (en) | Method of manufacturing semiconductor device | |
| KR19980037651A (en) | Pad of semiconductor memory device and manufacturing method thereof | |
| KR100271661B1 (en) | Method for fabricating semiconductor device | |
| KR0147474B1 (en) | The manufacture of semiconductor device | |
| KR100198637B1 (en) | Method of manufacturing semiconductor device | |
| KR930009476B1 (en) | Method for manufacturing self-aligned contacts in semiconductor devices | |
| KR100252767B1 (en) | A semiconductor device and method for fabricating the same | |
| KR100307296B1 (en) | A method of forming contact in semiconductor device | |
| KR0147770B1 (en) | Manufacture method of semiconductor device | |
| KR20010003206A (en) | Method of manufacturing SOI device | |
| KR100223333B1 (en) | Method for forming a contact of semiconductor device | |
| KR100261991B1 (en) | Manufacturing method for transistor of semiconductor memory cell and its structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19961220 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |