KR19990003056A - Device Separation Method of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method of fabricating a device isolation layer of a semiconductor device, comprising forming a nitride film pattern and a pad oxide film pattern on a semiconductor substrate, forming a trench in which a lower portion of the semiconductor substrate is exposed by etching the patterns, and then performing two heat treatments. Performing a process to form a thermal oxide film on the trench sidewalls and performing a first field stop ion implantation process on the entire surface, and then forming a CVD-oxide film having a predetermined thickness to fill the trench, until the nitride film is exposed by a CMP process. After planarizing to polish, the nitride film is removed by a wet etching process to expose the CVD oxide film and the pad oxide film, and a second field stop ion implantation is performed on the front surface to eliminate non-uniform field stop ion implantation. The present invention relates to a technique for preventing and improving the battery characteristics of a device.

Description

Device Separation Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a device isolation film of a semiconductor device, in particular, after forming a thermal oxide film on a trench surface, performing a first field stop ion implantation process, removing the nitride film, and then exposing a CVD oxide film and a pad oxide film. By performing the second field stop ion implantation process, the present invention relates to a technique for preventing the non-uniformity of the field stop ion implantation caused by the nonuniformity of the CMP process to improve the electrical characteristics of the device.

In general, a semiconductor device with low integration has no problem in patterning or planarization of each conductive layer due to the small step, but when the device is highly integrated and the number of steps and stacked layers between the layers increases, the process of fabricating the device may include Defects, etc. occur, and the planarization process of flattening the upper portions of the stacked layers has an important effect on process yield and reliability of the device.

In modern 1M DRAM or higher devices, HDP (High Density Plasma) CVD oxide film or B.P is formed by chemical vapor deposition (CVD) method which contains a large amount of impurities and has excellent fluidity. Bos Phosphor silicate Glass (hereinafter referred to as BPSG) and Teos (tetra ethyl rotho silicate) (hereinafter referred to as TEOS) oxide films are widely used as planarization films.

However, the planarization films are limited in the degree of planarization in spite of their excellent fluidity. Therefore, the level difference between the cell area and the peripheral circuit area is maintained at 0.8-1.0 μm, so that the level difference is continuously maintained. Causes problems.

In other words, as the wiring size decreases in the photolithography process of metal wiring, the depth of focus decreases as the ultraviolet exposure machine is used (about 0.4 μm). Metal wires may break or cause bridges.

In addition, a large amount of impurities have another problem. To solve the above problems, the CMP process has appeared, and if the BPSG thin film is deposited with a thick CMP device to reduce the step, the CMP process Difficult to smooth the entire surface due to the difference in polishing speed in the dense and non-dense areas.

In addition, such a problem may occur not only in one device but also in a wafer, and thus, it may be difficult to control the etching thickness in the subsequent etching process.

1A to 1C are cross-sectional views of a device isolation film of a semiconductor device according to the related art.

First, a pad oxide film 12 and a nitride film (not shown) are sequentially formed below the semiconductor substrate 10, and then a nitride film pattern and a pad oxide film pattern are formed using a device isolation mask.

Next, a trench is formed in which the lower portion of the semiconductor substrate is exposed by etching the patterns.

Next, an insulating film 14 having a predetermined thickness filling the trench is formed, and then polished and planarized until the nitride film is exposed by a CMP process.

Next, the nitride film is removed by a wet process, followed by a fieldstop ion implantation process.

Here, FIG. 1A shows that the implant depth is formed too far below the field oxide layer during the field stop ion implantation process, and FIG. 1C shows the most ideal implant depth.

According to the conventional technique as described above, in the trench trench isolation (STI) process, the trench is filled with an insulator, the nitride film is removed after the CMP process, and the field stop ion implantation process is performed. Can't Politics

Therefore, there are many field oxides in the non-uniformity at the time of field stop ion implantation due to the non-uniformity of the CMP process, i.

Therefore, there are many field oxide films in poorly polished areas (Fig. 1B), so that field stop ion implantation is poor in the trench bottom, or the implant depth is too deep below the field oxide films in heavily polished areas (Fig. 1A). There is a problem in that the non-uniformity of the field stop ion implantation due to the non-uniformity of the CMP process.

Accordingly, the present invention is to solve the above problems and to perform two field-stop ion implantation process to prevent the non-uniformity of field-stop ion implantation due to the non-uniformity of the CMP process, the thermal oxide film is first applied to the trench surface After the formation, a first fieldstop ion implantation process is performed, and a second fieldstop ion implantation process is performed on the exposed CVD-oxide and pad oxide layers by removing the second cut film, thereby improving the electrical characteristics of the device. An object of the present invention is to provide a method for manufacturing a device isolation film.

1A to 1C are cross-sectional views of a device isolation film process of a semiconductor device according to the related art.

2a to 2h is a manufacturing process diagram of the device isolation film of the semiconductor device according to the present invention

* Explanation of symbols for main parts of drawing

10,20 semiconductor substrate, 12,22 pad oxide film, 24 nitride film, 26 trench, 28 thermal oxide film, 30 CVD-oxide film, 14 insulating film

In order to achieve the above object, a device isolation film manufacturing method of a semiconductor device according to the present invention

Sequentially forming a pad oxide film and a nitride film on the semiconductor substrate;

Etching the semiconductor substrate with the device isolation mask until the semiconductor substrate is exposed to form a film layer pattern and a pad oxide layer pattern;

Forming a trench in which the lower portion of the semiconductor substrate is exposed by etching the patterns;

Forming a thermal oxide film on the sidewalls of the trench by performing a heat treatment process twice;

Performing a first field stop ion implantation on the entire surface of the structure;

Forming a CVD-oxide film having a predetermined thickness to fill the trench;

Polishing and planarizing the CNT process until the nitride film is exposed;

Removing the nitride film by a wet etching process to expose the CVD oxide film and the pad oxide film;

And performing a second field ion implantation on the entire surface of the structure.

Hereinafter, a device isolation film manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device according to the present invention.

First, the pad oxide film 22 and the nitride film 24 are sequentially formed on the semiconducting substrate 20.

In this case, the pad oxide film 22 is formed to a thickness of 50 ~ 150Å, the nitride film 24 is formed to a thickness of 1000 ~ 3000Å. (See Figure 2A)

Subsequently, the semiconductor substrate 20 is etched using the device isolation mask to expose the nitride film 24 pattern and the pad oxide film 22 pattern.

A trench 26 is then formed under the semiconductor substrate 20 using the patterns 24 and 22 as etch barriers.

At this time, the trench 26 is formed to a depth of 1500 ~ 4000Å thickness. (See Figure 2b)

Next, two heat treatment steps may be performed. First, a thermal oxide layer 28 having a thickness of 50 to 200 μs is formed on the sidewalls of the trench 26, and 100 to 300 μm thickness is etched by a wet process. A thermal oxide film 28 having a thickness of 50 to 200 Å is formed on the side wall. (See FIG. 2C)

Subsequently, the first field stop ion implantation with a depth of 100 to 500 kPa is applied to the entire surface of the structure.

At this time, considering the thickness of the nitride film 24 of the active region, the ion implantation is formed on the surface of the semiconductor substrate 20. (See FIG. 2D)

Next, a CVD oxide film 30 having a predetermined thickness filling the trench 26 is formed.

At this time, an O ₃ -TEOS-oxide film is formed in the CVD oxide film 30 to a thickness of 4000-7000 Å (see FIG. 2E).

Then, the CMP process is polished and planarized until the nitride film 24 is exposed. (See Figure 2f)

Next, the nitride film 24 is removed by a wet etching process to expose the CVD-oxide film 30 in the field region and the pad oxide film 22 in the active region.

In this case, the pad oxide film 22 is used as an ion implantation screen oxide film (see FIG. 2G).

Then, a second field stop ion implantation is performed on the entire surface of the structure.

Here, the second field stop ion implantation is injected to a depth of 100 ~ 1000Å.

At this time, it is possible to prevent ion implantation unevenness due to thickness unevenness of the field oxide film 22 after the CMP process (see FIG. 2H).

As described above, according to the present invention, two field stop ion implantation processes are performed to prevent field stop ion implantation unevenness that may be caused by the difference in the thickness of the field oxide according to the CMP process, thereby improving the electrical characteristics of the device. There is an advantage of improving the reliability of the device.

Claims (9)

Sequentially forming a pad oxide film and a nitride film on the semiconductor substrate; Forming a nitride film pattern and a pad oxide film pattern by etching until the semiconductor substrate is exposed as a sound separation mask; Forming a trench in which the lower portion of the semiconductor substrate is exposed by etching the patterns; Forming a thermal oxide film on the sidewalls of the trench by performing two heat treatment steps; Performing a first field stop ion implantation on the entire surface of the structure; Forming a CVD-oxide film having a predetermined thickness to fill the trench; Polishing and planarizing the CNT process until the nitride film is exposed; Exposing the CVD oxide film and the pad oxide film by removing the nitride film by a wet etching process; And focusing the second field stop ion implantation on the entire surface of the structure. The method of claim 1, wherein the pad oxide layer has a thickness of about 50 to about 150 microns. The method of claim 1, wherein the nitride film is formed to have a thickness of 1000 to 3000 Å. The method of claim 1, wherein the trench is formed to a depth of 1500 to 4000 microns. The method of claim 1, wherein the thermal oxide layer is etched to a thickness of about 100 to about 300 microns in two heat treatment steps. The method of claim 1, wherein the thermal oxide film is formed to a thickness of 50 to 200 μm. The method of claim 1, wherein the CVD oxide film is formed to a thickness of 4000 ~ 7000 Å. 2. The method of claim 1, wherein the first field stop is implanted into a depth of 100 to 500 kV. 2. The method of claim 1, wherein the second field stop is implanted at a depth of 100 to 1000 microns.