KR20030001808A - Method for Forming Fuse layer in Semiconductor Device - Google Patents

Abstract

PURPOSE: A fuse formation method of semiconductor devices is provided to minimize generation of particle residues during a repair by forming a field channel as a fuse layer at lower of a trench isolation layer. CONSTITUTION: A pad oxide layer and a pad nitride layer are sequentially formed on a substrate. A shallow trench is formed by selectively etching the pad nitride layer, the pad oxide layer and the substrate. A fuse layer(16) is formed at lower of the shallow trench by implanting dopants into the shallow trench. An isolation layer is formed by filling an oxide layer into the shallow trench including the fuse layer(16). The pad nitride layer and the pad oxide layer are removed by CMP(Chemical Mechanical Polishing).

Description

Method for forming fuse of semiconductor device {Method for Forming Fuse layer in Semiconductor Device}

The present invention relates, in particular, to a method of forming a fuse in a semiconductor device in which field channels are formed under a trench type isolation layer to minimize residual foreign matters during a repair.

A fuse forming method of a conventional semiconductor device will be described below.

After the lower oxide film is formed on the substrate, a polysilicon layer is formed on the lower oxide film.

Subsequently, the photoresist is coated on the lower oxide film, and then exposed and developed to pattern the film.

The polysilicon layer is selectively removed using the patterned photoresist as a mask to form a fuse layer.

In addition, an upper oxide layer is deposited on the fuse layer to buffer the fuse layer.

However, the fuse of the semiconductor device formed by the conventional process as described above has the following problems.

First, the fuse layer uses a word line, a bit line, a storage node, a plate, and the like, so that when the fuse is cut with a laser during repair, Ruptures remain in the fuse layer and are often absorbed by neighboring normal fuses, causing electrical shorts.

Second, due to the oxide films (approximately 3000Å thick) formed on the upper and lower portions of the fuse layer to prevent damage to the substrate, residual materials remain even when the fuse is cut with a laser to deteriorate the characteristics of the fuse layer. .

The present invention has been made to solve the above problems to provide a method for forming a fuse of a semiconductor device that minimizes the generation of foreign matter during repair by forming a field channel (channel) under the trench type isolation layer , Its purpose is.

1A to 1E are cross-sectional views illustrating a fuse forming method of a semiconductor device in accordance with a first embodiment of the present invention.

2 is a cross-sectional view illustrating a method of forming a fuse of a semiconductor device in accordance with a second embodiment of the present invention.

Explanation of symbols of the main parts of the drawings

11: p-type substrate (p-sub) 12: pad oxide film

13 pad nitride film 14 photosensitive film

15: fuse layer unformed area 16: fuse layer

17 device isolation layer 18 contact region

21 p-type substrate 22 pad insulating film layer

23 device isolation layer 24 fuse layer

In order to achieve the above object, a fuse forming method of a semiconductor device according to an embodiment of the present invention may include depositing a pad oxide film and a pad nitride film on a substrate in turn, and selectively removing the pad nitride film, the pad oxide film, and the substrate to form a thin trench. And implanting a substrate and a release ion implantation process using a mask on the thin trench to form a fuse layer on a predetermined region of the lower surface of the thin trench, and filling the thin trench including the fuse layer with an oxide film. And forming a device isolation film and removing the pad nitride film and the pad oxide film remaining on the substrate through a planarization process using the pad oxide film as an end point.

In this case, the fuse layer may be formed by forming an isolation layer and then performing an ion implantation process on the isolation layer using a mask.

Hereinafter, a method of forming a fuse of a semiconductor device according to a first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of forming a fuse of a semiconductor device according to a first embodiment of the present invention.

As shown in FIG. 1A, a pad oxide film 12 and a pad nitride film 13 are sequentially deposited on the p-type substrate 11.

In this case, the pad oxide layer 12 may include HDP SOG (High Density Plasma Spin On Glass), USG (Undoped Silicate Glass), PE-TEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), LP-TEOS (Low Pressure Tetra Ethyl Ortho Silicate) Deposition by one of the methods of Phosphorus Silicate Glass (PSG) and Boron Phosphorus Silicate Glass (BPSG).

In addition, the pad nitride layer 13 may be deposited using PE-Nitride (Plasma Enhanced Nitride) or LP-Nitride (Low Plasma Nitride).

The thickness of the pad layer may be adjusted by depositing a polysilicon layer between the pad oxide layer 12 and the pad nitride layer 13.

As shown in FIG. 1B, the photoresist layer 14 is deposited, exposed and developed, and then patterned, and then the pad nitride layer 13 and the pad oxide layer 12 are selectively removed by using a mask for forming an isolation layer to remove a thin trench. Form.

At this time, the thin trench is formed as the term, means that the groove is dug into a trench of a thin thickness compared to the overall thickness of the substrate.

As illustrated in FIG. 1C, an n-type (substrate and release) ion implantation process is performed using a mask defining a fuse layer on the thin trench to form a fuse layer 16 on the lower surface of the trench. Here, the illustrated fuse non-forming region 15 is a region where ions are not transmitted through the ion implantation process of the mask defining the fuse layer.

At this time, the n-type ions use P or As.

As illustrated in FIG. 1D, an oxide film is sufficiently deposited on the entire surface of the substrate to fill the trench in the substrate 11. These oxides can be deposited using HDP High Density Plasma Spin On Glass (HDP SOG), Undoped Silicate Glass (USG), Plasma Enhanced Tetra Ethyl Ortho Silicate (PE-TEOS), Low Pressure Tetra Ethyl Ortho Silicate (LP-TEOS), Phosphorus It is deposited by one of Silicate Glass) and BPSG (Boron Phosphorus Silicate Glass).

Next, a planarization process is performed by using the lower surface of the pad oxide film as an end point to remove the pad oxide film and the pad nitride film remaining on the substrate. Through the planarization process, the trench isolation device isolation layer 17 is formed.

The device isolation layer 17 serves as a buffer layer as the fuse layer during laser cutting.

As shown in FIG. 1E, the device isolation layer 17 on the fuse layer 16 is selectively removed to form a contact region, and a metal wiring is formed on the device isolation layer including the contact region 18. At this time, the metal wiring and the fuse layer are connected to each other through the contact region 18.

In the repair process, laser cutting is performed on a portion corresponding to a predetermined fuse to cut a predetermined fuse of the fuse layer 16.

When processed in the same manner as in the present invention, it is not necessary to deposit a separate oxide film under the fuse layer 16, thereby minimizing residual material at the cut portion after laser cutting.

Hereinafter, a method of forming a fuse of a semiconductor device according to a second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross sectional view showing a method of forming a fuse of a semiconductor device according to a second embodiment of the present invention.

As shown in FIG. 2, the second embodiment of the present invention proceeds to form the fuse layer after forming the isolation layer. The semiconductor device obtains the same effect as the first embodiment and the fuse layer formation and the formation of the isolation layer are reversed. Of fuse formation method.

That is, in the method of forming a fuse of the semiconductor device according to the second embodiment of the present invention, the step of sequentially depositing the pad insulating film layer 22 on the substrate 21 and selectively forming the pad insulating film layer 22 and the substrate 21 is performed. Forming a thin trench to form a device isolation layer 23 by filling the thin trench with an oxide film; and removing the remaining pad insulating layer 22 through a planarization process; 23) forming a fuse layer 24 on a predetermined region of the lower surface of the device isolation layer by performing an ion implantation process of a substrate and a release using a mask.

In addition, as a third embodiment of the present invention, before forming the n-type ion implantation process in FIG. There is a method of forming a fuse of a semiconductor device for forming a fuse layer.

The wells at this time may form one well or a plurality of wells under the thin trench region.

The fuse forming method of the semiconductor device of the present invention as described above has the following effects.

First, the process may be simplified by omitting the process of depositing an oxide film having a thickness of 3000 kV deposited above and below the fuse layer to form a fuse.

Secondly, instead of depositing a separate oxide film to protect the fuse layer, a fuse layer may be formed under the device isolation layer to serve as a buffer layer during laser cutting, thereby minimizing damage to other devices.

Third, due to the simplification of the process, almost no residual material is generated during the repair, thereby increasing the reliability of the fuse and improving lactation.

Claims (11)

Sequentially depositing a pad oxide film and a pad nitride film on the substrate; Selectively removing the pad nitride layer, the pad oxide layer, and the substrate to form a thin trench; Forming a fuse layer on a predetermined region of the lower surface of the thin trench by performing an ion implantation process with a substrate on the thin trench using a mask; Forming a device isolation layer by filling a thin trench including the fuse layer with an oxide layer; And removing the pad nitride film and the pad oxide film remaining on the substrate through a planarization process using the lower portion of the pad oxide film as an end point. The method of claim 1, wherein a thickness of the pad layer is controlled by depositing a polysilicon layer between the pad oxide layer and the pad nitride layer. The method of claim 1, wherein the pad oxide layer is deposited using one of HDP, SOG, USG, PE-TEOS, BPSG, and PSG. The method of claim 1, wherein the pad nitride layer is deposited using a method of PE-nitride or LP-nitride. The method of claim 1, wherein the ion implantation process is performed using ions of P or As. The method of claim 1, wherein the oxide filling the trench serves as a buffer for the fuse layer during laser cutting. The method of claim 6, wherein the oxide layer is deposited using one of HDP, SOG, USG, PE-TEOS, BPSG, and PSG. Sequentially depositing a pad oxide film and a pad nitride film on the substrate; Selectively removing the pad nitride layer, the pad oxide layer, and the substrate to form a thin trench; Filling the thin trench with an oxide film to form an isolation layer; Removing the pad nitride film and the pad oxide film remaining on the substrate through a planarization process using the pad oxide film as an end point; And forming a fuse layer on a predetermined region of the lower surface of the device isolation layer by performing an ion implantation process with a substrate on the device isolation layer using a mask. Sequentially depositing a pad oxide film and a pad nitride film on the substrate; Selectively removing the pad nitride layer, the pad oxide layer, and the substrate to form a thin trench; Forming a well region in the thin trench lower substrate by performing an ion implantation process homogeneous with the substrate on the thin trench; Forming a fuse layer on a predetermined region of the lower surface of the thin trench by performing an ion implantation process with a substrate on the thin trench using a mask; Forming a device isolation layer by filling a thin trench including the fuse layer with an oxide layer; And removing the pad nitride film and the pad oxide film remaining on the substrate through a planarization process using the lower portion of the pad oxide film as an end point. 10. The method of claim 9, wherein the well region is formed of a plurality of wells. The contact method is formed on a predetermined region of the fuse layer deposited on the lower surface of the device isolation layer to connect the fuse layer and the upper metal wiring.