KR19990004560A - Device Separation Method of Semiconductor Device - Google Patents
Device Separation Method of Semiconductor Device Download PDFInfo
- Publication number
- KR19990004560A KR19990004560A KR1019970028687A KR19970028687A KR19990004560A KR 19990004560 A KR19990004560 A KR 19990004560A KR 1019970028687 A KR1019970028687 A KR 1019970028687A KR 19970028687 A KR19970028687 A KR 19970028687A KR 19990004560 A KR19990004560 A KR 19990004560A
- Authority
- KR
- South Korea
- Prior art keywords
- trench
- teos
- oxide film
- forming
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000926 separation method Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 45
- 150000004767 nitrides Chemical class 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 52
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자의 소자분리막 제조방법에 관한 것으로, 트랜치가 형성되는 반도체 기판 하부의 필드영역에 절연막으로 O3-TEOS-oxide막을 액티브영역 보다 높게 형성함으로써 트랜치 모서리 부분에서의 씨닝(thinning)현상을 방지하여 소자의 전기적 특성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a device isolation film of a semiconductor device, wherein a thinning phenomenon in a corner portion of a trench is formed by forming an O 3 -TEOS-oxide film higher than an active region as an insulating layer in a field region below a semiconductor substrate where a trench is formed. The present invention relates to a technology for improving electrical characteristics of devices by preventing the damage.
이를 위한 본 발명은 반도체 기판 상부에 질화막패턴과 패드산화막패턴을 형성하고 상기 패턴들을 식각장벽으로 반도체 기판의 하부에 트랜치를 형성한 다음, 상기 트랜치 표면에 열산화막을 형성하고 플라즈마 전처리 공정을 실시한 후, 전표면에 제 1 O3-TEOS-oxide막을 형성하고 CMP공정으로 상기 질화막이 노출될 때까지 연마한 다음, 습식공정으로 상기 질화막을 제거하여 상기 제 1 O3-TEOS-oxide막과 패드산화막을 노출시킨 후, 전표면에 제 2 O3-TEOS-oxide막을 형성하고 희생산화 및 게이트 세정공정을 거쳐 트랜치 플러그를 형성하는 공정을 구비하는 반도체 소자의 소자분리막 제조방법에 관한 것이다.According to the present invention, a nitride pattern and a pad oxide pattern are formed on the semiconductor substrate, and a trench is formed on the lower surface of the semiconductor substrate using the patterns as an etch barrier. Then, a thermal oxide layer is formed on the trench surface and the plasma pretreatment process is performed. Forming a first O 3 -TEOS-oxide film on the entire surface, and polishing the nitride film until the nitride film is exposed by a CMP process, and then removing the nitride film by a wet process, the first O 3 -TEOS-oxide film and the pad oxide film After exposing the to form a second O 3 -TEOS-oxide film on the entire surface, and a step of forming a trench plug through the sacrificial oxidation and gate cleaning process.
Description
본 발명은 반도체 소자의 소자분리막 제조방법에 관한 것으로, 특히 트랜치가 형성되는 반도체 기판 하부의 필드영역에 절연막으로 O3-TEOS-oxide막을 액티브영역 보다 높게 형성함으로써 트랜치 모서리 부분에서의 씨닝(thinning)현상을 방지하여 소자의 전기적 특성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, and in particular, thinning at a trench edge part by forming an O 3 -TEOS-oxide film higher than an active region as an insulating film in a field region below a semiconductor substrate where a trench is formed. The present invention relates to a technique for preventing the phenomenon and improving the electrical characteristics of the device.
일반적으로, 집적도가 낮은 반도체소자는 단차가 작아 각 도전층들의 패턴닝이나 평탄화에 별다른 문제점이 없었으나, 소자가 고집적화되어 각층들간의 단차 및 적층되는 막의 수가 증가되면 소자의 제조 공정에서 나칭이나 단선 등의 불량들이 발생하게 되며, 이를 방지하기 위하여 적층막들의 상부를 평탄화하는 평탄화 공정이 공정수율 및 소자의 신뢰성에 중요한 영향을 미치게 된다.In general, a semiconductor device with low integration has no problem in patterning or planarization of each conductive layer due to a small step. However, when the device is highly integrated and there is an increase in the number of steps and stacked layers between the layers, in the fabrication process of the device, the stepping or disconnection occurs. Defects, etc., are generated, and the planarization process of planarizing the upper part of the stacked layers has a significant effect on process yield and device reliability.
현재 1M DRAM 이상의 소자에서는 다량의 불순물을 함유하여 유동성이 우수하고 화학기상증착(chemical vapor deposition; 이하 CVD라 칭함) 방법으로 형성되어 단차피복성이 우수한 HDP(High density Plasma)CVD나 비.피.에스.지(Boro Phosphor Silicate Glass; 이하 BPSG라 칭함), 테오스(Tetra ehtyl ortho silicate; 이하 TEOS라 칭함) 산화막 등을 평탄화막으로 널리 사용하고 있다.Currently, 1M DRAM or more devices contain a large amount of impurities and are formed by chemical vapor deposition (hereinafter referred to as CVD) method, and thus have high step coverage and high density plasma (HDP) CVD or B.P. Boro Phosphor Silicate Glass (hereinafter referred to as BPSG) and Teos (Tetra ehtyl ortho silicate; referred to as TEOS) oxide films and the like are widely used as planarization films.
그러나, 상기의 평탄화막들은 우수한 유동성에도 불구하고 평탄화의 정도에 한계가 있어 셀영역과 주변회로지역의 단차가 0.8 ~ 1.0㎛로 단차가 계속 유지되어 256M DRAM이상의 고집적 소자 제조 공정에 있어서 금속 배선 공정에 문제를 일으킨다.However, the planarization films have a limited degree of planarization in spite of their excellent fluidity. Therefore, the level difference between the cell region and the peripheral circuit region is maintained at 0.8 to 1.0 μm, so that the level difference is continuously maintained. Causes problems.
즉, 금속배선의 사진공정에서 배선크기가 작아짐에 따라 원자외선 노광기를 사용하게 됨에 따라 초점 심도가 작아져(약 0.4㎛) 상기의 단차에서는 금속배선을 형성할 수 없을 뿐만 아니라, 식각 공정시에도 금속배선이 끊어지거나 브리지를 유발하게 된다.In other words, as the wiring size decreases in the photolithography process of metal wiring, the depth of focus decreases as the ultraviolet ray exposure machine is used (about 0.4 μm). Metal wires may break or cause bridges.
또한, 불순물이 다량으로 포함되어 있어 또 다른 문제점을 갖고 있는데, 상기의 문제점을 해결하기 위해 CMP 공정이 등장하였으며, BPSG 박막을 두껍게 증착하여 CMP장치로 연마하면 단차를 줄여줄 수 있으나, CMP공정은 조밀한 지역과 조밀하지 않은 지역에서 연마 속도 차이가 나는 현상에 의해 전면 평탄화에 어려움이 있다.In addition, a large amount of impurities have another problem. To solve the above problems, a CMP process has emerged, and when the BPSG thin film is thickly deposited and polished with a CMP device, the step difference can be reduced. Difficult to smooth the entire surface due to the difference in polishing speed in the dense and non-dense areas.
그리고, 이러한 문제는 한 소자 내에서 뿐만 아니라 웨이퍼 내에서도 발생하여 후속 공정인 식각 공정에서 식각 두께의 조절이 힘들어지는 문제가 있다.In addition, such a problem may occur not only in one device but also in a wafer, and thus, it may be difficult to control the etching thickness in the subsequent etching process.
도면에는 도시되어 있지 않으나, 종래 기술에 따른 반도체 소자의 소자분리막 제조공정은 다음과 같다.Although not shown in the drawings, a device isolation film manufacturing process of a semiconductor device according to the prior art is as follows.
먼저, 반도체 기판 상부에 열산화막과 질화막을 순차적으로 형성한다음, 소자분리용 마스크로 반도체 기판이 노출될 때까지 식각하여 질화막패턴과 열산화막패턴을 형성한다.First, a thermal oxide film and a nitride film are sequentially formed on the semiconductor substrate, and then the nitride film pattern and the thermal oxide film pattern are formed by etching until the semiconductor substrate is exposed with a device isolation mask.
다음, 상기 패턴들을 식각장벽으로 반도체 기판의 하부가 노출되는 트랜치를 형성한다.Next, a trench is formed in which the lower portion of the semiconductor substrate is exposed by etching the patterns.
그 다음, 상기 트랜치를 매립하는 일정두께의 절연막을 형성한 다음, CMP공정으로 상기 질화막을 노출될 때까지 연마하여 평탄화한다.Next, an insulating film having a predetermined thickness filling the trench is formed, and then, the CN film is polished and planarized until the nitride film is exposed.
다음, 상기 질화막을 제거하여 상기 절연막과 열산화막을 노출시킨다음, 희생산화막 제거 및 게이트 세정공정을 진행한다.Next, the nitride film is removed to expose the insulating film and the thermal oxide film, and then the sacrificial oxide film is removed and the gate cleaning process is performed.
상기와 같은 종래 기술에 따르면, STI(shallow trench isolation) 공정에서 트랜치에 절연물을 채우고 CMP 공정후 희생산화막 제거 및 게이트 세정공정을 거치게 되면 트랜치 모서리 부분에서의 절연물의 높이가 액티브 영역보다 낮아지게 된다.According to the prior art as described above, when the trench is filled with an insulator in the shallow trench isolation (STI) process and the sacrificial oxide film is removed and the gate cleaning process is performed after the CMP process, the height of the insulator at the corner of the trench is lower than that of the active region.
즉, 소자분리막의 액티브여역 모서리 부근에서의 전기장이 집중되어 문턱전압 보다 낮은 전압에서 큰 누설전류가 발생되어 소자의 전기적 특성이 열화되는 문제점이 있다.That is, a large leakage current is generated at a voltage lower than the threshold voltage due to the concentration of an electric field near the edge of the active region of the device isolation layer, thereby deteriorating the electrical characteristics of the device.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 트랜치가 형성되는 반도체 기판 하부의 필드영역에 절연막으로 O3-TEOS-oxide막을 두차례에 걸쳐 형성하되 액티브영역 보다 높게 형성함으로써 트랜치 모서리 부분에서의 씨닝(thinning)현상을 방지하여 소자의 전기적 특성을 향상시키는 반도체 소자의 소자 분리막 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above problems and to form an O 3 -TEOS-oxide film twice as an insulating film in the field region under the semiconductor substrate where the trench is formed, but higher than the active region in the trench corner portion It is an object of the present invention to provide a device isolation film manufacturing method of a semiconductor device that prevents thinning and improves electrical characteristics of the device.
도 1a 내지 도 1h 는 본 발명에 따른 반도체 소자의 소자분리막 제조공정도1A to 1H are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
10 :반도체 기판 12 : 패드산화막10 semiconductor substrate 12 pad oxide film
14 : 질화막 16 : 트랜치14 nitride layer 16 trench
18 : 열산화막 20, 22 : 제 1,2 O3-TEOS-oxide막18: thermal oxide film 20, 22: first 1,2 O 3 -TEOS-oxide film
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 소자분리막 제조 방법은In order to achieve the above object, a device isolation film manufacturing method of a semiconductor device according to the present invention
반도체 기판 상부에 패드산호막과 질화막을 순차적으로 형성하는 공정과,Sequentially forming a pad coral film and a nitride film on the semiconductor substrate;
소자분리용 마스크로 반도체 기판이 노출될 때까지 식각하여 질화막패턴과 패드산화막패턴을 형성하는 공정과,Forming a nitride film pattern and a pad oxide film pattern by etching until the semiconductor substrate is exposed with a device isolation mask;
상기 패턴들을 식각장벽으로 이용하여 반도체 기판의 하부에 트랜치를 형성하는 공정과,Forming a trench in the lower portion of the semiconductor substrate using the patterns as an etch barrier;
두차례의 열처리 공정을 거쳐 상기 트랜치 표면에 열산화막을 형성하는 공정과,Forming a thermal oxide film on the trench surface through two heat treatment processes;
플라즈마 전처리 공정을 실시한 후, 상기 트랜치를 매립하는 제 1 O3-TEOS-oxide막을 형성하는 공정과,Forming a first O 3 -TEOS-oxide film filling the trench after performing a plasma pretreatment step;
CMP공정으로 상기 질화막이 노출될 때까지 연마하여 평탄화하는 공정과,Polishing and planarizing the CNT process until the nitride film is exposed;
상기 질화막을 습식공정으로 제거하여 상기 제 1 O3-TEOS-oxide막과 패드산화막을 노출시키는 공정과,Removing the nitride layer by a wet process to expose the first O 3 -TEOS-oxide layer and the pad oxide layer;
상기 구조의 전표면에 제 2 O3-TEOS-oxide막을 형성하는 공정과,Forming a second O 3 -TEOS-oxide film on the entire surface of the structure;
상기 구조의 전표면에 희생산화막 제거 및 게이트 세정공정을 거쳐 트랜치 소자분리막을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a trench isolation layer on the entire surface of the structure by removing the sacrificial oxide layer and performing a gate cleaning process.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 소자분리막 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a device isolation film manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1h 는 본 발명에 따른 반도체 소자의 소자분리막 제조공정도이다.1A to 1H are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device according to the present invention.
먼저, 반도체 기판(10) 상부에 열산화막인 패드산화막(12)과 질화막(14)을 순차적으로 형성한다.First, the pad oxide film 12 and the nitride film 14, which are thermal oxide films, are sequentially formed on the semiconductor substrate 10.
이때, 상기 패드산화막(12)은 50 ~ 300Å 두께로 형성하고, 상기 질화막(14)은 1000 ~ 3000Å 두께로 형성한다.(도 1a 참조)At this time, the pad oxide film 12 is formed to a thickness of 50 ~ 300Å, the nitride film 14 is formed to a thickness of 1000 ~ 3000Å (see Fig. 1a).
다음, 소자분리용 마스크를 이용하여 상기 반도체 기판(10)이 노출될 때까지 식각하여 질화막(14)패턴과 패드산화막(12)패턴을 형성한다.Next, the semiconductor substrate 10 is etched using the device isolation mask until the semiconductor substrate 10 is exposed to form the nitride layer 14 pattern and the pad oxide layer 12 pattern.
그 다음, 상기 패턴(14, 12)들을 식각장벽으로 이용하여 필드영역의 반도체기판(10) 하부에 일정 깊이의 트랜치(16)를 형성한다.Next, the trenches 14 having a predetermined depth are formed under the semiconductor substrate 10 in the field region by using the patterns 14 and 12 as etch barriers.
이 때, 상기 트랜치(16)는 1500 ~ 4000Å 두께의 깊이로 형성된다.At this time, the trench 16 is formed to a depth of 1500 ~ 4000Å thickness.
다음, 두차례의 열처리 공정을 거쳐 상기 트랜치(16) 측벽 표면에 열산화막(18)을 형성하고 식각한 다음, 재차 열산화막(18)을 형성하고 플라즈마 처리한다.Next, the thermal oxide film 18 is formed and etched on the sidewalls of the trench 16 through two heat treatment processes, and then the thermal oxide film 18 is formed and plasma-treated.
이때, 두차례의 열처리 공정을 거쳐 형성되는 상기 열처리막(18)은 50 ~ 200Å 두께 정도로 형성한다.(도 1c 참조)At this time, the heat treatment film 18 formed through two heat treatment processes is formed to a thickness of 50 ~ 200Åm (see Fig. 1c).
그 다음, 플라즈마 전처리 공정을 실시한 후 상기 트랜치(16)를 메우는 일정 두께의 제 1 O3-TEOS-oxide막(20)을 형성한다.Next, after the plasma pretreatment process is performed, a first O 3 -TEOS-oxide film 20 having a predetermined thickness filling the trench 16 is formed.
이 때, 상기 제 1 O3-TEOS-oxide막(20)은 3000 ~ 8000Å 두께 정도로 형성하는데, 상기 질화막(14)의 전표면을 더을 정도의 두께로 형성한다.(도 1d 참조)At this time, the first O 3 -TEOS-oxide film 20 is formed to a thickness of 3000 ~ 8000 Å, the entire surface of the nitride film 14 is formed to a thickness of more than (see Fig. 1d).
다음, 상기 구조의 전표면에 CMP공정으로 상기 질화막(14)이 노출될때 까지 연마하여 평탄화한다.(도 1e 참조)Next, the entire surface of the structure is polished and planarized by the CMP process until the nitride film 14 is exposed (see FIG. 1E).
그 다음, 상기 질화막(14)을 습식공정으로 제거하여 필드영역에는 상기 제 1 O3-TEOS-oxide막(20)을 노출시키고, 액티브영역에는 상기 패드산화막(12)을 노출시킨다.(도 1f 참조)The nitride film 14 is then removed by a wet process to expose the first O 3 -TEOS-oxide film 20 in the field region and the pad oxide film 12 in the active region. Reference)
다음, 상기 구조의 전표면에 200 ~ 500Å 두께 정도의 제 2 O3-TEOS-oxide막(22)을 형성한다.Next, a second O 3 -TEOS-oxide film 22 having a thickness of about 200 to 500 Å is formed on the entire surface of the structure.
여기서, 재증착되는 상기 제 2 O3-TEOS-oxide막(22) 형성시 플라즈마 전처리 공정을 실시하지 않는다.In this case, the plasma pretreatment process is not performed when the second O 3 -TEOS-oxide layer 22 is re-deposited.
이때, 액티브영역의 상기 패드산화막(12) 상부에는 제 2 O3-TEOS-oxide막(22)이 상대적으로 적게 증착된다.(도 1g 참조)At this time, relatively little second O 3 -TEOS-oxide layer 22 is deposited on the pad oxide layer 12 in the active region (see FIG. 1G).
그 다음, 상기 구조의 전표면에 희생산화막 제거 공정과 게이트 세정공정, 게이트산화공정을 거쳐 상기 필드영역에 트랜치(16) 소자분리막을 형성한다.A trench 16 device isolation layer is then formed in the field region through the sacrificial oxide removal process, the gate cleaning process, and the gate oxidation process on the entire surface of the structure.
이때, 상기 트랜치(16)의 필드영역에 형성된 절연막인 제 2 O3-TEOS-oxide막(22)은 액티브영역 보다 높게 형성되어 트랜치 모서리 부분에서의 전기장 집중에 의한 누설전류를 억제할 수 있게 된다.(도 1h 참조)At this time, the second O 3 -TEOS-oxide layer 22, which is an insulating layer formed in the field region of the trench 16, is formed higher than the active region, thereby suppressing leakage current due to electric field concentration at the trench edge portion. (See Figure 1H)
상기한 바와같이 본 발명에 따르면, 트랜치가 형성되는 반도체 기판 하부의 필드영역에 절연막으로 O3-TEOS-oxide막을 액티브영역 보다 높게 형성함으로써 트랜치 모서리 부분에서의 씨닝(thinning)현상을 방지하고, 액티브영역의 모서리 부근에서의 전기장이 집중되어 발생하는 전기적 특성 열화를 방지하여 소자의 전기적 특성을 향상시키는 이점이 있다.As described above, according to the present invention, by forming an O 3 -TEOS-oxide film higher than the active region as an insulating layer in the field region under the semiconductor substrate where the trench is formed, it is possible to prevent thinning at the edge of the trench and to There is an advantage to improve the electrical characteristics of the device by preventing the deterioration of electrical characteristics caused by the concentration of the electric field near the edge of the region.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970028687A KR100444310B1 (en) | 1997-06-28 | 1997-06-28 | Method for manufacturing isolation layer of semiconductor device preventing thinning at trench top corner using double o3-teos layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970028687A KR100444310B1 (en) | 1997-06-28 | 1997-06-28 | Method for manufacturing isolation layer of semiconductor device preventing thinning at trench top corner using double o3-teos layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990004560A true KR19990004560A (en) | 1999-01-15 |
| KR100444310B1 KR100444310B1 (en) | 2004-11-06 |
Family
ID=37362219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970028687A KR100444310B1 (en) | 1997-06-28 | 1997-06-28 | Method for manufacturing isolation layer of semiconductor device preventing thinning at trench top corner using double o3-teos layer |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100444310B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100446286B1 (en) * | 1997-10-22 | 2004-10-14 | 삼성전자주식회사 | Trench isolation method of semiconductor device for improving uniformity of planarization process |
| KR100842904B1 (en) * | 2005-09-30 | 2008-07-02 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
| US5387540A (en) * | 1993-09-30 | 1995-02-07 | Motorola Inc. | Method of forming trench isolation structure in an integrated circuit |
| JPH0897277A (en) * | 1994-09-29 | 1996-04-12 | Toshiba Corp | Manufacture of semiconductor device |
| US5731241A (en) * | 1997-05-15 | 1998-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned sacrificial oxide for shallow trench isolation |
-
1997
- 1997-06-28 KR KR1019970028687A patent/KR100444310B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100446286B1 (en) * | 1997-10-22 | 2004-10-14 | 삼성전자주식회사 | Trench isolation method of semiconductor device for improving uniformity of planarization process |
| KR100842904B1 (en) * | 2005-09-30 | 2008-07-02 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100444310B1 (en) | 2004-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20040023297A (en) | Semiconductor device having a SiN etch stopper by low temperature ALD and fabricating method the same | |
| US7049225B2 (en) | Method for manufacturing vias between conductive patterns utilizing etching mask patterns formed on the conductive patterns | |
| KR100444310B1 (en) | Method for manufacturing isolation layer of semiconductor device preventing thinning at trench top corner using double o3-teos layer | |
| KR20010036818A (en) | Method for forming a T-shaped trench isolation | |
| KR100500439B1 (en) | method for fabricating semiconductor device with gate spacer of positive slope | |
| KR100256821B1 (en) | Manufacture of semiconductor device | |
| KR19990003056A (en) | Device Separation Method of Semiconductor Device | |
| KR100420701B1 (en) | Method of forming an isolation film in semiconductor device | |
| KR100390838B1 (en) | Method for forming landing plug contact in semiconductor device | |
| US7199013B2 (en) | Semiconductor device and method for fabricating the same | |
| KR100296688B1 (en) | Method for planarizing semiconductor device | |
| KR100235971B1 (en) | Method of manufacturing semiconductor device | |
| KR19990006018A (en) | Method of forming device isolation film of semiconductor device | |
| KR20030001808A (en) | Method for Forming Fuse layer in Semiconductor Device | |
| KR20000033701A (en) | Method for manufacturing semiconductor device comprising flattening process when shallow trench isolation is formed | |
| KR20040061097A (en) | Fabricating method of semiconductor device | |
| KR20010056884A (en) | Method for forming bit line contact of semiconductor | |
| KR100226735B1 (en) | Method of forming a device isolation film of semiconductor device | |
| KR100578239B1 (en) | Method of forming shallow trench isolation layer in semiconductor device | |
| KR100379507B1 (en) | Method for Fabricating of Semiconductor Device | |
| KR20030044363A (en) | Method for planation of Semiconductor Device | |
| KR20040043931A (en) | Method of forming interlayer dielectric layer in semiconductor device | |
| KR20020087557A (en) | Method of forming a floating gate in a flash memory cell | |
| KR20000074388A (en) | Method for forming trench isolation | |
| KR20030018746A (en) | Method for forming metal wiring of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100726 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |