KR100296688B1 - Method for planarizing semiconductor device - Google Patents

Method for planarizing semiconductor device Download PDF

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KR100296688B1
KR100296688B1 KR1019970026834A KR19970026834A KR100296688B1 KR 100296688 B1 KR100296688 B1 KR 100296688B1 KR 1019970026834 A KR1019970026834 A KR 1019970026834A KR 19970026834 A KR19970026834 A KR 19970026834A KR 100296688 B1 KR100296688 B1 KR 100296688B1
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film
teos
peripheral circuit
bpsg
circuit portion
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KR1019970026834A
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Korean (ko)
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KR19990003043A (en
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오찬권
남철우
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Abstract

PURPOSE: A method for planarizing a semiconductor device is provided to prevent a reverse step coverage phenomenon by performing a planarizing process using a CMP process after applying a polishing stop layer of a PE-TEOS(Plasma Enhanced-Tetra Ethyl Ortho Silicate) to a step coverage portion between a cell portion and a peripheral circuit portion . CONSTITUTION: A BPSG(Boron Phosphorus Silicate Glass) layer(16) is formed on a semiconductor substrate(12) comprising a cell portion and a peripheral circuit portion. A PE-TEOS layer is formed on the BPSG layer. The resultant structure is planarized by a CMP process, wherein after exposing the BPSG layer of the cell portion, a polishing speed at the peripheral circuit portion having a low step coverage is reduced due to a PE-TEOS layer, thereby polishing uniformly the cell portion and the peripheral circuit portion. The BPSG layer is deposited in the thickness of 8000-30000Å. The PE-TEOS layer have 1/3-1/5 of a polishing selectivity with regard to the BPSG layer.

Description

반도체소자의 평탄화방법Planarization method of semiconductor device

본 발명은 반도체소자의 평탄화방법에 관한 것으로, 특히 웨이퍼 전 표면에 층간절연막 보다 연마속도가 느린 PE-TEOS를 연마정지층으로 증착하여 셀부와 주변회로부간의 역단차 현상을 방지하고, 소자의 특성을 향상시키는 기술에 관한 것이다.The present invention relates to a planarization method of a semiconductor device, and in particular, PE-TEOS, which is slower than an interlayer insulating film, is deposited on the entire surface of a wafer as a polishing stop layer to prevent the reverse step phenomenon between the cell portion and the peripheral circuit portion, and to improve the characteristics of the device. It is about a technique to improve.

일반적으로 반도체소자는 트랜지스터나 캐패시터 등과 같은 소자들이 형성되는 활성영역과, 상기 소자들의 동작이 서로 방해되지 않도록 활성영역들을 분리하는 소자분리 영역으로 구성되어 있다.Generally, a semiconductor device is composed of an active region in which devices such as a transistor or a capacitor are formed, and an isolation region separating the active regions so that the operation of the devices does not interfere with each other.

최근 반도체소자의 고집적화 추세에 따라 반도체소자에서 많은 면적을 차지하는 소자분리 영역의 면적을 감소시키려는 노력이 꾸준히 진행되고 있다.Recently, with the trend toward higher integration of semiconductor devices, efforts have been made to reduce the area of device isolation regions, which occupy a large area in semiconductor devices.

이러한 소자분리 영역의 제조 방법으로는 질화막 패턴을 마스크로 하여 실리콘 반도체기판을 열산화시키는 통상의 로코스(1ocal oxidation of silicon:이하 LOCOS 라 함) 방법이나 , 반도체기판 상부에 적층된 별도의 다결정실리콘층을 열산화시키는 세폭스(SEFOX) 방법 그리고, 반도체 기판에 트랜치를 형성하고 이를 절연물질로 메우는 트렌치 분리등의 방법이 사용되고 있으며, 그 중 LOCOS 방법은 비교적 공정이 간단하여 널리 사용되지만 소자분리 면적이 넓고, 경계면에 버즈빅이 생성되어 기판 스트레스에 의한 격자결함이 발생되는 단점이 있다.As a method of manufacturing the device isolation region, a conventional LOCOS method of thermally oxidizing a silicon semiconductor substrate using a nitride film pattern as a mask, or a separate polycrystalline silicon stacked on top of the semiconductor substrate SEFOX method for thermal oxidation of layers and trench isolation to form trenches in semiconductor substrates and fill them with insulating materials are used. Among them, LOCOS method is widely used because it is relatively simple, This is wide, and there is a drawback that the lattice defects caused by the stress of the substrate is generated by the generation of buzz big on the interface.

상기 LOCOS 필드 산화막의 제조단차가 증가하게 되면, 후속공정에서 진행되는 리소그래피(lithography)공정시 초점심도가 각각의 부분마다 다르게 되어 오초점(defocus)이 발생되고, 결과적으로 반도체기판 상부에 균일한 패턴을 형성하는 것이 불가능하게 된다.If the manufacturing step of the LOCOS field oxide film is increased, the depth of focus is different for each part during the lithography process which is performed in a subsequent process, resulting in defocus, and as a result, a uniform pattern on the upper portion of the semiconductor substrate. It becomes impossible to form

집적도가 낮은 반도체소자는 단차가 작아 별 문제가 되지 않지만, 소자가 고집적화되어 각 층들간의 단차 및 적층되는 막의 수가 증가되면 소자의 제조 공정에서 나칭이나 단선 등의 불량이 발생하게 되며, 이를 방지하기 위하여 적층막들의 상부를 평탄화하는 평탄화 공정이 공정수율 및 소자의 신뢰성에 중요한 영향을 미치게 된다.The low integration semiconductor device is not a problem because the step is small, but if the device is highly integrated and the number of steps between the layers and the number of stacked films is increased, defects such as missing or disconnection may occur in the manufacturing process of the device. For this purpose, the planarization process of planarizing the upper part of the laminated films has an important effect on the process yield and the reliability of the device.

현재 1M DRAM 이상의 소자에서는 다량의 불순물을 함유하여 유동성 이 우수하고, 화학기상증착(chemical vapor deposition, 이하 CVD 라 함)방법으로 형성되어 단차피복성이 우수한 비.피.에스.지.(boro phospho silicate glass, 이하 BPSG 라 함)나 O3-TEOS 산화막 등을 평탄화막으로 널리 사용하고 있다. 그러나, 상기 평탄화막들은 상대적으로 좁은 평탄화는 가능하게 하나, 셀부 및 주변회로부와 같은 넓은 평탄화에는 한계가 있다.Currently, more than 1M DRAM devices contain a large amount of impurities and have excellent fluidity and are formed by chemical vapor deposition (hereinafter referred to as CVD). silicate glass (hereinafter referred to as BPSG) or O 3 -TEOS oxide is widely used as a planarization film. However, the planarization films allow relatively narrow planarization, but are limited in wide planarization such as cell portions and peripheral circuit portions.

이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 평탄화방법을 자세히 설명하기로 한다.Hereinafter, a planarization method of a semiconductor device according to the related art will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 평탄화방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a planarization method of a semiconductor device according to the prior art.

먼저, 반도체기판(11) 상부에 게이트전극 등의 하부구조물을 형성하고, 하부절연막(13)을 증착하여 평탄화시킨 후, 상기 하부절연막(13) 상부에 전하저장전극 등의 소자를 형성한다.First, a lower structure such as a gate electrode is formed on the semiconductor substrate 11, a lower insulating layer 13 is deposited and planarized, and an element such as a charge storage electrode is formed on the lower insulating layer 13.

그리고, 전체표면 상부에 층간절연막(15)인 BPSG 를 증착한다. 이때, 소자들이 형성되어 있는 셀부와 주변회로부에 단차가 발생한다.(도 1a)Then, BPSG, which is an interlayer insulating film 15, is deposited on the entire surface. At this time, a step occurs in the cell portion where the elements are formed and the peripheral circuit portion (FIG. 1A).

그 후, 종래의 일반적인 CMP방법을 적용하여 단차를 제거하는 공정을 실시한다.Thereafter, a step of removing a step is performed by applying a conventional CMP method.

그러나, 상기 셀부분과 주변회로부분의 단차는 제거되지 않는다.(도 1b)However, the step between the cell portion and the peripheral circuit portion is not removed (Fig. 1B).

그래서, 이에 대한 보완 방법으로 상기와 같은 방법으로 형성된 하부절연막(13) 상부에 층간절연막(15)을 증착한 후, 연마 정지층인 질화막(17)으로 Si3N4및 SiON 박막을 전면에 증착하거나, 마스크를 사용하여 주변회로부에만 질화막을 남긴 후 평탄화 공정을 실시하는 방법이 활성화되었다.(도 1c)Thus, after the interlayer insulating film 15 is deposited on the lower insulating film 13 formed as described above, the Si 3 N 4 and SiON thin films are deposited on the entire surface of the nitride film 17 as a polishing stop layer. Alternatively, a method of performing a planarization process after leaving a nitride film only in the peripheral circuit portion by using a mask was activated (FIG. 1C).

그러나, 상기 연마 정지층인 질화막(17)의 연마속도는 층간절연막(13)인 BPSG에 비해 1/5 내지 1/10 정도 낮기 때문에 셀부에 주변회로부에 비해 더욱 많이 연마되어 역단차 현상이 발생하므로 상기 BPSG가 층간절연 능력을 잃게 될 수도 있다.However, since the polishing rate of the nitride film 17, which is the polishing stop layer, is about 1/5 to 1/10 lower than that of the BPSG, the interlayer insulating film 13, the polishing step is more polished than the peripheral circuit part. The BPSG may lose interlayer insulation capability.

또한, 상기 연마 정지층인 질화막(17)은 연마공정후 질화막이 잔류하고 질화막성 구형의 파티클(particle)이 증가하는 경향이 있기 때문에, HF 증기로 세정을 하는 공정과, 평탄화 공정후 잔존하는 연마 정지층(17) 제거공정이 추가되어 공정이 복잡하고 소자의 특성이 악화되는 문제점이 발생한다.(도 1d)In addition, since the nitride film 17, which is the polishing stop layer, tends to have a nitride film remaining after the polishing process and particles of a nitride film-like sphere, the cleaning process is performed with HF vapor and the polishing remaining after the planarization process. The addition of the stop layer 17 removal process causes a problem that the process is complicated and the characteristics of the device deteriorate (FIG. 1D).

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 셀부와 주변회로부의 단차부분에 새로운 연마 정지층을 적용하여 CMP 공정으로 평탄화 공정을 실시함으로써 역단차 현상을 방지하고, 후속공정을 용이하게 하는 반도체소자의 평탄화방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by applying a new polishing stop layer to the stepped portion of the cell portion and the peripheral circuit portion to perform the planarization process by the CMP process to prevent the reverse step phenomenon, to facilitate the subsequent process It is an object of the present invention to provide a planarization method of a semiconductor device.

도 la 내지 도 1d 는 종래기술의 실시예에 따른 반도체소자의 평탄화방법을 나타낸 단면도.La to 1d are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with an embodiment of the prior art;

도 2a 및 도 2b 는 본 발명의 제1실시예에 따른 반도체소자의 화학적 기계적 평탄화 방법을 나타낸 단면도.2A and 2B are cross-sectional views illustrating a chemical mechanical planarization method of a semiconductor device in accordance with a first embodiment of the present invention.

도 3a 및 도 3b 는 본 발명의 제2실시예에 따른 반도체소자의 화학적 기계적 평탄화 방법을 나타낸 단면도.3A and 3B are cross-sectional views illustrating a chemical mechanical planarization method of a semiconductor device in accordance with a second embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11,12 : 반도체기판 13,14 : 하부절연막11,12 semiconductor substrate 13,14 lower insulating film

15,16 : 층간절연막 17 : 연마 정지층인 질화막15,16: interlayer insulating film 17: nitride film as polishing stop layer

18 : PE-TEOS 막18: PE-TEOS membrane

이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 평탄화 방법은, 소정의 하부 구조물이 구비되는 셀부와 주면희로부로 구성되는 반도체기판 상부에 BPSG막을 형성하는 공정과, 상기 BPSG막 상부에 PE-TEOS막을 형성하는 공정과, 상기 구조를 화학적 기계적 연마방법으로 평탄화시키되, 상기 화학적 기계적 연마방법 중에 셀부의 BPSG막이 노출된 후 단차가 낮은 주변 회로부의 PE-TEOS막에 의해 상기 주변회로부에서의 연마속도를 감소시켜 셀부와 주변회로부를 평탄화시키는 공정을 포함하는 것을 제1특징으로 한다.According to an aspect of the present invention, there is provided a planarization method of a semiconductor device, including: forming a BPSG film on an upper surface of a semiconductor substrate including a cell portion and a main surface roughness portion having a predetermined lower structure; and PE-TEOS on the BPSG film. The process of forming a film and planarizing the structure by a chemical mechanical polishing method, wherein during the chemical mechanical polishing method, the BPSG film of the cell portion is exposed, and then the polishing rate of the peripheral circuit portion is reduced by the PE-TEOS film having a low stepped peripheral circuit portion. A first feature is to include a process of reducing the planarization of the cell portion and the peripheral circuit portion by reducing it.

또한, 이상의 목적을 달성하기 위한 반도체소자의 평탄화방법은, 소정의 하부 구조물이 구비되는 셀부와 주면회로부로 구성되는 반도체기판 상부에 BPSG막을 형성하는 공정과, 상기 BPSG막 상부에 PE-TEOS막을 형성하는 공정과, 상기 셀부를 노출시키는 셀마스크를 식각마스크로 상기 PE-TEOS막을 식각하여 상기 셀부보다 연마 속도가 빠른 상기 주변회로부 상에 PE-TEOS막패턴을 형성하는 공정과, 상기 구조를 화학적 기계적 연마방법으로 평탄화시키되, 상기 화학적 기계적 연마방법 중에 셀부의 BPSG막이 노출된 후 단차가 낮은 주변 회로부의 PE-TEOS막에 의해 상기 주변회로부에서의 연마속도를 감소시켜 셀부와 주변회로부를 평탄화시키는 공정을 포함하는 것을 제2특징으로 한다.In addition, the planarization method of the semiconductor device for achieving the above object is a step of forming a BPSG film on the upper surface of the semiconductor substrate consisting of a cell portion and a main circuit portion provided with a predetermined lower structure, and a PE-TEOS film formed on the BPSG film Forming a PE-TEOS film pattern on the peripheral circuit part having a polishing rate higher than that of the cell part by etching the PE-TEOS film by using a cell mask that exposes the cell part as an etch mask; Flattening by a polishing method, but after the BPSG film of the cell part is exposed during the chemical mechanical polishing method, the step of reducing the polishing rate in the peripheral circuit part by the PE-TEOS film of the peripheral circuit part having a low step is used to planarize the cell part and the peripheral circuit part. It is set as the 2nd characteristic to include.

한편, 이상의 목적을 달성하기위한 본 발명의 원리는, 층간절연막으로 BPSG 를 증착한 후, 연마 속도가 느린 Si3N4및 SiON 박막과 같은 질화막 대신에, 상기 BPSG 보다 연마 속도가 1/3 내지 1/5 정도 느린 PE-TEOS 산화막을 전면 또는 선택적으로 형성함으로써 상기 질화막을 적용하여 발생하는 역단차 현상을 방지하고, 파티클이 발생하는 원인을 근본적으로 방지하며, 평탄화 공정후 잔류하는 상기 PE-TEOS 막을 제거하지 않아도 하부의 BPSG와 같은 산화막이기 때문에 후속 공정의 진행을 용이하게 하는 것이다.On the other hand, the principle of the present invention for achieving the above object, after depositing the BPSG with an interlayer insulating film, instead of the nitride film such as Si 3 N 4 and SiON thin film having a slow polishing rate, the polishing rate is 1/3 to 1/3 than the BPSG Forming a 1/5 slow PE-TEOS oxide film as a whole or selectively to prevent reverse step phenomenon caused by applying the nitride film, fundamentally preventing the occurrence of particles, and the PE-TEOS remaining after the planarization process Even if the film is not removed, it is an oxide film such as the lower BPSG, thereby facilitating the subsequent process.

이하, 본 발명에 따른 반도체소자의 평탄화방법에 관하여 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a planarization method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 및 도 2b 는 본 발명의 제1실시예에 따른 반도체소자의 평탄화방법을 나타낸 단면도이다.2A and 2B are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with a first embodiment of the present invention.

먼저, 반도체기판(12) 상에 여러가지 크기와 형태를 가지는 하부구조물들을 형성하고, 상기 구조의 전 표면에 하부절연막(14)을 증착하여 평탄화시킨 다음, 전하저장전극 등의 구조물을 형성한다.First, lower structures having various sizes and shapes are formed on the semiconductor substrate 12, and the lower insulating layer 14 is deposited on the entire surface of the structure to planarize, and then a structure such as a charge storage electrode is formed.

그다음, 전표면 상부에 층간절연막(16)을 증착한다. 이때, 상기 층간절연막(16)은 산화막 재질의 BPSG를 사용하여 상기 하부구조물들에 의해 생긴 단차를 완화시키기 위해, 셀부 및 주면회로부에 8000 ∼ 30000 Å정도의 두께로 전면에 증착한다.Then, an interlayer insulating film 16 is deposited over the entire surface. In this case, the interlayer insulating layer 16 is deposited on the front surface of the cell portion and the main circuit portion with a thickness of about 8000 to 30000 mW to alleviate the step caused by the lower structures using BPSG made of an oxide film.

다음, 상기 층간절연막(16) 상부에 BPSG에 대한 연마 선택비가 1/3 내지 1/5 정도인 PE-TEOS(18) 막을 연마방지막으로500 ∼ 5000 Å 정도 두께 증착한다.(도 2a)Next, a PE-TEOS 18 film having a polishing selectivity of 1/3 to 1/5 with respect to BPSG is deposited on the interlayer insulating film 16 with a thickness of 500 to 5000 kPa as an anti-polishing film (FIG. 2A).

여기서, 상기 PE-TEOS(18) 막 대신에 엘피-티이오에스(Low Press-Tetra Ethyl Ortho Silicate : LP-TEOS), 오존-TEOS, 에이치디피-유에스지(High Density Plasma-Undoped Silicate Glass : HDP-USG), PE-SiH4및 에이피엘(Advanced Planaraization Layer : APL) 산화막의 USG계열 산화막 중 하나로 형성할 수 있다.Here, instead of the PE-TEOS (18) film, LP-TEOS (Low Press-Tetra Ethyl Ortho Silicate: LP-TEOS), ozone-TEOS, H.D.P-High Density Plasma-Undoped Silicate Glass (HDP-) USG), PE-SiH 4 and APL (Advanced Planaraization Layer: APL) oxide film of one of the USG-based oxide film can be formed.

그 다음, CMP 공정을 실시하여 상기 PE-TEOS(18) 및 층간절연막(16)을 연마하여 평탄화한다.Then, the PE-TEOS 18 and the interlayer insulating film 16 are polished and planarized by performing a CMP process.

여기서, 상기 CMP 공정시 사용되는 슬러리는 산화막 연마용 슬러리로서 pH l0 ∼ 11 정도의 염기성을 갖으며, 100 ∼ 200 nm 정도 크기의 실리카 입자가 현탁된 것이다.Here, the slurry used in the CMP process has a basic pH of about 11 to 11 as an oxide film polishing slurry, and silica particles having a size of about 100 to 200 nm are suspended.

예를 들면 셀부와 주변회로부간의 단차가 10000Å일 경우, 상기 층간절연막(16)을 15000Å의 두께로 그리고 상기 PE-TEOS(18)를 800Å의 두께로 증착한 후, 상기 PE-TEOS(18) 및 층간절연막(16)을 CMP 공정으로 93초 동안 연마하여 평탄화한다.(도 2b)For example, when the step between the cell portion and the peripheral circuit portion is 10000 kPa, the interlayer insulating film 16 is deposited to a thickness of 15000 kPa and the PE-TEOS 18 is deposited to a thickness of 800 kPa, and then the PE-TEOS 18 and The interlayer insulating film 16 is polished and planarized for 93 seconds by the CMP process (FIG. 2B).

도 3a 및 도 3b 는 본 발명의 제2실시예에 따른 반도체소자의 평탄화방법을 나타낸 단면도이다.3A and 3B are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with a second embodiment of the present invention.

먼저, 반도체기판(12) 상에 여러가지 크기와 형태를 가지는 하부구조물들을 형성하고, 상기 구조의 전 표면에 하부절연막(14)을 증착하여 평탄화시킨 다음, 전하저장전극 등의 구조물을 형성한다.First, lower structures having various sizes and shapes are formed on the semiconductor substrate 12, and the lower insulating layer 14 is deposited on the entire surface of the structure to planarize, and then a structure such as a charge storage electrode is formed.

그다음, 전표면 상부에 층간절연막(16)을 증착한다. 이때, 상기 층간 절연막(16)은 산화막 재질의 BPSG 를 사용하여 상기 하부구조물들에 의해 생긴 단차를 완화시키기 위해, 셀부 및 주변회로부에 8000 ∼ 30000Å 두께를 전면적으로 증착한다.Then, an interlayer insulating film 16 is deposited over the entire surface. At this time, the interlayer insulating film 16 is deposited on the cell portion and the peripheral circuit portion 8000 ~ 30000 Å in thickness in order to alleviate the step caused by the lower structures using the BPSG oxide material.

다음, 상기 층간절연막(16) 상부에 산화막에 대한 연마 선택비가 1/3 내지 1/5 정도인 PE-TEOS(18) 막을 500 ∼ 5000 Å 두께로 전면적으로 증착한다.Next, a PE-TEOS 18 film having a polishing selectivity of about 1/3 to 1/5 with respect to an oxide film is deposited on the interlayer insulating film 16 to a thickness of 500 to 5000 Å.

여기서, 상기 PE-TEOS(18) 막 대신에 LP-TEOS, 오존-TEOS, HDP-USG, PE-SiH4및 APL 산화막으로 이루어지는 USG계열 산화막 중 하나로 형성할 수 있다.Instead of the PE-TEOS 18 film, it may be formed of one of the USG-based oxide films including LP-TEOS, ozone-TEOS, HDP-USG, PE-SiH 4, and APL oxide films.

그 다음, 상기 PE-TEOS (18) 상부에 감광막(도시안됨)을 코팅한다.Next, a photoresist (not shown) is coated on the PE-TEOS 18.

여기서, 상기 감광막은 음성 또는 양성 감광막을 사용하여 0.6 ∼ 10 μm 정도의 두께로 형성한다.Here, the photosensitive film is formed to a thickness of about 0.6 to 10 μm using a negative or positive photosensitive film.

그리고, 상기 감광막이 형성된 반도체기판(12)을 소프트 베이크한다.Then, the semiconductor substrate 12 on which the photosensitive film is formed is soft baked.

이때, 상기 소프트 베이크 공정은 대류 오븐, 이동벨트 아이.알.(IR) 오븐, 초고주파 오븐 또는 전도벨트 오븐을 사용하여 50 ∼ 90 ℃ 정도의 온도에서 1 ∼ 30 분 정도 실시한다.At this time, the soft bake process is performed at a temperature of about 50 to 90 ° C. for about 1 to 30 minutes using a convection oven, a moving belt I. (IR) oven, an microwave oven, or a conductive belt oven.

그 후, 상기 감광막을 주변회로부에만 선택적으로 형성하기 위해서 노광 및 현상 공정을 실시하여 감광막 패턴을 형성한다. 이때, 상기 노광 공정은 아이-라인(i-line, 이하 'i-라인' 이라 함), 지-라인(g-line, 이하 'g-라인' 이라 함), 원자외선(deep ultra violet, DUV), 이-빔(E-beam) 또는 엑스선(X-ray) 등의 노출 시스템을 이용하여 실시한다.Thereafter, in order to selectively form the photoresist film only in the peripheral circuit portion, exposure and development processes are performed to form a photoresist pattern. In this case, the exposure process is an i-line (i-line, hereinafter 'i-line'), G-line (g-line, hereinafter 'g-line'), deep ultra violet (DUV) ), Using an exposure system such as an E-beam or X-ray.

그리고, 상기 감광막 패턴을 식각마스크로 사용하여 셀부에 증착되어 있는 상기 PE-TEOS(18)를 제거한다. 이때, 상기 식각공정은 습식식각, 플라즈마 에칭, 이온빔 밀링 또는 반응성 이온 에치빔 방법을 사용하여 실시한다.(도 3a)The PE-TEOS 18 deposited on the cell portion is removed using the photoresist pattern as an etching mask. At this time, the etching process is performed using a wet etching, plasma etching, ion beam milling or reactive ion etch beam method (Fig. 3a).

그 다음, CMP 공정을 실시하여 상기 PE-TEOS (18) 및 층간절연막(16)을 연마하여 평탄화한다. 여기서, 상기 CMP 공정 시 사용되는 슬러리는 산화막 연마용 슬러리로서 pH l0 ∼ 11 의 염기성을 갖으며, 100 ∼ 200 nm 크기의 실리카 입자가 현탁된 것이다.Next, the PE-TEOS 18 and the interlayer insulating film 16 are polished and planarized by performing a CMP process. Here, the slurry used in the CMP process has a basic pH of 11 to 11 as an oxide film polishing slurry, and silica particles having a size of 100 to 200 nm are suspended.

예를 들면 셀부와 주변회로부간의 단차가 10000Å일 경우, 상기 층간절연막(16)을 15000Å의 두께로 그리고 상기 PE-TEOS(18)를 800Å의 두께로 증착한 후, 상기 PE-TEOS(18) 및 층간절연막(16)을 CMP 공정으로 93초 동안 연마하여 평탄화한다.(도 3b)For example, when the step between the cell portion and the peripheral circuit portion is 10000 kPa, the interlayer insulating film 16 is deposited to a thickness of 15000 kPa and the PE-TEOS 18 is deposited to a thickness of 800 kPa, and then the PE-TEOS 18 and The interlayer insulating film 16 is polished and planarized for 93 seconds by the CMP process (FIG. 3B).

상기한 바와 같이 본 발명에 따른 반도체소자의 평탄화방법은, 트랜지스터, 캐패시터, 비트라인 및 금속배선 등이 밀집되어 있는 셀 부와 주변회로부로 구성되는 반도체기판 상부에 층간절연막으로 BPSG막을 증착하고, 상기 BPSG막 상부에 PE-TEOS막을 전면적 또는 평탄화 대상층에 선택적으로 증착한 후 CMP공정을 실시함으로써 상기 셀부와 주변회로부에 발생하는 단차를 제거하고 그에 따른 반도체소자의 공정 수율 및 소자동작의 신뢰성을 향상시키는 이점이 있다.As described above, in the planarization method of a semiconductor device according to the present invention, a BPSG film is deposited as an interlayer insulating film on an upper surface of a semiconductor substrate including a cell portion and a peripheral circuit portion in which transistors, capacitors, bit lines, and metal wirings are densely formed. By selectively depositing the PE-TEOS film on the entire surface or the planarization target layer on the BPSG film and then performing the CMP process, the step difference generated in the cell part and the peripheral circuit part is eliminated, thereby improving the process yield and reliability of the device operation. There is an advantage.

Claims (8)

(2차 정정)소정의 하부 구조물이 구비되는 셀부와 주변회로부로 구성되는 반도체기판 상부에 BPSG막을 형성하는 공정과, 상기 BPSG막 상부에 PE-TEOS막을 형성하는 공정과, 상기 구조를 화학적 기계적 연마방법으로 평탄화시키되, 상기 화학적 기계적 연마방법 중에 셀부의 BPSG막이 노출된 후 단차가 낮은 주변회로부의 PE-TEOS막에 의해 상기 주변회로부에서의 연마속도를 감소시켜 셀부와 주변회로부를 평탄화시키는 공정을 포함하는 반도체소자의 평탄화방법.(Secondary correction) forming a BPSG film on an upper part of a semiconductor substrate including a cell part and a peripheral circuit part having a predetermined lower structure, forming a PE-TEOS film on the BPSG film, and chemically mechanical polishing the structure. Flattening by the method, and during the chemical mechanical polishing method, after the BPSG film of the cell portion is exposed, the PE-TEOS film of the peripheral circuit portion having a low step is reduced to reduce the polishing rate in the peripheral circuit portion to planarize the cell portion and the peripheral circuit portion. A planarization method of a semiconductor device. (2차 정정)청구항 1 에 있어서, 상기 BPSG막은 8000∼30000Å두께로 증착하는 것을 특징으로 하는 반도체소자의 평탄화방법.(Secondary correction) The method of claim 1, wherein the BPSG film is deposited at a thickness of 8000 to 30000 kPa. (2차 정정)청구항 1 에 있어서, 상기 PE-TEOS막은 상기 BPSG막에 대한 연마 선택비가 1/3 내지 1/5이고, 상기 PE-TEOS막 대신 LP-TEOS막, 오존-TEOS막, HDP-USG막, PE-SiH4막 및 APL 산화막으로 이루어지는 USG계열 산화막 중 하나를 이용하여 500 ∼ 5000 Å 두께로 형성함을 특징으로 하는 반도체소자의 평탄화 방법.(Secondary correction) The method of claim 1, wherein the PE-TEOS film has a polishing selectivity of 1/3 to 1/5 with respect to the BPSG film, and instead of the PE-TEOS film, an LP-TEOS film, an ozone-TEOS film, and an HDP- film. A method of planarizing a semiconductor device, characterized in that it is formed to a thickness of 500 to 5000 mm using one of a USG series oxide film composed of a USG film, a PE-SiH 4 film, and an APL oxide film. (2차 정정)청구항 1 에 있어서, 상기 화학적 기계적 연마방법은 pH가 10∼11이고, 100 ∼ 150nm의 실리카 입자가 탈이온수와 혼합된 산화막 평탄화용 슬러리를 사용하는 것을 특징으로 하는 반도체소자의 평탄화 방법.(Secondary correction) The method of claim 1, wherein the chemical mechanical polishing method uses a slurry for planarizing an oxide film having a pH of 10 to 11 and silica particles of 100 to 150 nm mixed with deionized water. Way. (2차 정정)소정의 하부 구조물이 구비되는 셀부와 주변회로부로 구성되는 반도체기판 상부에 BPSG막을 형성하는 공정과, 상기 BPSG막 상부에 PE-TEOS막을 형성하는 공정과, 상기 셀부를 노출시키는 셀마스크를 식각마스크로 상기 PE-TEOS막을 식각하여 상기 셀부보다 연마 속도가 빠른 상기 주변회로부 상에 PE-TEOS막패턴을 형성하는 공정과, 상기 구조를 화학적 기계적 연마방법으로 평탄화시키되, 상기 화학적 기계적 연마방법 중에 셀부의 BPSG막이 노출된 후 단차가 낮은 주변회로부의 PE-TEOS막에 의해 상기 주변회로부에서의 연마속도를 감소시켜 셀부와 주변회로부를 평탄화시키는 공정을 포함하는 반도체소자의 평탄화방법.(Secondary correction) forming a BPSG film on an upper portion of a semiconductor substrate including a cell portion having a predetermined lower structure and a peripheral circuit portion, forming a PE-TEOS film on the BPSG film, and exposing the cell portion Etching the PE-TEOS film using an etch mask to form a PE-TEOS film pattern on the peripheral circuit portion having a faster polishing rate than the cell portion, and planarizing the structure by a chemical mechanical polishing method, wherein the chemical mechanical polishing is performed. And flattening the cell portion and the peripheral circuit portion by reducing the polishing rate in the peripheral circuit portion by the PE-TEOS film of the peripheral circuit portion having a low step after the BPSG film of the cell portion is exposed during the method. (2차 정정)청구항 5 에 있어서, 상기 BPSG막은 8000 ∼ 30000 Å 두께로 증착하는 것을 특징으로 하는 반도체소자의 평탄화방법.(Secondary correction) The method of claim 5, wherein the BPSG film is deposited to a thickness of 8000 to 30000 GPa. (2차 정정)청구항 5 에 있어서, 상기 PE-TEOS막은 상기 BPSG막에 대한 연마 선택비가 1/3 내지 1/5이고, 상기 PE-TEOS막 대신 LP-TEOS막, 오존-TEOS막, HDP-USG막, PE-SiH4막 및 APL 산화막으로 이루어지는 USG계열 산화막 중 하나를 이용하여 500 ∼ 5000 Å 두께로 형성함을 특징으로 하는 반도체소자의 평탄화방법.(Secondary correction) The method of claim 5, wherein the PE-TEOS film has a polishing selectivity of 1/3 to 1/5 with respect to the BPSG film, and instead of the PE-TEOS film, an LP-TEOS film, an ozone-TEOS film, and an HDP- film. A method of planarizing a semiconductor device, characterized in that it is formed to a thickness of 500 to 5000 mm by using one of a USG series oxide film composed of a USG film, a PE-SiH 4 film, and an APL oxide film. (2차 정정)청구항 5 에 있어서, 상기 화학적 기계적 연마방법은 pH가 10∼11이고, 100∼150nm의 실리카 입자가 탈 탈이온수와 혼합된 산화막 평탄화용 슬러리를 사용하는 것을 특징으로 하는 반도체소자의 평탄화방법.(Secondary correction) The semiconductor device according to claim 5, wherein the chemical mechanical polishing method uses a slurry for planarizing an oxide film having a pH of 10 to 11 and silica particles of 100 to 150 nm mixed with deionized water. Planarization method.
KR1019970026834A 1997-06-24 1997-06-24 Method for planarizing semiconductor device KR100296688B1 (en)

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