KR0168149B1 - Method of forming flat layer on semiconductor device - Google Patents
Method of forming flat layer on semiconductor device Download PDFInfo
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- KR0168149B1 KR0168149B1 KR1019950010975A KR19950010975A KR0168149B1 KR 0168149 B1 KR0168149 B1 KR 0168149B1 KR 1019950010975 A KR1019950010975 A KR 1019950010975A KR 19950010975 A KR19950010975 A KR 19950010975A KR 0168149 B1 KR0168149 B1 KR 0168149B1
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- planarization layer
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 22
- 230000002093 peripheral effect Effects 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 42
- -1 argon (Ar) Chemical class 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
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- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 평탄화방법에 관한 것으로, 초고집적 반도체 소자의 제조를 위한 사진공정시 단차로 인해 발생되는 촛점의 깊이에 대한 이득의 저하를 방지하기 위하여 평탄화층을 형성한 후 단차비에 따라 이온주입량(Dose)및 이온주입 에너지(Energy)를 조절하여 불순물이온을 주입하므로써 단차 및 소자의 동작속도를 향상시킬 수 있도록 한 반도체 소자의 평탄화방법에 관한 것이다.The present invention relates to a planarization method of a semiconductor device, and to form a planarization layer after forming a planarization layer in order to prevent a decrease in gain of focus depth caused by a step in a photolithography process for manufacturing an ultra-high density semiconductor device. The present invention relates to a planarization method of a semiconductor device in which an impurity ion is implanted by controlling an ion implantation dose and an ion implantation energy to improve a step and an operation speed of the device.
Description
제1a및 제1b도는 종래 반도체 소자의 평탄화방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a planarization method of a conventional semiconductor device.
제2a및 제2b도는 종래 반도체 소자의 평탄화방법을 설명하기 위한 소자의 단면도.2A and 2B are cross-sectional views of a device for explaining a planarization method of a conventional semiconductor device.
제3a 내지 제3c도는 본 발명의 제1실시예를 설명하기 위한 소자의 단면도.3A to 3C are cross-sectional views of devices for explaining the first embodiment of the present invention.
제4a 내지 제4d도는본발명의 제2실시예를 설명하기 위한 소자의 단면도.4A to 4D are cross-sectional views of elements for explaining the second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 도전층패턴1 silicon substrate 2 conductive layer pattern
3 및 5 : 산화막 4 : SOG막3 and 5: oxide film 4: SOG film
3A 및 3B : 절연막 4A 및 4B : 평탄화층3A and 3B: insulating film 4A and 4B: planarization layer
6 : 감광막6: photosensitive film
본 발명은 반도체 소자의 평탄화방법에 관한 것으로, 특히 평탄화층을 형성한 후 단차비에 따라 이온주입량(Dose) 및 이온주입 에너지(Energy)를 조절하여 불순물이온을 주입하므로써 단차 및 소자의 동작속도를 향상시킬 수 있도록 한 반도체 소자의 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device. In particular, after the planarization layer is formed, an impurity ion is implanted by adjusting the amount of implantation and the amount of ion implantation energy according to the step difference ratio, thereby increasing the operation speed of the step and the device. The present invention relates to a planarization method of a semiconductor device that can be improved.
일반적으로 반도체 소자가 고집적화됨에 따라 셀(Cell)지역과 주변(Periphery) 지역간의 단차(Topology)는 더욱 증가되고, 그에 따라 사진 (Photo) 공정시 촛점깊이(Depth of Focus)에 대한 이득(Margin)이 감소되어 소자의 제조에 어려움이 따른다. 더욱이 초고집적 반도체 소자의 제조에 있어서는 해상력(Resolution)을 갖는 장비를 사용하기 때문에 이러한 문제는 더욱 심각해진다. 또한 단차의 발생으로 인하여 내부접속라인 (Interconnection Line Line)의 길이가 증가되어 소자의 동작속도가 저하된다.In general, as semiconductor devices are highly integrated, the topology between the cell and peripheral regions is further increased, thus margining the depth of focus during the photo process. This is reduced resulting in difficulty in fabrication of the device. Moreover, this problem becomes more serious in the manufacture of ultra-high density semiconductor devices because equipment having resolution is used. In addition, due to the generation of a step, the length of the interconnection line is increased, thereby reducing the operation speed of the device.
그러면 종래 반도체 소자의 평탄화방법을 제1a 및 제1b도와 제2a및 제 2b도를 통해 설명하면 다음과 같다.The planarization method of the conventional semiconductor device will now be described with reference to FIGS. 1A and 1B and FIGS. 2A and 2B.
종래에는 제1a도에 도시된 바와같이 셀지역(c)에 소정의 단차를 갖는 도전층패턴(2)이 형성된 실리콘기판(1)을 평탄화시키기 위하여 먼저 전체상부면에 산화막(3)을 형성한 후 SOG(Spin-On-Glass; 4)막을 도포한다. 이후 셀지역(c)과 주변지역(p)간의 단차를 감소시키기 위하여 전면식각공정 으로 상기 SOG막(4)및 산화막(3)을 순차적으로 식각하여 제1b도와 같이 평탄화시키는데, 이때 상기 제1a도에서와 같이 단차가 높은 셀지역(c)의 산화막(3)상에는 SOG막(4)이 얇게 도포되는 반면에, 비교적 단차가 낮은 주변지역(p)의 산화막(3)상에는 SOG막(4)이 두껍게 도포되기 때문에 평탄화 공정후에도 주변지역(p)에는 SOG막(4)이 일부 잔류된다. 그러므로 이와 같은 방법을 이용하면 평탄화후에도 단차가 존재하게 되며, 단차가 낮은 지 역에 잔류되는 SOG막내에 함유된 수분 및 수소의 외부확산(Out diffusion) 으로 인하여 후속 열처리 공정시 소자의 특성에 영향을 미치는 문제점이 발생된다. 그래서 이와같은 문제점을 보완하기 위하여 제2a도와같이 실리콘기판(1)상의 셀지역(c)에 소정의 단차를 갖는 도전층패턴(2)이 형성된 상태에서 전체상부면에 산화막(5)을 두껍게 형성한 후 화학적 기계연마 (Chemical Mechanical Polishing)방법을 이용하여 상기 산화막(5)을 제 2b도와 같이 평탄화시키는 방법을 이용하기도 한다. 그러나 이 방법은 완전한 평탄화를 실현할 수 있는 반면에, 연마시 다량의 파티클(Particle), 긁힘(Scratch)및 갈라짐(Crack)등이 발생되어 소자의 수율을 저하시키는 단점이 있다.Conventionally, in order to planarize the silicon substrate 1 on which the conductive layer pattern 2 having a predetermined step is formed in the cell region c, as shown in FIG. 1A, the oxide film 3 is first formed on the entire upper surface. After the SOG (Spin-On-Glass; 4) film is applied. Thereafter, the SOG film 4 and the oxide film 3 are sequentially etched by the front etching process in order to reduce the step difference between the cell region c and the surrounding region p, and planarized as shown in FIG. As described above, the SOG film 4 is thinly applied on the oxide film 3 in the cell region c having a high step, while the SOG film 4 is deposited on the oxide film 3 in the peripheral region p having a relatively low step. Since the coating is thick, a part of the SOG film 4 remains in the peripheral region p even after the planarization process. Therefore, using this method, there is a step even after planarization, and due to the out diffusion of water and hydrogen contained in the SOG film remaining in the low step area, it affects the characteristics of the device during the subsequent heat treatment process. There is a problem. Therefore, in order to compensate for such a problem, the oxide film 5 is thickly formed on the entire upper surface in the state where the conductive layer pattern 2 having the predetermined step is formed in the cell region c on the silicon substrate 1 as shown in FIG. After that, a method of planarizing the oxide film 5 as shown in FIG. 2B may be used by using chemical mechanical polishing. However, while this method can realize perfect planarization, a large amount of particles, scratches, and cracks are generated during polishing, which lowers the yield of the device.
따라서 본 발명은 평탄화층을 형성한 후 단차비에 따라 이온주입량 및 이온주입 에너지를 조절하여 불순물이온을 주입하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 평탄화방법을 제공하는데 그 목적이 있다. 상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 평탄화방법은 주변지역에 비하여 셀지역의 단차가 높게 형성된 실리콘기판상에 절연막 및 평탄화층을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 평탄화층의 식각비를 조절하기 위하여 전체 상부면에 불순물이온을 주입하는 단계와, 상기 단계로부터 전면식각공정으로 상기 평탄화층 및 절연막을 순차적으로 식각하여 표면을 평탄화시키는 단계로 이루어지는 것을 특징으로 하며, 다른 반도체 소자의 평탄화방법은 주변지역에 비하여 셀지역의 단차가 높게 형성된 실리콘기판상에 절연막 및 평탄화층을 순차적으로 형성하는 단계와, 상기 단계로부터 전체면에 감광막을 도포한 후 소정의 마스크를 이용한 노광 및 현상공정을 실시하여 상기 주변지역의 평탄화층이 노출되도록 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 상기 노출된 평탄화 층의 식각비를 조절하기 위하여 전체 상부면에 불순물이온을 주입하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 제거한 후 전면식각공정으로 상기 평탄화층 및 절연막을 순차적으로 식각하여 표면을 평탄화시키는 단계로 이루어지는 것을 특징으로 한다.Accordingly, an object of the present invention is to provide a planarization method of a semiconductor device capable of solving the above-mentioned disadvantages by implanting impurity ions by adjusting the ion implantation amount and ion implantation energy according to the step difference ratio after forming the planarization layer. According to an aspect of the present invention, there is provided a method of planarizing a semiconductor device, the method including sequentially forming an insulating film and a planarization layer on a silicon substrate having a higher step height of a cell region compared to a peripheral region, and from the step, the planarization layer. Implanting impurity ions into the entire upper surface to control the etching ratio of the semiconductor substrate; and sequentially etching the planarization layer and the insulating layer from the step to the entire surface etching process to planarize the surface of the semiconductor. The planarization method of the device includes the steps of sequentially forming an insulating film and a planarization layer on a silicon substrate having a higher step height in the cell region compared to the surrounding area, and applying a photoresist film to the entire surface from the step, and then using a predetermined mask. The development process is performed to expose the planarization layer in the surrounding area. Patterning the photoresist layer, implanting impurity ions into the entire upper surface to control the etch rate of the exposed planarization layer from the step, and removing the patterned photoresist film from the step and then planarizing the entire surface by the etching process And etching the layer and the insulating film sequentially to planarize the surface.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3a 내지 제3c도는 본발명의 제1실시예를 설명하기 위한 소자의 단면도로서, 제3a도는 셀지역(c)에 소정의 단차를 갖는 도전층패턴(2)이 형성된 실리콘기판(1)상에 절연막(3a)및 평탄화층(4a)을 순차적으로 형성한 상태의 단면도인데, 상기 평탄화층(4a)의 특성에 의해 단차가 높은 셀지역(c)의 절연막(3a)상에는 평탄화층(4a)이 얇게 형성되는 반면에, 비교적 단차가 낮은 주변지역(p)의 절연막(3a)상에는 평탄화층(4a)이 두껍게 형성된다. 여기서 상기 절연막(3a)으로는 산화막을 이용하고 셀지역(c)과 주변지역(p)간의 단차보다 두껍게 형성하며, 상기 평탄화층(4a)은 SOG막을 도포하여 형성한다.3A to 3C are cross-sectional views of the device for explaining the first embodiment of the present invention, and FIG. 3A is a view on the silicon substrate 1 on which the conductive layer pattern 2 having a predetermined step is formed in the cell region c. The insulating film 3a and the planarization layer 4a are formed in the cross-sectional view, and the planarization layer 4a is formed on the insulating film 3a of the cell region c with a high level of difference due to the characteristics of the planarization layer 4a. While the thin film is formed, the planarization layer 4a is thickly formed on the insulating film 3a in the peripheral region p having a relatively low level. In this case, an oxide film is used as the insulating film 3a and is formed thicker than a step between the cell region c and the peripheral region p. The planarization layer 4a is formed by applying an SOG film.
제3b도는 전체 상부면에 아르곤(Ar), 인(P), 비소(As)또는 붕소(B)와 같은 불순물이온을 주입하는 상태의 단면도로서, 이때 이온이 주입된 평탄화층(4a)은 그 구조가 조밀(Dense)해져 식각비가 낮아지는 특성을 이용 하여 단차가 낮은 주변지역(p)의 주입량이 단차가 높은 셀지역(C)의 주입량보다 많도록 이온의양과 이온주입 에너지를 조절한다.3B is a cross-sectional view of implanting impurity ions such as argon (Ar), phosphorus (P), arsenic (As), or boron (B) on the entire upper surface, wherein the planarization layer 4a into which the ions are implanted is By using the dense structure to lower the etch rate, the amount of ions and the ion implantation energy are controlled so that the amount of implantation in the peripheral region (p) having a low level is higher than that of the cell region (C) having a high level of difference.
제3c도는 습식식각방법을 이용한 전면식각으로 상기 평탄화충 (4a)및 절연막(3a)을 순차적으로 식각하여 표면을 평탄화시킨 상태의 단면도인데, 이때 이온주입량이 많은 상기 주변지역(p)의 평탄화층(4a)은 낮은 식각비를 갖기 때문에 주변지역(P)의 평탄화층(4A)이 완전히 제거되는 시점에서는 단차가 없어지게 된다. 또한 이때 건식식각공정을 추가 실시하여 잔류되는 절연막(3A)의 두께를 정확하게 조절할 수 있다.FIG. 3C is a cross-sectional view of the planarization layer 4a and the insulating layer 3a which are sequentially etched by the front etching using a wet etching method to planarize the surface, wherein the planarization layer of the peripheral region p having a large amount of ion implantation Since 4a has a low etching rate, the step is eliminated when the planarization layer 4A of the peripheral area P is completely removed. In addition, by performing a dry etching process, the thickness of the remaining insulating film 3A can be accurately adjusted.
예를들어 상기 셀지역(C)과 주변지역(P)간의 단차가 8000Å인 경우에, 상기 절연막(3a)은 10000Å, 상기 평탄화층(4a)은 4000Å정도의 두께로 각각 형성하며, 이온주입시 상기 평탄화층(4a)이 절연막(3a)보다 약 1/2정도의 식각비를 갖도록 이온주입 에너지와 이온의 량을 조절하고 4000Å의 두께를 타겟(Target)으로 습식식각을 실시한다. 그러면 상기 평탄화층(4a)이 완전히 제거되는 동안 상기 절연막(3a)은 8000Å이 식각되어 셀지역(c)과 주변지역(p)간의 단차가 동일해진다. 또한 여기서 잔류되는 절연막(3a)의 두께를 정착히 조절하기 위해서는 건식식각공정을 추가로 실시하면 된다.For example, when the step between the cell region C and the peripheral region P is 8000 kPa, the insulating film 3a is formed at a thickness of about 10000 kPa and the planarization layer 4a is about 4000 kPa, respectively. Ion implantation energy and the amount of ions are adjusted so that the planarization layer 4a has an etch ratio of about 1/2 of the insulating film 3a, and wet etching is performed with a target of 4000 Å in thickness. Then, while the planarization layer 4a is completely removed, the insulating layer 3a is etched at 8000 Å so that the level difference between the cell region c and the peripheral region p is the same. In addition, a dry etching process may be further performed to fix the thickness of the insulating film 3a remaining therein.
그런데 공정의 진행증에 상기 평탄화충이 매우 얇게 도포되는 경우, 단차가 높은 셀지역의 평탄화층의 두께는 더욱 얇아지기 때문에 전체면에 이온주입을 할 경우 셀지역의 평탄화층은 물론 그 하부의 절연막까지도 이온이 주입되어 식각비가 낮아지게 되므로 정착한 평탄화의 실현이 어려울 수 있다. 그래서 본 발명에서는 이러한 문제점을 보완할 수 있는 평탄화방법을 제2실시예를 통해 설명하고져 한다.However, when the planarizing worm is applied very thinly as the process progresses, the thickness of the planarization layer of the cell region having a high level of difference becomes thinner. Therefore, when ion implantation is performed on the entire surface, not only the planarization layer of the cell region but also the insulating layer underneath it. Since ion is implanted and the etching ratio is lowered, it may be difficult to realize the flattening. Therefore, in the present invention, a planarization method that can compensate for this problem will be described through the second embodiment.
제4a 내지 제4d도는 본발명의 제2실시예를 설명하기 위한 소자의 단면도로서, 제4a도는 셀지역(c)에 소정의 단차를 갖는 도전층패턴(2)이 형성된 실리콘기판(1)상에 절연막(3b) 및 평탄화층(4b)을 순차적으로 형성한 상태의 단면도로서, 여기서 상기 절연막(3a)으로는 산화막을 이용하고 셀지역(c)과 주변지역(p)간의 단차보다 두껍게 형성하며, 상기 평탄화층(4b)은 SOG막을 도포하여 형성하였는데, 셀지역(c)의 평탄화층(4b)이 매우 얇게 도포되어 있는 상태이다.4A to 4D are cross-sectional views of elements for explaining the second embodiment of the present invention. FIG. 4A is a view showing a silicon substrate 1 on which a conductive layer pattern 2 having a predetermined step is formed in a cell region c. A cross-sectional view of the insulating film 3b and the planarization layer 4b sequentially formed thereon, wherein the insulating film 3a is formed of an oxide film and formed thicker than the step between the cell region c and the surrounding region p. The planarization layer 4b is formed by applying an SOG film, and the planarization layer 4b of the cell region c is very thinly coated.
제4b도는 전체면에 감광막(a)을 도포한 후 소정의 마스크를 이웅 한 노광 및 현상공정을 실시하여 상기 주변지역(p)의 평탄화층(4b)이 노출 되도록 상기 감광막(a)을 패터닝한 후 상기 노출된 주변지역(p)의 평탄화층(4b)에 아르곤(Ar), 인(P), 비소(As)또는 붕소(B)와 같은 불순물이온을 주입하는 상태의 단면도로서, 이때 이온이 주입된 주변지역(p)의 평탄화층 (4b)은 그 구조가 조밀해져 식각비가 낮아진다.FIG. 4B shows the photoresist film a being coated on the entire surface and then subjected to an exposure and development process using a predetermined mask to pattern the photoresist film a so that the planarization layer 4b of the peripheral area p is exposed. A cross-sectional view of a state in which impurity ions such as argon (Ar), phosphorus (P), arsenic (As), or boron (B) are implanted into the exposed planarization layer 4b in the exposed peripheral area p. The planarization layer 4b of the implanted peripheral area p has a dense structure, thereby lowering the etching ratio.
제4c도는 상기 감광막(6)을 제거한 상태의 단면도이고, 제4d도는 습식식각방법을 이용한 전면식각으로 상기 평탄화층(4b) 및 절연막(3b)을 순차적으로 식각하여 표면을 평탄화시킨 상태의 단면도인데, 이때 상기 감광막(a)에 의해 이온주입되지 않은 상기 셀지역(c)의 평탄화층(4b)은 상기 이온이 주입된 주변지역(p)의 평탄화층(4b)에 비해 높은 식각비를 갖기 때문에 주변지역(p)의 평탄화층(4b)이 완전히 제거되는 시점에서는 단차가 없어지게 된다. 또한 여기서 잔류되는 절연막(3b)의 두께를 정확히 조절하기 위해서는 건식식각공정을 추가로 실시하면 된다.4C is a cross-sectional view of the photoresist film 6 with the photoresist film 6 removed, and FIG. 4D is a cross-sectional view where the surface is flattened by sequentially etching the planarization layer 4b and the insulating film 3b by front etching using a wet etching method. In this case, since the planarization layer 4b of the cell region c not ion-implanted by the photosensitive film a has a higher etching ratio than the planarization layer 4b of the peripheral region p where the ions are implanted. When the planarization layer 4b of the peripheral area p is completely removed, the step is eliminated. In addition, in order to accurately adjust the thickness of the insulating film 3b remaining here, a dry etching process may be further performed.
상술한 바와같이 본 발명에 의하면 평탄화층을 형성한 후 단차비에 따라 이온 주입량 및 이온주입 에너지를 조절하여 불순물이온을 주입하므로써 효과적으로 단차를 최소화시킬 수 있으며, 이에따라 후속 사진공정시의 촛점깊이에 대한 이득도 중가된다. 또한 내부 접속라인의 길이를 최소화시킬 수 있어 소자의 동작속도가 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, after the planarization layer is formed, the impurities can be effectively minimized by injecting impurity ions by adjusting the ion implantation amount and the ion implantation energy according to the step difference ratio. The gain is also weighted. In addition, since the length of the internal connection line can be minimized, there is an excellent effect that the operation speed of the device can be improved.
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