KR960043027A - Planarization method of semiconductor device - Google Patents

Planarization method of semiconductor device Download PDF

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Publication number
KR960043027A
KR960043027A KR1019950010975A KR19950010975A KR960043027A KR 960043027 A KR960043027 A KR 960043027A KR 1019950010975 A KR1019950010975 A KR 1019950010975A KR 19950010975 A KR19950010975 A KR 19950010975A KR 960043027 A KR960043027 A KR 960043027A
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KR
South Korea
Prior art keywords
planarization layer
etching
semiconductor device
impurity ions
film
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KR1019950010975A
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Korean (ko)
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KR0168149B1 (en
Inventor
이우봉
홍흥기
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김주용
현대전자산업 주식회사
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Priority to KR1019950010975A priority Critical patent/KR0168149B1/en
Publication of KR960043027A publication Critical patent/KR960043027A/en
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Publication of KR0168149B1 publication Critical patent/KR0168149B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching

Abstract

본 발명은 반도체 소자의 평탄화방법에 관한 것으로, 초고집적 반도체 소자의 제조를 위한 사진공정시 단차로 인해 발생되는 촛점의 깊이에 대한 이득의 저하를 방지하기 위하여 평탄화층을 형성한 후 단차비에 따라 이온주입량(Dose)및 이온주입 에너지(Energy)를 조절하여 불순물이온을 주입하므로써 단차 및 소자의 동작속도를 향상시킬 수 있도록 한 반도체소자의 평탄화방법에 관한 것이다.The present invention relates to a planarization method of a semiconductor device, and to form a planarization layer after forming a planarization layer in order to prevent a decrease in gain of focus depth caused by a step in a photolithography process for manufacturing an ultra-high density semiconductor device. The present invention relates to a planarization method of a semiconductor device in which impurity ions are implanted by controlling ion implantation dose and ion implantation energy, thereby improving the level difference and the operation speed of the device.

Description

반도체 소자의 평탄화방법Planarization method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3a 내지 제3c도는 본 발명의 제1실시예를 설명하기 위한 소자의 단면도, 제4a 내지 제4d도는 본 발명의 제2실시예를 설명하기 위한 소자의 단면도.3A to 3C are cross-sectional views of elements for explaining the first embodiment of the present invention, and FIGS. 4A to 4D are cross-sectional views of elements for explaining the second embodiment of the present invention.

Claims (15)

반도체 소자의 평탄화방법에 있어서, 주변지역에 비하여 셀지역의 단차가 높게 형성된 실리콘기판상에 절연막 및 평탄화층을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 평탄화층의 식각비를 조절하기 위하여 전체상부면에 불순물이온을 주입하는 단계와, 상기 단계로부터 전면식각공정으로 상기 평탄화층 및 절연막을 순차적으로 식각하여 표면을 평탄화시키는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 평탄화방법.A method of planarizing a semiconductor device, the method comprising: sequentially forming an insulating film and a planarization layer on a silicon substrate having a higher step height in a cell region than a peripheral region, and adjusting the etching ratio of the planarization layer from the step. Implanting impurity ions into a surface, and sequentially etching the planarization layer and the insulating layer through the entire surface etching process from the step to planarize the surface of the semiconductor device. 제1항에 있어서, 상기 절연막은 상기 셀지역과 주변지역간의 단차보다 두껍게 형성되는 것을 특징으로 하는 반도체 소자의 평탄화방법.The method of claim 1, wherein the insulating layer is formed thicker than a step between the cell region and a peripheral region. 제1항에 있어서, 상기 절연막은 산화막이며, 상기 평탄화층은 SOG막인 것을 특징으로 하는 반도체 소자의 평탄화방법.The method of claim 1, wherein the insulating film is an oxide film and the planarization layer is an SOG film. 제1항에 있어서, 상기 불순물이온 주입시 상기 단차가 높은 셀지역보다 상기 단차가 낮은 주변지역에 불순물이온이 많이 주입되도록 하는 것을 특징으로 하는 반도체 소자의 평탄화 방법.The planarization method of claim 1, wherein the impurity ions are implanted with more impurity ions into the peripheral area having the step difference lower than the cell area having the step difference. 제1항에 있어서, 상기 전면식각공정은 습식식각으로 실시되는 것을 특징으로 하는 반도체 소자의 평탄화방법.The method of claim 1, wherein the front surface etching process is performed by wet etching. 제1 또는 5항에 있어서, 상기 전면식각공정은 습식 및 건식식각이 순차적으로 실시되는 것을 특징으로 하는 반도체 소자의 평탄화방법.The method of claim 1, wherein the front surface etching process is performed by wet and dry etching sequentially. 반도체 소자의 평탄화방법에 있어서, 주변지역에 비하여 셀지역의 단차가 높게 형성된 실리콘기판상에 절연막 및 평탄화층을 순차적으로 형성하는 단계와, 상기 단계로부터 전체면에 감광막을 도포한 후 소정의 마스크를 이용한 노광 및 현상공정을 실시하여 상기 주변지역의 평탄화층이 노출되도록 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 상기 노출된 평탄화층의 식각비를 조절하기 위하여 전체 상부면에 불순물이온을 주입하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 제거한 후 전면식각공정으로 상기 평탄화층 및 절연막을 순차적으로 식각하여 표면을 평탄화시키는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 평탄화방법.In the planarization method of a semiconductor device, the steps of sequentially forming an insulating film and a planarization layer on a silicon substrate having a higher step height in the cell region compared to the surrounding area, and applying a photoresist film to the entire surface from the step, and then applying a predetermined mask Patterning the photoresist film so as to expose the planarization layer in the peripheral region by performing exposure and development processes, and implanting impurity ions into the entire upper surface to control the etching ratio of the exposed planarization layer from the step; And removing the patterned photoresist film from the step, and then etching the planarization layer and the insulating layer sequentially by a front surface etching process to planarize the surface of the semiconductor device. 제7항에 있어서, 상기 절연막은 상기 셀지역과 주변지역간의 단차보다 두껍게 형성 되는 것을 특징으로 하는 반도체 소자의 평탄화방법.8. The method of claim 7, wherein the insulating film is formed thicker than the step between the cell region and the peripheral region. 제7항에 있어서, 상기 절연막은 산화막이며, 상기 평탄화층은 SOG막인 것을 특징으로 하는 반도체 소자의 평탄화방법.8. The method of claim 7, wherein the insulating film is an oxide film and the planarization layer is an SOG film. 제7항에 있어서, 상기 전면식각공정은 습식식각으로 실시되는 것을 특징으로 하는 반도체 소자의 평탄화방법.The method of claim 7, wherein the front surface etching process is performed by wet etching. 제7 또는 10항에 있어서, 상기 전면식각공정은 습식 및 건식식각이 순차적으로 실시되는 것을 특징으로하는 반도체 소자의 평탄화방법.The method of claim 7 or 10, wherein the front surface etching process is performed by wet and dry etching sequentially. 제1 또는 7항에 있어서, 상기 불순물이온은 아르곤(Ar)이온인 것을 특징으로 하는 반도체 소자의 평탄화방법.8. The method of claim 1 or 7, wherein the impurity ions are argon (Ar) ions. 제1 또는 7항에 있어서, 상기 불순물이온은 인(P)이온인 것을 특징으로 하는 반도체 소자의 평탄화방법.8. The method of claim 1 or 7, wherein the impurity ions are phosphorus (P) ions. 제1 또는 7항에 있어서, 상기 불순물이온은 비소(As)이온인 것을 특징으로 하는 반도체 소자의 평탄화방법.8. The method of claim 1 or 7, wherein the impurity ions are arsenic (As) ions. 제1 또는 7항에 있어서, 상기 불순물이온은 붕소(B)이온인 것을 특징으로 하는 반도체 소자의 평탄화방법.8. The method of claim 1 or 7, wherein the impurity ion is boron (B) ion. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950010975A 1995-05-04 1995-05-04 Method of forming flat layer on semiconductor device KR0168149B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291412B1 (en) * 1998-02-02 2001-07-12 김영환 Method for applying photoresist
KR100595324B1 (en) * 2004-12-30 2006-06-30 동부일렉트로닉스 주식회사 Method for forming semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100519515B1 (en) * 1999-07-02 2005-10-07 주식회사 하이닉스반도체 Method for forming bit-line of a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291412B1 (en) * 1998-02-02 2001-07-12 김영환 Method for applying photoresist
KR100595324B1 (en) * 2004-12-30 2006-06-30 동부일렉트로닉스 주식회사 Method for forming semiconductor device

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