KR970003634A - Planarization method of semiconductor device - Google Patents
Planarization method of semiconductor device Download PDFInfo
- Publication number
- KR970003634A KR970003634A KR1019950018854A KR19950018854A KR970003634A KR 970003634 A KR970003634 A KR 970003634A KR 1019950018854 A KR1019950018854 A KR 1019950018854A KR 19950018854 A KR19950018854 A KR 19950018854A KR 970003634 A KR970003634 A KR 970003634A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- plasma oxide
- forming
- semiconductor device
- photoresist pattern
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 평탄화 방법에 관한 것으로 물질층이 형성된 반도체기판 상부에 금속배선을 형성하고 전체표면상부에 제1플라즈마 산화막을 형성한 다음, 전체표면상부에 평탄화층을 형성하고 상기 평탄화층 상부에 제2플라즈마 산화막을 형성한 다음, 셀부와 주변회로부 사이가 경사진 감광막패턴을 단차가 낮은 주변회로부에 형성하고 상기 감광막패턴을 마스크로하여 상기 단차가 높아 노출된 제2플라즈마 산화막에 불순물이온을 주입한 다음, 상기 감광막패턴을 제거하고 상기 불순물이온이 주입된 부분과 주입되지 않은 부분의 식각 선택비 차이를 이용한 식각공정으로 상기 단차가 높은 셀부를 일정두께 제거함으로써 단차를 완화시켜 후공정을 용이하게 하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a planarization method of a semiconductor device, wherein a metal wiring is formed on an upper surface of a semiconductor substrate on which a material layer is formed, a first plasma oxide film is formed on an entire surface, and a planarization layer is formed on an entire surface of the semiconductor substrate. After forming the second plasma oxide film on the substrate, a photoresist pattern inclined between the cell portion and the peripheral circuit portion is formed in the peripheral circuit portion having a low level, and impurity ions are formed in the exposed second plasma oxide film using the photosensitive film pattern as a mask. After the implantation, the photoresist pattern is removed, and an etching process using a difference in etching selectivity between the portions into which the impurity ions are implanted and the portions into which the impurity ions are implanted is removed. It is a technology that enables high integration of the semiconductor device accordingly.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2A도 내지 제2C도는 본 발명의 실시예에 따른 반도체소자의 평탄화 방법을 도시한 단면도.2A through 2C are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with an embodiment of the present invention.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018854A KR970003634A (en) | 1995-06-30 | 1995-06-30 | Planarization method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018854A KR970003634A (en) | 1995-06-30 | 1995-06-30 | Planarization method of semiconductor device |
Publications (1)
Publication Number | Publication Date |
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KR970003634A true KR970003634A (en) | 1997-01-28 |
Family
ID=66526519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950018854A KR970003634A (en) | 1995-06-30 | 1995-06-30 | Planarization method of semiconductor device |
Country Status (1)
Country | Link |
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KR (1) | KR970003634A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100869845B1 (en) * | 2006-12-04 | 2008-11-21 | 주식회사 하이닉스반도체 | Method for forming oxide pattern and patterning method of semiconductor device |
-
1995
- 1995-06-30 KR KR1019950018854A patent/KR970003634A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100869845B1 (en) * | 2006-12-04 | 2008-11-21 | 주식회사 하이닉스반도체 | Method for forming oxide pattern and patterning method of semiconductor device |
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E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |