KR970003634A - Planarization method of semiconductor device - Google Patents

Planarization method of semiconductor device Download PDF

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Publication number
KR970003634A
KR970003634A KR1019950018854A KR19950018854A KR970003634A KR 970003634 A KR970003634 A KR 970003634A KR 1019950018854 A KR1019950018854 A KR 1019950018854A KR 19950018854 A KR19950018854 A KR 19950018854A KR 970003634 A KR970003634 A KR 970003634A
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KR
South Korea
Prior art keywords
oxide film
plasma oxide
forming
semiconductor device
photoresist pattern
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Application number
KR1019950018854A
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Korean (ko)
Inventor
김시범
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김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950018854A priority Critical patent/KR970003634A/en
Publication of KR970003634A publication Critical patent/KR970003634A/en

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Abstract

본 발명은 반도체소자의 평탄화 방법에 관한 것으로 물질층이 형성된 반도체기판 상부에 금속배선을 형성하고 전체표면상부에 제1플라즈마 산화막을 형성한 다음, 전체표면상부에 평탄화층을 형성하고 상기 평탄화층 상부에 제2플라즈마 산화막을 형성한 다음, 셀부와 주변회로부 사이가 경사진 감광막패턴을 단차가 낮은 주변회로부에 형성하고 상기 감광막패턴을 마스크로하여 상기 단차가 높아 노출된 제2플라즈마 산화막에 불순물이온을 주입한 다음, 상기 감광막패턴을 제거하고 상기 불순물이온이 주입된 부분과 주입되지 않은 부분의 식각 선택비 차이를 이용한 식각공정으로 상기 단차가 높은 셀부를 일정두께 제거함으로써 단차를 완화시켜 후공정을 용이하게 하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a planarization method of a semiconductor device, wherein a metal wiring is formed on an upper surface of a semiconductor substrate on which a material layer is formed, a first plasma oxide film is formed on an entire surface, and a planarization layer is formed on an entire surface of the semiconductor substrate. After forming the second plasma oxide film on the substrate, a photoresist pattern inclined between the cell portion and the peripheral circuit portion is formed in the peripheral circuit portion having a low level, and impurity ions are formed in the exposed second plasma oxide film using the photosensitive film pattern as a mask. After the implantation, the photoresist pattern is removed, and an etching process using a difference in etching selectivity between the portions into which the impurity ions are implanted and the portions into which the impurity ions are implanted is removed. It is a technology that enables high integration of the semiconductor device accordingly.

Description

반도체소자의 평탄화 방법Planarization method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명의 실시예에 따른 반도체소자의 평탄화 방법을 도시한 단면도.2A through 2C are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with an embodiment of the present invention.

Claims (6)

반도체기판의 셀부와 주변회로부에 각각 금속패턴을 형성하고 그 상부를 평탄화시키는 반도체소자의 평탄화 방법에 있어서, 금속배선을 형성하는 공정과, 전체표면상부에 제1플라즈마 산화막을 형성하는 공정과, 전체 표면상부에 SOG막을 형성하는 공정과, 상기 SOG막 상부에 제2플라즈마 산화막을 형성하는 공정과, 상기 제2플라즈마 산화막 상부중에서 단차가 낮은 부분에 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로 하여 상기 노출된 제2플라즈마 산화막에 불순물이온을 일정깊이 주입하는 공정과, 상기 감광막패턴을 제거하는 공정과, 상기 불순물이 주입된 부분과 주입되지 않은 부분이 식각선택비 차이를 이용하여 상기 불순물이온이 주입된 제2플라즈마 산화막을 제거하는 공정을 포함하는 반도체소자의 평탄화 방법.A method of planarizing a semiconductor device in which a metal pattern is formed on each of a cell portion and a peripheral circuit portion of a semiconductor substrate, and a top thereof is planarized, the method comprising: forming a metal wiring; forming a first plasma oxide film over the entire surface; Forming a SOG film on the surface, forming a second plasma oxide film on the SOG film, forming a photoresist pattern on a portion of the upper portion of the second plasma oxide film having a low step, and masking the photosensitive film pattern Implanting impurity ions into the exposed second plasma oxide film at a predetermined depth; removing the photoresist pattern; and implanting the impurity and non-implanted portions using the difference in etching selectivity. A method of planarizing a semiconductor device comprising the step of removing the second plasma oxide film implanted with ions. 제1항에 있어서, 상기 감광막패턴은 주변회로부와 셀부의 경계부가 경사지게 형성되는 것을 특징으로 하는 반도체소자의 평탄화 방법.The method of claim 1, wherein the photoresist pattern is formed such that a boundary between a peripheral circuit portion and a cell portion is inclined. 제1항에 있어서, 상기 불순물이온은 인이 사용되는 것을 특징으로 하는 반도체소자의 평탄화 방법.The method of claim 1, wherein the impurity ions are phosphorus. 제3항에 있어서, 상기 인이 함유된 상기 제2플라즈마 산화막은 불산용액으로 제거되는 것을 특징으로 하는 반도체소자의 평탄화 방법.The method of claim 3, wherein the second plasma oxide film containing phosphorus is removed with a hydrofluoric acid solution. 제1항에 있어서, 상기 붕소가 함유된 상기 제2플라즈마 산화막은 완충불산으로 제거되는 것을 특징으로 하는 반도체소자의 평탄화 방법.The method of claim 1, wherein the boron-containing second plasma oxide film is removed by buffered hydrofluoric acid. 제1항에 있어서, 상기 불순물이온의 농도는 1015/㎠ 이상의 실시되는 것을 특징으로 하는 반도체소자의 평탄화 방법.The method of claim 1, wherein the concentration of the impurity ion is 10 15 / cm 2 or more. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950018854A 1995-06-30 1995-06-30 Planarization method of semiconductor device KR970003634A (en)

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KR1019950018854A KR970003634A (en) 1995-06-30 1995-06-30 Planarization method of semiconductor device

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KR1019950018854A KR970003634A (en) 1995-06-30 1995-06-30 Planarization method of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100869845B1 (en) * 2006-12-04 2008-11-21 주식회사 하이닉스반도체 Method for forming oxide pattern and patterning method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100869845B1 (en) * 2006-12-04 2008-11-21 주식회사 하이닉스반도체 Method for forming oxide pattern and patterning method of semiconductor device

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