KR970004055A - Angle regulated trench - Google Patents

Abstract

The present invention relates to a method of forming a device isolation insulating film of a semiconductor device, wherein the first photoresist layer pattern formed by the etching process using the first device isolation mask is used as a mask to form first and second trenches, and the etching using the second device isolation mask. Forming a high concentration ion implantation layer using the second photoresist pattern formed as a mask as a mask, and then forming a field oxide film by the field oxidation process, and separating the trench type and LOCOS type devices in the cell part and the peripheral circuit part by the planarization process and the planarization etching process, respectively. It is a technology that can simplify the process by forming an insulating film to improve the yield and productivity of the semiconductor device.

Description

Angle regulated trench

Since this is an open matter, no full text was included.

1A to 1E are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device in accordance with an embodiment of the present invention.

Claims (7)

Forming a first photoresist pattern on the semiconductor substrate, forming the first and second trenches in the cell portion and the peripheral circuit by etching the semiconductor substrate using the first photoresist pattern as a mask, Forming a second photoresist pattern, forming a high ion implantation layer by implanting a high concentration of impurity ions into the second trench using the second photoresist pattern as a mask, and removing the second and first photoresist pattern And a step of forming a field oxide film by a field oxidation process, a step of forming a planarization layer on the entire surface, and a step of forming a device isolation insulating film on the cell portion and the peripheral circuit portion by a planarization etching process. A device isolation insulating film formation method of a device. The method of claim 1, wherein the first photoresist layer pattern is formed by an etching process using a first device isolation mask to form trenches in the cell unit and the peripheral circuit unit. The method of claim 1, wherein the trench is formed to a depth of 1000 to 3500 microns. The method of claim 1, wherein the second photoresist pattern exposes only the peripheral circuit portion. The method of claim 1, wherein the field oxide layer is formed to have a thickness of 2500 to 6000 GPa. The method of claim 1, wherein the planarization layer is formed of an insulating material having a good flow such as BPSG. The method of claim 1, wherein the planarization etching process is performed by a dry method and a wet method. ※ Note: The disclosure is based on the initial application.