KR970072295A - Method for forming a separation film of a semiconductor element - Google Patents

Method for forming a separation film of a semiconductor element Download PDF

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Publication number
KR970072295A
KR970072295A KR1019960010285A KR19960010285A KR970072295A KR 970072295 A KR970072295 A KR 970072295A KR 1019960010285 A KR1019960010285 A KR 1019960010285A KR 19960010285 A KR19960010285 A KR 19960010285A KR 970072295 A KR970072295 A KR 970072295A
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South Korea
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forming
oxide film
semiconductor substrate
trench
conductive
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KR1019960010285A
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Korean (ko)
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KR0179291B1 (en
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이욱하
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문정환
Lg 반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 소자중 격리막 형성방법에 관한 것으로, 일반적인 로코스 공정에 의한 격리막과 트렌치 구조를 이용한 격리막을 단위셀에 적용하여 소자의 신뢰도를 향상하는 데 그목적이 있다.The present invention relates to a method of forming an isolation layer in a semiconductor device, and an object of the present invention is to improve reliability of a device by applying a isolation layer using a general LOCOS process and a trench structure to a unit cell.

이를 위한 본 발명의 반도체 소자의 격리막 형성방법은 메모리셀부와 주변회로부로 정의된 제1도전형 반도체 기판상에 주변회로부에는 제1도전형 웰과 제2도전형 웰을 형성하고 메모리셀부에는 제1도전형 웰을 형성하는 단계; 상기 제1도전형 반도체 기판중 트랜치를 이용한 격리막 형성영역과 필드 산화막 형성영역으로 격리영역을 정의하는 단계; 제1도전형 반도체 기판에 초기 산화막과 질화막을 차례로 형성하는 단계; 상기 트랜치를 이용한 격리막 형성영역의 질화막과 초기 산화막을 선택적으로 패터닝하여 트랜치를 형성할 제1도전형 반도체 기판을 노출시키는 단계; 상기 질화막을 마스크로 하여 노출된 제1도전형 반도체 기판상에 형성된 제1, 제2도전형 웰을 선택적으로 식각하여 트랜치를 형성하는데 단계; 상기 트랜치내에 격리막을 형성하는 단계를 포함하여 이루어지고, 필드 산화막 형성영역의 질화산막과 산화막질을 선택적으로 패터닝 하여 필드 산화막을 형설할 제1도전형 반도체 기판을 노출시키는 단계; 상기 노출된 제1도전형 반도체 기판상에 형성된 제1도전형 웰에는 제1도전형 채널 스톱층을 형성하고, 제2도전형 웰에는 제2도전형 채널 스톱층을 형성하는 단계; 상기 필드 산화막 형성영역 전면에 열산화를 실시하여 필드 산화막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method for forming a separation layer of a semiconductor device of the present invention includes forming a first conductive type well and a second conductive type well in a peripheral circuit portion on a first conductive type semiconductor substrate defined by a memory cell portion and a peripheral circuit portion, Forming a conductive well; Defining an isolation region in the first conductive semiconductor substrate using a trench and a field oxide film formation region; Sequentially forming an initial oxide film and a nitride film on the first conductivity type semiconductor substrate; Exposing a first conductivity type semiconductor substrate on which a trench is to be formed by selectively patterning a nitride film and an initial oxide film in a separation film formation region using the trench; Etching the first and second conductive wells formed on the exposed first conductive semiconductor substrate using the nitride film as a mask to form a trench; Exposing a first conductive type semiconductor substrate to form a field oxide film by selectively patterning a nitride film and an oxide film in a field oxide film formation region, the method comprising: forming a separation film in the trench; Forming a first conductive type channel stop layer in the first conductive type well formed on the exposed first conductivity type semiconductor substrate and a second conductive type channel stop layer in the second conductive type well; And forming a field oxide film by performing thermal oxidation on the entire surface of the field oxide film formation region.

Description

반도체 소자의 격리막 형성방법Method for forming a separation film of a semiconductor element

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도(d) 내지 (i)은 본 발명 제1실시예에 따른 반도체 소자의 격리막 제조공정 단면도.FIG. 2 (d) to FIG. 2 (i) are sectional views of a process for manufacturing a semiconductor device isolation film according to the first embodiment of the present invention.

Claims (5)

메모리셀부와 주변회로부로 정의된 제1도전형 반도체 기판상에 주변회로부에는 제1도전형 웰과 제2도전형 웰을 형성하고 메모리셀부에는 제1도전형 웰을 형성하는 단계; 상기 제1도전형 반도체 기판중 트랜치를 이용한 격리막 형성영역과 필드 산화막 형성영역으로 격리영역을 정의하는 단계; 제1도전형 반도체 기판에 초기 산화막과 질화막을 차례로 형성하는 단계; 상기 트랜치를 이용한 격리막 형성영역의 질화막과 초기 산화막을 선택적으로 패터닝하여 트랜치를 형성할 제1도전형 반도체 기판을 노출시키는 단계; 상기 질화막을 마스크로 하여 노출된 제1도전형 반도체 기판상에 형성된 제1, 제2도전형 웰을 선택적으로 식각하여 트랜치를 형성하는 단계; 상기 트랜치내에 격리막을 형성하는 단계를 포함하여 이루어지고, 필드 산화막 형성영역의 질화막과 산화막을 선택적으로 패터닝 하여 필드 산화막을 형설할 제1도전혀 반도체 기판을 노출시키는 단계; 상기 노출된 제1도전형 반도체 기판상에 형성된 제1도전형 웰에는 제1도전형 채널 스톱층을 형성하고, 제2도전형 웰에는 제2도전형 채널 스톱층을 형성하는 단계; 상기 필드 산화막 형성영역 전면에 일산화를 실시하여 필드 산화막을 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 격리막 형성방법.Forming a first conductivity type well and a second conductivity type well in a peripheral circuit portion and forming a first conductivity type well in a memory cell portion on a first conductivity type semiconductor substrate defined by a memory cell portion and a peripheral circuit portion; Defining an isolation region in the first conductive semiconductor substrate using a trench and a field oxide film formation region; Sequentially forming an initial oxide film and a nitride film on the first conductivity type semiconductor substrate; Exposing a first conductivity type semiconductor substrate on which a trench is to be formed by selectively patterning a nitride film and an initial oxide film in a separation film formation region using the trench; Forming a trench by selectively etching the first and second conductive wells formed on the exposed first conductive semiconductor substrate using the nitride film as a mask; Exposing a first conductive tongue semiconductor substrate to form a field oxide film by selectively patterning a nitride film and an oxide film in a field oxide film formation region, the method comprising: forming a separation film in the trench; Forming a first conductive type channel stop layer in the first conductive type well formed on the exposed first conductivity type semiconductor substrate and a second conductive type channel stop layer in the second conductive type well; And forming a field oxide film by performing mono-oxidation on the entire surface of the field oxide film formation region. 제1항에 있어서, 상기 격리막은 산화막으로 형성함을 특징으로 하는 반도체 소자의 격리막 형성방법.The method of claim 1, wherein the isolation layer is formed of an oxide layer. 제2항에 있어서, 상기 산화막은 CVD법으로 형성함을 특징으로 하는 소자의 격리막 형성방법.The method according to claim 2, wherein the oxide film is formed by CVD. 제1항에 있어서, 제1도전형 기판상에 형성하는 트랜치를 이용한 격리막과 열산화를 이용한 필드 산화막을 각각 집적도가 높은 부분과 집적도에 여유가 있는 부분을 정의한 후 사용하는 것을 특징으로 하는 반도체 소자의 격리막 형성방법.2. The semiconductor device according to claim 1, wherein a separation film using a trench formed on the first conductive type substrate and a field oxide film using thermal oxidation are defined after defining a portion having a high degree of integration and a portion having a sufficient degree of integration, . 제1항에 있어서, 트랜치 형성후 필드이온을 주입하여 채널 스톱층을 형성한 다음 격리막을 형성하는 것을 특징으로 하는 반도체 소자의 격리막 형성방법.The method for forming a separation film of a semiconductor device according to claim 1, wherein a field ion is implanted to form a channel stop layer after forming the trench, and then a separation film is formed. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960010285A 1996-04-04 1996-04-04 Method for forming isolation film of semiconductor device KR0179291B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020056288A (en) * 2000-12-29 2002-07-10 박종섭 Method for forming shallow trench isolation in semiconductor device
KR100390903B1 (en) * 2000-12-29 2003-07-12 주식회사 하이닉스반도체 method for manufacturing of SRAM of semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010064965A (en) * 1999-12-20 2001-07-11 박종섭 Method for manufacturing of semiconductor device
KR100375870B1 (en) * 2000-05-22 2003-03-15 상산소재 주식회사 Method for press molding sheet made of artificial marble and washstand integrated bowl manufactured by the method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020056288A (en) * 2000-12-29 2002-07-10 박종섭 Method for forming shallow trench isolation in semiconductor device
KR100390903B1 (en) * 2000-12-29 2003-07-12 주식회사 하이닉스반도체 method for manufacturing of SRAM of semiconductor device

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