KR970054431A - MOS transistor and manufacturing method thereof - Google Patents

MOS transistor and manufacturing method thereof Download PDF

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KR970054431A
KR970054431A KR1019950054718A KR19950054718A KR970054431A KR 970054431 A KR970054431 A KR 970054431A KR 1019950054718 A KR1019950054718 A KR 1019950054718A KR 19950054718 A KR19950054718 A KR 19950054718A KR 970054431 A KR970054431 A KR 970054431A
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gate electrode
thickness
gate
conductive film
pattern
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KR0183785B1 (en
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김성환
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

모스 트랜지스터 및 그 제조방법이 개시되어 있다. 본 발명은 제1도전형의 반도체 기판; 상기 반도체 기판 표면에 채널영역을 사이에 두고 그 양 옆에 제2도전형의 불순물로 도우핑된 소오스 영역 및 드레인 영역; 상기 채널영역 표면 및 상기 소오스/드레인 영역 표면에 각각 제1두께 및 상기 제1두께보다 두꺼운 제2두께를 갖는 게이트 산화막 패턴; 상기 제1두께의 게이트 산화막 패턴 상에 형성된 제1게이트 전극; 상기 제1게이트 전극양 측벽에 형성된 제3게이트 전극; 및 상기 제3게이트 전극 양 측벽이면서 상기 제2두께의 게이트 산화막 패턴상에 폴리실리콘 스페이서로 이루어진 제2게이트 전극을 구비하는 것을 특징으로 하는 모스 트랜지스터를 제공한다. 본 발명에 의하면, 게이트 전극의 양 끝 부분의 아래에 두꺼운 게이트 산화막 패턴을 형성하여 게이트전극으로의 핫 캐리어 주입을 크게 감소시킬 수 있으며, 결과적으로 신뢰성이 높은 모스 트랜지스터를 구현할 수 있다.A MOS transistor and a manufacturing method thereof are disclosed. The present invention provides a semiconductor substrate of a first conductive type; A source region and a drain region doped with impurities of a second conductivity type on both sides of the semiconductor substrate with a channel region interposed therebetween; A gate oxide pattern having a first thickness and a second thickness thicker than the first thickness on the channel region surface and the source / drain region surface, respectively; A first gate electrode formed on the gate oxide pattern of the first thickness; Third gate electrodes formed on sidewalls of the first gate electrode; And a second gate electrode formed of polysilicon spacers on both sidewalls of the third gate electrode and on the gate oxide layer pattern having the second thickness. According to the present invention, a thick gate oxide film pattern is formed under both ends of the gate electrode, thereby greatly reducing hot carrier injection into the gate electrode, and as a result, a highly reliable MOS transistor can be realized.

Description

모스 트랜지스터 및 그 제조방법MOS transistor and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 모스 트랜지스터의 구조를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a MOS transistor according to the present invention.

Claims (7)

제1도전형의 반도체 기판; 상기 반도체 기판 표면에 채널영역을 사이에 두고 그 양 옆에 제2도전형의 불순물로 도우핑된 소오스 영역 및 드레인 영역; 상기 채널영역 표면 및 상기 소오스/드레인 영역 표면에 각각 제1두께 및 상기 제1두께보다 두께운 제2두께를 갖는 게이트 산화막 패턴; 상기 제1두께의 게이트 산화막 패턴상에 형성된 제1게이트 전극; 상기 제1게이트 전극 양 측벽에 형성된 제3게이트 전극; 및 상기 제3게이트 전극 양 측벽이면서 상기 제2두께의 게이트 산화막 패턴상에 폴리실리콘 스페이서로 이루어진 제2게이트 전극을 구비하는 것을 특징으로 하는 모스 트랜지스터.A first conductive semiconductor substrate; A source region and a drain region doped with impurities of a second conductivity type on both sides of the semiconductor substrate with a channel region interposed therebetween; A gate oxide pattern having a first thickness and a second thickness greater than the first thickness on the channel region surface and the source / drain region surface, respectively; A first gate electrode formed on the gate oxide pattern of the first thickness; Third gate electrodes formed on both sidewalls of the first gate electrode; And a second gate electrode formed of polysilicon spacers on both sidewalls of the third gate electrode and on the gate oxide layer pattern having the second thickness. 제1항에 있어서, 상기 소오스/드레인 영역은 LDD구조인 것을 특징으로 하는 모스 트랜지스터.The MOS transistor of claim 1, wherein the source / drain region has an LDD structure. 제1도전형의 반도체 기판 전면에 제1두께를 갖는 게이트 산화막을 형성하는 단계; 상기 게이트 산화막의 소정영역 상에 제1도전막으로 이루어진 제1게이트 전극을 형성하는 단계; 상기 제1게이트 전극의 양 측벽에 실리콘질화막 스페이서를 형성하는 단계; 상기 결과물을 열산화시키어 상기 실리콘질화막 스페이서 양 옆의 반도체 기판 표면에 상기 제1두께보다 두꺼운 제2두께의 게이트 산화막 패턴을 형성함과 동시에 상기 제1게이트 전극상에 열산화막을 형성하는 단계; 상기 결과물 전면에 제2도전막을 형성한 후 이를 이방성식각하여 상기 실리콘질화막 스페이서의 측벽에 제2도전막 스페이서로 이루어진 제2게이트 전극을 형성하는 단계; 상기 열산화막을 노출시키는 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각 마스크로 하여 상기 열산화막 및 상기 실리콘질화막 스페이서를 제거하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 상기 결과물 전면에 상기 실리콘질화막 스페이서가 제거된 부분을 채우는 제3도전막을 형성하는 단계; 및 상기 제3도전막을 이방성식각하여 상기 실리콘질화막 스페이서가 제거된 부분을 채우는 제3도전막으로 이루어진 제3게이트 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.Forming a gate oxide film having a first thickness on the entire surface of the first conductive semiconductor substrate; Forming a first gate electrode formed of a first conductive film on a predetermined region of the gate oxide film; Forming silicon nitride film spacers on both sidewalls of the first gate electrode; Thermally oxidizing the resultant to form a gate oxide layer pattern having a second thickness thicker than the first thickness on surfaces of semiconductor substrates adjacent to the silicon nitride layer spacers, and simultaneously forming a thermal oxide layer on the first gate electrode; Forming a second conductive film on the entire surface of the resultant and then anisotropically etching the second conductive film to form a second gate electrode formed of a second conductive film spacer on a sidewall of the silicon nitride film spacer; Forming a photoresist pattern exposing the thermal oxide film; Removing the thermal oxide layer and the silicon nitride layer spacer using the photoresist pattern as an etching mask; Removing the photoresist pattern; Forming a third conductive film on the entire surface of the resultant material to fill the portion where the silicon nitride film spacer is removed; And anisotropically etching the third conductive film to form a third gate electrode formed of a third conductive film filling a portion from which the silicon nitride film spacer is removed. 제3항에 있어서, 상기 제1도전막은 도우핑된 폴리실리콘 또는 텅스텐 폴리사이드로 형성하는 것을 특징으로 하는 모스 트랜지스터 제조방법.The method of claim 3, wherein the first conductive layer is formed of doped polysilicon or tungsten polyside. 제3항에 있어서, 상기 제2도전막 및 제3도전막은 모두 도우핑된 폴리실리콘으로 형성하는 것을 특징으로 하는 모스 트랜지스터 제조방법.The method of claim 3, wherein both of the second conductive film and the third conductive film are formed of doped polysilicon. 제3항에 있어서, 상기 포토레지스트 패턴은 상기 제2게이트 전극이 형성된 반도체 기판 전면에 포토레지스트 패턴을 도포한 후, 상기 열산화막이 노출될 때까지 상기 포토레지스트 패턴을 전면 에치백하여 형성하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.The method of claim 3, wherein the photoresist pattern is formed by applying a photoresist pattern on the entire surface of the semiconductor substrate on which the second gate electrode is formed, and then etching back the entire photoresist pattern until the thermal oxide layer is exposed. A method of manufacturing a MOS transistor. 제6항에 있어서, 상기 전면 에치백은 건식식각방법으로 실시하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.7. The method of claim 6, wherein the front etch back is performed by a dry etching method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950054718A 1995-12-22 1995-12-22 Method of manufacturing mos transistor KR0183785B1 (en)

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Publication number Priority date Publication date Assignee Title
KR20040035088A (en) * 2002-10-18 2004-04-29 삼성전자주식회사 Method for forming a gate electrode having side wall spacer
KR100809335B1 (en) 2006-09-28 2008-03-05 삼성전자주식회사 Semiconductor device and method of fabricating the same
US20080116521A1 (en) 2006-11-16 2008-05-22 Samsung Electronics Co., Ltd CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same
US7534678B2 (en) 2007-03-27 2009-05-19 Samsung Electronics Co., Ltd. Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby
US7902082B2 (en) 2007-09-20 2011-03-08 Samsung Electronics Co., Ltd. Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers
US7923365B2 (en) 2007-10-17 2011-04-12 Samsung Electronics Co., Ltd. Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon

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