KR970054379A

KR970054379A - Manufacturing method of LDD MOS device

Info

Publication number: KR970054379A
Application number: KR1019950047588A
Authority: KR
Inventors: 박강욱
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-07
Filing date: 1995-12-07
Publication date: 1997-07-31

Abstract

본 발명은 등방성 플라즈마 애싱(Isotropic plasma ashing)을 이용한 엘디디(LDD) 모스(MOS) 소자의 제조방법에 관한 것으로서, 한 번의 사진 공정으로 소오스, 드레인 영역 및 LDD영역을 형성함으로써 스페이서를 침적하고 식각함에 따른 공정 단가 상승을 해결하고, 소오스 및 드레인 영역이 도전층의 식각 단계에서 산화막에 의해 보호되도록 함으로써 이 부분의 표면 손상을 방지할 수 있으며, 따라서 전체적인 공정이 선행 기술에 비해 간단한 LDD MOS소자의 제조방법을 제공하고자 한 것이다.The present invention relates to a method for manufacturing an LDD MOS device using isotropic plasma ashing, in which a spacer is deposited and etched by forming a source, a drain region, and an LDD region in a single photographic process. In order to solve the process cost increase and to ensure that the source and drain regions are protected by the oxide film in the etching step of the conductive layer, it is possible to prevent the surface damage of this part. It is to provide a manufacturing method.

Description

Manufacturing method of LDD MOS device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 LDD MOS 소자의 형성 과정을 도시한 공정도.2 is a process chart showing the formation process of the LDD MOS device according to the present invention.

Claims

Forming a gate oxide film and a conductive layer on the silicon substrate; Forming a photoresist pattern on the conductive layer to define a high concentration of source and drain regions; Selectively etching the conductive layer until the gate oxide layer is exposed through the opening of the photoresist pattern; A fourth step of implanting ions into the silicon substrate from the gate oxide layer through the etched portion of the conductive layer to form a high concentration source and drain region; A fifth step of defining a gate region by etching an edge portion of the conductive layer upper photoresist pattern by a predetermined width; A sixth step of forming a gate electrode by etching the conductive layer using the photoresist pattern formed in the fifth step as a mask; And forming a low concentration source and drain regions in the silicon substrate so as to self-align to the gate electrode.

The method of claim 1, further comprising: depositing polysilicon to a predetermined thickness over the entire upper surface of the silicon substrate to form an overlap LDD device; And anisotropic dry etching the deposited polysilicon layer to form spacers on the sidewalls of the conductive layer.

The method of claim 1, wherein the gate electrode is a double structure of polysilicon and silicide.

4. The method of claim 3, wherein the silicide of the gate electrode is formed of a conductive layer of Al, Cu-Al, Ti-Al, Cu, or the like.

The method of manufacturing an LDD MOS device according to claim 1, wherein an additional oxide film is formed according to the use of the gate oxide film.

The method of claim 1 or 2, wherein the etching of the second and sixth steps is anisotropic dry etching.

※ Note: The disclosure is based on the initial application.