KR950030279A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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KR950030279A
KR950030279A KR1019940006925A KR19940006925A KR950030279A KR 950030279 A KR950030279 A KR 950030279A KR 1019940006925 A KR1019940006925 A KR 1019940006925A KR 19940006925 A KR19940006925 A KR 19940006925A KR 950030279 A KR950030279 A KR 950030279A
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insulating film
conductive layer
gate insulating
forming
region
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KR970006266B1 (en
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이봉재
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체소자 및 이의 제조방법에 관한 것으로, 채널길이가 짧은 MOSFET의 숏채널 효과를 개선하기 위한 것이다.The present invention relates to a semiconductor device and a method for manufacturing the same, and to improve the short channel effect of a MOSFET having a short channel length.

본 발명은 제1도전형의 반도체기판상에 버퍼층을 형성하는 공정과, 상기 버퍼층상에 절연막을 형성하는 공정, 상기 절연막상에 포토레지스트를 도포하는 공정, 상기 포토레지스트를 사진식각공정에 의해 선택적으로 노광 및 현상하여 반도체기판의 게이트전극이 형성될 영역 이외의 영역에만 남기는 공정, 상기 포토레지스트를 마스크로 하여 상기 절연막과 버퍼층을 선택적으로 제거하여 반도체기판의 게이트전극 형성영역을 노출시키는 공정, 상기 포토레지스트를 제거하는 공정, 상기 노출된 반도체기판영역상에 제1게이트절연막을 형성하는 공정, 상기 제1게이트절연막 및 절연막 전면에 도전물질을 증착한후 에치백하여 상기 절연막의 측면에 스페이서 형태의 제1도전층을 형성하는 공정, 상기 절연막 및 제1도전층을 마스크로 이용하여 상기 제1게이트절연막을 선택적으로 식각하는 공정, 상기 제1게이트절연막의 식각에 의해 노출된 반도체기판영역과 제1도전층상에 제2게이트절연막을 형성하는 공정, 제1도전형 불순물을 저농도로 이온주입하여 제2게이트절연막 하부의 반도체기판내에 펀치쓰루 방지영역을 형성하는 공정, 상기 제2게이트절연막상에 제2도전층을 형성하는 공정, 상기 제2게이트절연막의 소정부분을 제거하여 상기 제1도전층의 상부를 노출시키는 공정, 상기 노출된 제1도전층 상부 및 제2도전층상에 제3도전층을 형성하는 공정, 상기 절연막 및 버퍼층을 차례로 제거하는 공정, 제2도전형 불순물을 저농도로 이온주입하여 반도체기판내의 소정영역에 저농도 불순물영역을 형성하는 공정, 상기 제1도전층 및 제3도전층 측면에 절연막 측벽스페이서를 형성하는 공정, 및 제2도전형 불순물을 고농도로 이온주입하여 반도체기판내의 소정영역에 고농도 소오스 및 드레인영역을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자 제조방법을 제공한다.The present invention provides a method of forming a buffer layer on a semiconductor substrate of a first conductivity type, forming an insulating film on the buffer layer, applying a photoresist on the insulating film, and selectively etching the photoresist by a photolithography process. Exposing and developing the semiconductor substrate to leave only regions other than the region where the gate electrode is to be formed, and selectively removing the insulating layer and the buffer layer using the photoresist as a mask to expose the gate electrode forming region of the semiconductor substrate. Removing the photoresist; forming a first gate insulating film on the exposed semiconductor substrate region; depositing a conductive material on the entire surface of the first gate insulating film and the insulating film, and then etching back to form a spacer on the side of the insulating film. Forming a first conductive layer, using the insulating film and the first conductive layer as a mask; Selectively etching a gate insulating film, forming a second gate insulating film on the semiconductor substrate region and the first conductive layer exposed by the etching of the first gate insulating film, and ion-implanting a first conductive impurity at low concentration. Forming a punch-through prevention region in the semiconductor substrate under the two-gate insulating film; forming a second conductive layer on the second gate insulating film; and removing a predetermined portion of the second gate insulating film to remove the predetermined portion of the first conductive layer. Exposing the upper portion, forming a third conductive layer on the exposed first conductive layer and on the second conductive layer, sequentially removing the insulating layer and the buffer layer, and ion implanting the second conductive impurities at low concentration. Forming a low concentration impurity region in a predetermined region in the semiconductor substrate, forming an insulating film sidewall spacer on the side surfaces of the first conductive layer and the third conductive layer, and a second conductive type A method of manufacturing a semiconductor device comprising the step of forming a high concentration source and drain region in a predetermined region in a semiconductor substrate by implanting impurities at a high concentration.

Description

반도체소자 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 일실시예에 의한 LDD구조의 MOS트랜지스터 제조방법을 도시한 공정순서도.4 is a process flowchart showing a method of manufacturing an MOS transistor of an LDD structure according to an embodiment of the present invention.

Claims (15)

제1도전형의 반도체기판(1)과, 상기 제1도전형의 반도체기판(1)내에 서로 이격되어 형성된 제2도전형의 고농도 소오스영역 및 드레인영역(26), 상기 제2도전형의 고농도 소오스영역과 드레인영역(26)의 마주 보는 측에 소오스영역 및 드레인영역 각각에 인접하여 형성된 제2도전형의 저농도 불순물영역(24), 상기 제2도전형의 저농도 불순물영역(24)사이의 반도체기판영역 상부의 양단부분에 형성된 제1게이트절연막(16), 상기 제1게이트절연막(16)사이의 반도체기판영역 상부에 형성된 제2게이트절연막(18), 상기 제1게이트절연막(16)상에 형성된 측벽스페이서 형태의 제1도전층(17), 상기 제2게이트절연막(18)상에 형성된 제2도전층(21), 상기 제1도전층(17) 및 제2도전층(21)상부에 형성된 제3도전층(22), 상기 제1도전층(17) 및 제3도전층(22) 측면에 형성된 절연막 측벽스페이서(25), 및 상기 제2게이트절연막(18) 하부의 반도체기판 영역내에 형성된 펀치쓰루방지영역(20)을 포함하여 이루어진 것을 특징으로 하는 반도체소자.High concentration source and drain regions 26 of the second conductive type and the high concentration of the second conductive type that are formed in the first conductive semiconductor substrate 1 and the first conductive semiconductor substrate 1 are spaced apart from each other. The semiconductor between the low concentration impurity region 24 of the second conductive type and the low concentration impurity region 24 of the second conductive type formed adjacent to the source region and the drain region respectively on the opposite side of the source region and the drain region 26. On the first gate insulating film 16 formed on both ends of the substrate region, the second gate insulating film 18 formed on the semiconductor substrate region between the first gate insulating film 16 and the first gate insulating film 16. A first conductive layer 17 having a sidewall spacer shape, a second conductive layer 21 formed on the second gate insulating layer 18, and an upper portion of the first conductive layer 17 and the second conductive layer 21. An insulating film sidewall formed on side surfaces of the third conductive layer 22, the first conductive layer 17, and the third conductive layer 22. Pacer 25, and a semiconductor device, characterized in that the punch-through preventing region formed including 20 formed in the second gate insulating film 18, the semiconductor substrate region of the bottom. 제1항에 있어서, 상기 제1게이트절연막(16)과 제2게이트절연막(18)은 서로 다른 두께를 가지는 것을 특징으로 하는 반도체소자.The semiconductor device according to claim 1, wherein the first gate insulating film (16) and the second gate insulating film (18) have different thicknesses. 제1항에 있어서, 상기 제2게이트절연막의 두께는 상기 제1게이트절연막 두께보다 두꺼운 것을 특징으로 하는 반도체소자.The semiconductor device of claim 1, wherein a thickness of the second gate insulating layer is thicker than a thickness of the first gate insulating layer. 제1항에 있어서, 상기 제1도전층(17)과 제2도전층(21) 및 제3도전층(22)이 서로 연결되어 게이트전극을 이루는 것을 특징으로 하는 반도체소자.The semiconductor device according to claim 1, wherein the first conductive layer (17), the second conductive layer (21), and the third conductive layer (22) are connected to each other to form a gate electrode. 제1항에 있어서, 상기 제2게이트절연막(18)은 상기 제1게이트절연막(16)사이의 반도체기판영역상부 및 상기 제1도전층(17)상에 형성됨을 특징으로 하는 반도체소자.The semiconductor device according to claim 1, wherein the second gate insulating film (18) is formed on the semiconductor substrate region between the first gate insulating film (16) and on the first conductive layer (17). 제1항에 있어서, 상기 제3도전층(22)은 살리사이드로 형성하는 것을 특징으로 하는 반도체소자.The semiconductor device according to claim 1, wherein the third conductive layer (22) is made of salicide. 제1도전형의 반도체기판(1)상에 버퍼층(12)을 형성하는 공정과, 상기 버퍼층(12)상에 절연막(13)을 형성하는 공정, 상기 절연막(13)상에 포토레지스트(14)를 도포하는 공정, 상기 포토레지스트(14)를 사진식각공정에 의한 선택적으로 노광 및 현상하여 반도체기판의 게이트전극의 형성될 영역(15) 이외의 영역에만 남기는 공정, 상기 포토레지스트(14)를 마스크로 하여 상기 절연막(13)과 버퍼층(12)을 선택적으로 제거하여 반도체기판의 게이트전극 형성영역을 노출시키는 공정, 상기 포토레지스트를 제거하는 공정, 상기 노출된 반도체기판 영역상에 제1게이트절연막(16)을 형성하는 공정, 상기 제1게이트절연막(16) 및 절연막(13) 전면에 도전물질을 증착한후 에치백하여 상기 절연막(13)의 측면에 스페이서 형태의 제1도전층(17)을 형성하는 공정, 상기 절연막(13) 및 제1도전층(17)를 마스크로 이용하여 상기 제1게이트절연막(16)을 선택적으로 식각하는 공정, 상기 제1게이트절연막(16)의 식각에 의해 노출된 반도체기판영역과 제1도전층(17)상에 제2게이트절연막(18)을 형성하는 공정, 제1도전형 불순물을 저농도로 이온주입하여 제2게이트절연막 하부의 반도체가 판내에 펀치쓰루 방지영역(20)을 형성하는 공정, 상기 제2게이트절연막(18)상에 제2도전층(21)을 형성하는 공정, 상기 제2게이트절연막(18)의 소정부분을 제거하여 상기 제1도정층(17)의 상부를 노출시키는 공정, 상기 노출된 제1도전층(17)상부 및 제2도전층(21) 상에 제3도전층(22)을 형성하는 공정, 상기 절연막 (13) 및 버퍼층(12)을 차례로 제거하는 공정, 제2도전형 불순물을 저농도로 이온주입하여 반도체기판내의 소정영역에 저농도 불순물영역(24)을 형성하는 공정, 상기 제1도전층(17) 및 제3도전층(22) 측면에 절연막 측벽스페이서(25)를 형성하는 공정, 및 제2도전형 불순물을 고농도로 이온주입하여 반도체기판내의 소정영역에 고농도소오스 및 드레인영역(26)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자 제조방법.Forming a buffer layer 12 on the first conductive semiconductor substrate 1, forming an insulating film 13 on the buffer layer 12, and photoresist 14 on the insulating film 13. Applying photoresist, selectively exposing and developing the photoresist 14 by a photolithography process to leave only the regions other than the region 15 to be formed of the gate electrode of the semiconductor substrate, masking the photoresist 14 Selectively removing the insulating layer 13 and the buffer layer 12 to expose the gate electrode forming region of the semiconductor substrate, removing the photoresist, and forming a first gate insulating film on the exposed semiconductor substrate region. 16, a conductive material is deposited on the entire surface of the first gate insulating layer 16 and the insulating layer 13, and then etched back to form a spacer-type first conductive layer 17 on the side surface of the insulating layer 13. Forming step, the insulating film 13 and Selectively etching the first gate insulating layer 16 using the first conductive layer 17 as a mask, the semiconductor substrate region and the first conductive layer exposed by etching of the first gate insulating layer 16 ( A process of forming a second gate insulating film 18 on the second gate insulating film 18 and a process of forming a punch-through prevention region 20 in the plate of the semiconductor under the second gate insulating film by ion implanting the first conductive impurities at low concentration. Forming a second conductive layer 21 on the second gate insulating film 18, removing a predetermined portion of the second gate insulating film 18 to expose an upper portion of the first conductive layer 17, Forming a third conductive layer 22 on the exposed first conductive layer 17 and on the second conductive layer 21, and sequentially removing the insulating layer 13 and the buffer layer 12, and Forming a low concentration impurity region 24 in a predetermined region in a semiconductor substrate by implanting two conductive impurities in low concentration; Forming an insulating film sidewall spacer 25 on the side surfaces of the first conductive layer 17 and the third conductive layer 22, and ion implanting the second conductive impurities at a high concentration to provide a high concentration source to a predetermined region in the semiconductor substrate. And forming a drain region (26). 제7항에 있어서, 상기 버퍼층(12)은 실리콘질화막으로 형성하는 것을 특징으로 하는 반도체소자 제조방법.8. The method of claim 7, wherein the buffer layer is formed of a silicon nitride film. 제7항에 있어서, 상기 절연막(13)은 습식식각에 대해 상기 제1도전층, 제2도전층, 제3도전층과의 식각선택성이 있는 물질로 형성하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 7, wherein the insulating layer is formed of a material having an etching selectivity with respect to the wet etching of the first conductive layer, the second conductive layer, and the third conductive layer. 제7항에 있어서, 상기 절연막(13)은 실리콘산화막으로 형성하는 것을 특징으로 하는 반도체소자 제조방법.8. The method of claim 7, wherein the insulating film is formed of a silicon oxide film. 제7항에 있어서, 상기 제1게이트절연막(16)은 열산화공정에 의해 형성하는 것을 특징으로 하는 반도체소자 제조방법.8. A method according to claim 7, wherein the first gate insulating film (16) is formed by a thermal oxidation process. 제7항에 있어서, 상기 제1도전층(17)은 폴리실리콘으로 형성하는 것을 특징으로 하는 반도체소자 제조방법.8. The method of claim 7, wherein the first conductive layer (17) is formed of polysilicon. 제7항에 있어서, 상기 제2게이트절연막(18)은 열산화공정에 의해 형성하는 것을 특징으로 하는 반도체소자 제조방법.8. A method according to claim 7, wherein the second gate insulating film (18) is formed by a thermal oxidation process. 제7항에 있어서, 상기 제2도전층(21)은 폴리실리콘으로 형성하는 것을 특징으로 하는 반도체소자 제조방법.8. The method of claim 7, wherein the second conductive layer (21) is made of polysilicon. 제7항에 있어서, 상기 제3도전층(22)은 살리사이드로 형성하는 것을 특징으로 하는 반도체소자 제조방법.8. The method of claim 7, wherein the third conductive layer (22) is made of salicide. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR94006925A 1994-04-01 1994-04-01 Semiconductor device and fabrication method KR970006266B1 (en)

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