KR950030279A - Semiconductor device and manufacturing method - Google Patents
Semiconductor device and manufacturing method Download PDFInfo
- Publication number
- KR950030279A KR950030279A KR1019940006925A KR19940006925A KR950030279A KR 950030279 A KR950030279 A KR 950030279A KR 1019940006925 A KR1019940006925 A KR 1019940006925A KR 19940006925 A KR19940006925 A KR 19940006925A KR 950030279 A KR950030279 A KR 950030279A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- conductive layer
- gate insulating
- forming
- region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract 31
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract 21
- 239000012535 impurity Substances 0.000 claims abstract 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract 9
- 238000005530 etching Methods 0.000 claims abstract 7
- 125000006850 spacer group Chemical group 0.000 claims abstract 4
- 239000004020 conductor Substances 0.000 claims abstract 2
- 238000000206 photolithography Methods 0.000 claims abstract 2
- 230000002265 prevention Effects 0.000 claims abstract 2
- 150000002500 ions Chemical class 0.000 claims 2
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- 229920005591 polysilicon Polymers 0.000 claims 2
- 102100026827 Protein associated with UVRAG as autophagy enhancer Human genes 0.000 claims 1
- 101710102978 Protein associated with UVRAG as autophagy enhancer Proteins 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자 및 이의 제조방법에 관한 것으로, 채널길이가 짧은 MOSFET의 숏채널 효과를 개선하기 위한 것이다.The present invention relates to a semiconductor device and a method for manufacturing the same, and to improve the short channel effect of a MOSFET having a short channel length.
본 발명은 제1도전형의 반도체기판상에 버퍼층을 형성하는 공정과, 상기 버퍼층상에 절연막을 형성하는 공정, 상기 절연막상에 포토레지스트를 도포하는 공정, 상기 포토레지스트를 사진식각공정에 의해 선택적으로 노광 및 현상하여 반도체기판의 게이트전극이 형성될 영역 이외의 영역에만 남기는 공정, 상기 포토레지스트를 마스크로 하여 상기 절연막과 버퍼층을 선택적으로 제거하여 반도체기판의 게이트전극 형성영역을 노출시키는 공정, 상기 포토레지스트를 제거하는 공정, 상기 노출된 반도체기판영역상에 제1게이트절연막을 형성하는 공정, 상기 제1게이트절연막 및 절연막 전면에 도전물질을 증착한후 에치백하여 상기 절연막의 측면에 스페이서 형태의 제1도전층을 형성하는 공정, 상기 절연막 및 제1도전층을 마스크로 이용하여 상기 제1게이트절연막을 선택적으로 식각하는 공정, 상기 제1게이트절연막의 식각에 의해 노출된 반도체기판영역과 제1도전층상에 제2게이트절연막을 형성하는 공정, 제1도전형 불순물을 저농도로 이온주입하여 제2게이트절연막 하부의 반도체기판내에 펀치쓰루 방지영역을 형성하는 공정, 상기 제2게이트절연막상에 제2도전층을 형성하는 공정, 상기 제2게이트절연막의 소정부분을 제거하여 상기 제1도전층의 상부를 노출시키는 공정, 상기 노출된 제1도전층 상부 및 제2도전층상에 제3도전층을 형성하는 공정, 상기 절연막 및 버퍼층을 차례로 제거하는 공정, 제2도전형 불순물을 저농도로 이온주입하여 반도체기판내의 소정영역에 저농도 불순물영역을 형성하는 공정, 상기 제1도전층 및 제3도전층 측면에 절연막 측벽스페이서를 형성하는 공정, 및 제2도전형 불순물을 고농도로 이온주입하여 반도체기판내의 소정영역에 고농도 소오스 및 드레인영역을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자 제조방법을 제공한다.The present invention provides a method of forming a buffer layer on a semiconductor substrate of a first conductivity type, forming an insulating film on the buffer layer, applying a photoresist on the insulating film, and selectively etching the photoresist by a photolithography process. Exposing and developing the semiconductor substrate to leave only regions other than the region where the gate electrode is to be formed, and selectively removing the insulating layer and the buffer layer using the photoresist as a mask to expose the gate electrode forming region of the semiconductor substrate. Removing the photoresist; forming a first gate insulating film on the exposed semiconductor substrate region; depositing a conductive material on the entire surface of the first gate insulating film and the insulating film, and then etching back to form a spacer on the side of the insulating film. Forming a first conductive layer, using the insulating film and the first conductive layer as a mask; Selectively etching a gate insulating film, forming a second gate insulating film on the semiconductor substrate region and the first conductive layer exposed by the etching of the first gate insulating film, and ion-implanting a first conductive impurity at low concentration. Forming a punch-through prevention region in the semiconductor substrate under the two-gate insulating film; forming a second conductive layer on the second gate insulating film; and removing a predetermined portion of the second gate insulating film to remove the predetermined portion of the first conductive layer. Exposing the upper portion, forming a third conductive layer on the exposed first conductive layer and on the second conductive layer, sequentially removing the insulating layer and the buffer layer, and ion implanting the second conductive impurities at low concentration. Forming a low concentration impurity region in a predetermined region in the semiconductor substrate, forming an insulating film sidewall spacer on the side surfaces of the first conductive layer and the third conductive layer, and a second conductive type A method of manufacturing a semiconductor device comprising the step of forming a high concentration source and drain region in a predetermined region in a semiconductor substrate by implanting impurities at a high concentration.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제4도는 본 발명의 일실시예에 의한 LDD구조의 MOS트랜지스터 제조방법을 도시한 공정순서도.4 is a process flowchart showing a method of manufacturing an MOS transistor of an LDD structure according to an embodiment of the present invention.
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR94006925A KR970006266B1 (en) | 1994-04-01 | 1994-04-01 | Semiconductor device and fabrication method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR94006925A KR970006266B1 (en) | 1994-04-01 | 1994-04-01 | Semiconductor device and fabrication method |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950030279A true KR950030279A (en) | 1995-11-24 |
KR970006266B1 KR970006266B1 (en) | 1997-04-25 |
Family
ID=19380325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR94006925A KR970006266B1 (en) | 1994-04-01 | 1994-04-01 | Semiconductor device and fabrication method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970006266B1 (en) |
-
1994
- 1994-04-01 KR KR94006925A patent/KR970006266B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR970006266B1 (en) | 1997-04-25 |
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