KR960002743A - Semiconductor device separated by trench and field insulating film and manufacturing method thereof - Google Patents

Semiconductor device separated by trench and field insulating film and manufacturing method thereof Download PDF

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KR960002743A
KR960002743A KR1019940014743A KR19940014743A KR960002743A KR 960002743 A KR960002743 A KR 960002743A KR 1019940014743 A KR1019940014743 A KR 1019940014743A KR 19940014743 A KR19940014743 A KR 19940014743A KR 960002743 A KR960002743 A KR 960002743A
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South Korea
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isolation
trench
region
peripheral circuit
insulating film
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KR1019940014743A
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Korean (ko)
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KR0123730B1 (en
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박태서
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

넓은 비활성영역 및 좁은 비활성영역의 분리절연막을 각각 국부적 산화(Local Oxidation of Silicon : LOCOS)방법 및 트렌치 분리방법에 의해 형성하는 반도체 장치 및 그 소자분리 방법에 관하여 개시한다. 본 발명은 반도체 기판상에 셀 배열부와 주변회로부를 갖는 반도체 장치에 있어서, 상기 주변회로부의 비활성영역은 국부적 산화방법에 의해 형성된 제1분리절연막으로 구성되고, 상기 셀 배열부의 비활성영역은 트렌치 분리방법에 의해 형성된 제2분리절연막으로 구성된 소자분리영역을 갖는 것을 특징으로 한다. 또한, 본 발명은 소자분리영역을 각각 국부적 산화방법 및 트렌치 분리방법을 통해 형성하고 CMP를 실시하므로써 트렌치의 폭이 수 ㎜정도로 커지더라도 넓은 트렌치 영역의 가운데가 접시모양으로 파이는 디싱(dishing)현상이 발생되지 않으며, 이에따라 안정한 소자분리특성을 얻을 수 있고 구조적인 단차를 유발하는 문제점을 해결할 수 있다.Disclosed are a semiconductor device and a device isolation method for forming a wide isolation region and a narrow isolation region by a local oxide of silicon (LOCOS) method and a trench isolation method, respectively. A semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, wherein the inactive region of the peripheral circuit portion is formed of a first isolation insulating film formed by a local oxidation method, and the inactive region of the cell array portion is a trench isolation. And a device isolation region composed of a second isolation insulating film formed by the method. In addition, the present invention forms the device isolation region through a local oxidation method and a trench isolation method, and the piecing is dished out in the shape of a plate in the middle of the wide trench region even when the width of the trench increases to several millimeters by CMP. This does not occur, and thus can obtain stable device isolation characteristics and solve the problem of causing a structural step.

Description

트렌치와 필드절연막으로 소자분리된 반도체 장치 및 그 제조방법Semiconductor device separated by trench and field insulating film and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제13도는 본 발명의 소자분리방법에 의한 실시예를 제조공정순서대로 도시한 단면도이다.13 is a cross-sectional view showing an embodiment according to the device isolation method of the present invention in the manufacturing process sequence.

Claims (8)

반도체 기판상에 셀 배열부와 주변회로부를 갖는 반도체 장치에 있어서, 상기 주변회로부의 비활성영역은 국부적 산화방법에 의해 형성된 제1분리절연막으로 구성되고, 상기 셀 배열부의 비활성영역은 트렌치 분리방법에 의해 형성된 제2분리절연막으로 구성된 소자분리영역을 갖는 것을 특징으로 하는 반도체 장치.A semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, wherein the inactive region of the peripheral circuit portion is formed of a first isolation insulating film formed by a local oxidation method, and the inactive region of the cell array portion is formed by a trench isolation method. And a device isolation region comprising a second isolation insulating film formed thereon. 반도체 기판상에 셀 배열부와 주변회로부가 형성되는 반도체 장치에 있어서, 상기 주변회로부의 비활성 영역은 국부적 산화방법에 의해 제1분리절연막을 형성하고, 상기 셀 배열부의 비활성영역은 트렌치 분리방법에 제2분리절연막을 형성하여 소자분리하는 것을 특징으로 하는 반도체 장치의 소자분리방법.In a semiconductor device in which a cell array portion and a peripheral circuit portion are formed on a semiconductor substrate, an inactive region of the peripheral circuit portion forms a first isolation insulating film by a local oxidation method, and an inactive region of the cell array portion is formed in a trench isolation method. 2. A device isolation method for a semiconductor device, comprising forming a isolation insulating film to separate devices. 반도체 기판상에 셀 배열부와 주변회로부를 갖는 반도체 장치에 있어서, 상기 반도체 기판상에 패드 산화막, 제1질화막 패턴 및 제2질화막을 순차적으로 형성하는 단계 ; 상기 주변회로부에 형성된 상기 제2질화막을 식각하는 단계; 상기 주변회로부의 소정영역에 제1분리절연막을 형성하여 활성영역 및 비활성영역을 정의하는 단계; 상기 주변회로부의 비활성 영역에 형성된 상기 제2질화막 패턴 및 패드 산화막을 식각하는 단계 ; 상기 셀 배열부의 기판을 식각하여 트렌치를 형성하는 단계; 및 상기 셀 배열부의 트렌치에 제2분리절연막을 형성하여 활성영역 및 비활성영역을 정의하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 소자분리방법.A semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, comprising: sequentially forming a pad oxide film, a first nitride film pattern, and a second nitride film on the semiconductor substrate; Etching the second nitride film formed on the peripheral circuit portion; Defining an active region and an inactive region by forming a first isolation insulating layer in a predetermined region of the peripheral circuit portion; Etching the second nitride film pattern and the pad oxide film formed in the inactive region of the peripheral circuit portion; Etching the substrate of the cell array unit to form a trench; And forming a second isolation insulating layer in the trench of the cell array to define an active region and an inactive region. 제3항에 있어서, 상기 제1분리절연막은 국부적 산화방법에 의해 형성되는 것을 특징으로 하는 반도체 장치의 소자분리방법.4. The method of claim 3, wherein the first isolation insulating film is formed by a local oxidation method. 제3항에 있어서, 상기 제2분리절연막을 형성하는 단계후에 상기 기판의 전면에 CMP 또는 반응성 이온식각을 실시하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 소자분리방법.4. The method of claim 3, further comprising performing CMP or reactive ion etching on the entire surface of the substrate after the forming of the second isolation insulating film. 제5항에 있어서, 상기 CMP 또는 반응성 이온식각을 실시하여 상기 제1질화막 패턴이 드러나게 하는 것을 특징으로 하는 반도체 장치의 소자분리방법.The method of claim 5, wherein the first nitride layer pattern is exposed by performing CMP or reactive ion etching. 제6항에 있어서, 상기 CMP 또는 반응성 이온식각을 실시하는 단계후 상기 제1질화막 패턴을 반응성 이온식각법에 의하여 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 소자분리방법.The device isolation method of claim 6, further comprising removing the first nitride film pattern by a reactive ion etching method after performing the CMP or reactive ion etching. 제7항에 있어서, 상기 제1질화막 패턴을 제거하는 단계후 상기 패드산화막을 희석된 HF 용액 또는 B.O.E를 이용하여 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 소자 분리방법.The method of claim 7, further comprising removing the pad oxide film using a diluted HF solution or B.O.E after removing the first nitride film pattern. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940014743A 1994-06-25 1994-06-25 Semiconductor device and its forming method KR0123730B1 (en)

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