KR0139268B1 - Forming method of field oxide in a semiconductor device - Google Patents
Forming method of field oxide in a semiconductor deviceInfo
- Publication number
- KR0139268B1 KR0139268B1 KR1019940038581A KR19940038581A KR0139268B1 KR 0139268 B1 KR0139268 B1 KR 0139268B1 KR 1019940038581 A KR1019940038581 A KR 1019940038581A KR 19940038581 A KR19940038581 A KR 19940038581A KR 0139268 B1 KR0139268 B1 KR 0139268B1
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- Prior art keywords
- oxide film
- film
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- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 239000000243 solution Substances 0.000 claims description 6
- 241000252506 Characiformes Species 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 239000007864 aqueous solution Substances 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 208000024891 symptom Diseases 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자의 필드산화막 형성방법에 관한 것으로, 필드산화막의 체적비 및 단차를 향상시키기 위하여 반구형폴리실리콘막을 이용하여 필드영역의 실리콘기판에 다수의 미세트랜치를 형성한 후 산화공정을 실시하므로써 필드산화막의 단차를 향상시키고 버즈빅의 발생을 최소화시키며 체적비를 증대시킬 수 있도록 한 반도체 소자의 필드산화막 형성방법에 관한 것이다.Field of the Invention The present invention relates to a field oxide film formation method of a semiconductor device. In order to improve the volume ratio and step difference of a field oxide film, a field is formed by using a hemispherical polysilicon film to form a plurality of fine trenches in a silicon substrate in a field region and then performing an oxidation process. The present invention relates to a method of forming a field oxide film of a semiconductor device capable of improving the step height of an oxide film, minimizing the occurrence of buzz big and increasing the volume ratio.
Description
제 1a 내지 제 1g 도는 본 발명에 따른 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도.1A to 1G are cross-sectional views of a device for explaining a method of forming a field oxide film of a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1: 실리콘기판2 및 4: 제 1 및 제 2 질화막1: Silicon substrates 2 and 4: First and second nitride films
3 및 5: 제 1 및 제 2 산화막3 and 5: first and second oxide films
6: 감광막6: photosensitive film
7: HSG막8: 필드산화막7: HSG film 8: field oxide film
9: 미세트랜치9: micro trench
본 발명은 반도체 소자의 필드산화막 형성방법에 관한 것으로, 특히 반구형폴리실리콘막(HSG막)을 이용하여 필드영역의 실리콘기판에 다수의 미세트랜치(Trench)를 형성한 후 산화공정을 실시하므로써 필드산화막의 체적비(Volume ratio) 및 단차(Topology)를 향상시킬 수 있도록 한 반도체 소자의 필드산화막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method for forming a field oxide film of a semiconductor device. In particular, a field oxide film is formed by performing a oxidation process after forming a plurality of fine trenches in a silicon substrate in a field region using a hemispherical polysilicon film (HSG film). The present invention relates to a method for forming a field oxide film of a semiconductor device capable of improving a volume ratio and a topology.
일반적으로 반도체 소자의 제조공정에서 소자와 소자사이를 분리시키기 위하여 소자분리막인 필드산화막을 형성시키는데, 소자가 고집적화됨에 따라 최소한의 소자분리영역유지, 버즈빅의 감소, 표면단차의 완화 및 필드산화막의 전체두께에 대한 실리콘기판의 산화두께를 나타내는 체적비(Volume ratio)의 증가 등이 요구되어진다.In general, in the manufacturing process of a semiconductor device, a field oxide film, which is a device isolation film, is formed in order to separate a device from a device.As the device is highly integrated, a minimum device isolation area, a reduction of buzz big, a surface step reduction, and a field oxide film Increasing the volume ratio indicating the oxide thickness of the silicon substrate with respect to the entire thickness is required.
종래의 필드산화막을 형성하기 위한 LOCOS(Local Oxidation of Silicon) 공정 및 개량된 PBL(Poly Buffered LOCOS) 공정은 버즈빅의 제어 및 필드산화막의 두께 등의 측면에서 256M 이상의 소자에서는 더 이상의 적용이 어려워지는 실정이다. 그러므로 이를 보완하기 위하여 실리콘기판을 리세스(recess)구조로 일정깊이 식각한 후 산화공정을 실시하여 필드산화막을 형성시키는데, 산화공정시 산화제(Oxidant)가 패드산화막 쪽으로 침투되어 들어가 버즈빅이 발생되며, 또한 표면의 단차가 불량하여 후속공정시 어려움이 있다.Conventional Local Oxidation of Silicon (LOCOS) process and improved PBL (Poly Buffered LOCOS) process for forming field oxide film are difficult to apply more than 256M devices in terms of control of Buzzvik and thickness of field oxide film. It is true. Therefore, to compensate for this, the silicon substrate is etched in a recessed structure to a depth, and then an oxidation process is performed to form a field oxide film. During the oxidation process, an oxidant penetrates into the pad oxide film and burjbig is generated. In addition, there is a difficulty in the subsequent process due to the poor level of the surface.
따라서 본 발명은 반구형폴리실리콘막을 이용하여 필드영역의 실리콘기판에 다수의 미세트랜치를 형성한 후 산화공정을 실시하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 필드산화막 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a field oxide film of a semiconductor device which can solve the above-mentioned disadvantages by performing an oxidation process after forming a plurality of fine trenches in a silicon substrate in a field region using a hemispherical polysilicon film. have.
상기한 목적을 달성하기 위한 본 발명은 실리콘기판상에 제 1 질화막, 제 1 산화막, 제 2 질화막 및 제 2 산화막을 순차적으로 형성시킨 후 감광막을 도포하고 소자분리마스크를 이용하여 상기 감광막을 패터닝시키는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 마스크로 이용하여 상기 제 2 산화막 및 제 2 질화막을 순차적으로 식각한 후 상기 감광막을 제거하고 전체면에 반구형폴리실리콘막을 형성시키는 단계와, 상기 단계로부터 상기 반구형폴리실리콘막의 그레인크기를 줄이며 상기 필드영역에만 반구형폴리실리콘막이 잔류되도록 상기 반구형폴리실리콘막을 부분식각하는 단계와, 상기 단계로부터 상기 필드영역의 노출되는 제 1 산화막 및 제 1 질화막을 순차적으로 제거한 다음 노출된 실리콘기판을 식각하여 다수의 미세트랜치를 형성하는 단계와, 상기 단계 후 잔류된 반구형폴리실리콘막과 노출된 제 2 산화막을 제거하고 세정시킨 다음 산화공정을 실시하여 상기 필드영역에 필드산화막을 형성시키는 단계와, 상기 단계로부터 잔류된 제 2 질화막 및 제 1 산화막을 순차적으로 제거한 후 상기 제 1 질화막을 제거시키는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention sequentially forms a first nitride film, a first oxide film, a second nitride film, and a second oxide film on a silicon substrate, and then applies a photosensitive film and patterns the photosensitive film using an element isolation mask. And etching the second oxide film and the second nitride film sequentially using the patterned photoresist film as a mask from the step, removing the photoresist film, and forming a hemispherical polysilicon film on the whole surface. Partially etching the hemispherical polysilicon film such that the grain size of the hemispherical polysilicon film is reduced and the hemispherical polysilicon film remains only in the field region; and sequentially removing the exposed first oxide film and the first nitride film of the field region from the step; The exposed silicon substrate is etched to form a plurality of micro trenches. And removing and cleaning the hemispherical polysilicon film remaining after the step and the exposed second oxide film, followed by an oxidation process to form a field oxide film in the field region, and the second nitride film remaining from the step. And sequentially removing the first oxide film and then removing the first nitride film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 1a 내지 제 1g 도는 본 발명에 따른 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도로서,1A to 1G are cross-sectional views of devices for describing a method of forming a field oxide film of a semiconductor device according to the present invention.
제 1a 도는 실리콘기판(1)상에 제 1 질화막(2), 제 1 산화막(3), 제 2 질화막(4) 및 제 2 산화막(5)을 순차적으로 형성시킨 후 감광막(6)을 도포하고 소자분리마스크(Mask)를 이용하여 상기 감광막(6)을 패터닝한 상태의 단면도인데, 상기 제 1 질화막(2)은 30 내지 100Å, 제 1 산화막(3)은 100 내지 500Å, 제 2 질화막(4)은 1000 내지 2000Å, 그리고 제 2 산화막(5)은 200 내지 1000Å의 두께로 형성시킨다.1a or 1, the first nitride film 2, the first oxide film 3, the second nitride film 4 and the second oxide film 5 are sequentially formed on the silicon substrate 1, and then the photosensitive film 6 is applied. The photosensitive film 6 is patterned using a device isolation mask. The first nitride film 2 is 30 to 100 mW, the first oxide film 3 is 100 to 500 mW, and the second nitride film 4 is formed. ) Is 1000 to 2000 GPa, and the second oxide film 5 is formed to a thickness of 200 to 1000 GPa.
제 1b 도는 상기 패터닝된 감광막(6)을 마스크로 이용하여 상기 제 2 산화막(5), 제 2 질화막(4) 및 제 1 산화막(3)의 일부를 순차적으로 식각한 후 상기 감광막(6)을 제거하고 전체면에 반구형폴리실리콘막(7)을 형성시킨 상태의 단면도인데, 상기 반구형폴리실리콘막(7)의 그레인크기는 400 내지 1000Å 정도인 것을 사용한다.In FIG. 1B, a portion of the second oxide film 5, the second nitride film 4, and the first oxide film 3 is sequentially etched using the patterned photosensitive film 6 as a mask, and then the photosensitive film 6 is etched. It is sectional drawing of the state which removed and the hemispherical polysilicon film 7 was formed in the whole surface, The grain size of the hemispherical polysilicon film 7 is about 400-1000 GPa.
제 1c 도는 상기 반구형폴리실리콘막(7)의 그레인(Grain)크기를 반으로 줄이며 상기 필드영역에만 상기 반구형폴리실리콘막(7)이 잔류되도록 상기 반구형폴리실리콘막(7)을 부분식각한 후 상기 필드영역의 노출되는 제 1 산화막(3) 및 제 1 질화막(2)을 순차적으로 제거한 다음 계속해서 산화막에 대한 식각선택도가 높은 식각방법을 이용하여 노출된 실리콘기판(1)을 식각하여 제 1d 도와 같이 필드영역에 다수의 미세트랜치(9)를 형성시킨 상태의 단면도인데, 상기 미세트랜치(9)의 깊이는 500 내지 2000Å정도가 되도록 식각한다.FIG. 1C illustrates that the hemispherical polysilicon film 7 is partially etched so that the grain size of the hemispherical polysilicon film 7 is reduced in half and the hemispherical polysilicon film 7 remains only in the field region. The first oxide film 3 and the first nitride film 2 exposed in the field region are sequentially removed, and then the exposed silicon substrate 1 is etched by using an etching method having high etching selectivity to the oxide film. As shown in the drawing, a plurality of micro trenches 9 are formed in the field region, and the micro trenches 9 are etched to have a depth of about 500 to 2000 micrometers.
제 1e 도는 잔류된 반구형폴리실리콘막(7)을 제거하고 노출된 제 2 산화막(5)을 피란하(Piranha), 불산수용액(HF), IPA 드라이어(Dryer)를 순차적으로 사용하여 제거시킨 후 세정(Cleaning)시킨 상태의 단면도인데, 상기 피란하 수용액은 H2O2: H2SO4= 1 내지 4 : 1의 비율로 혼합된 용액이며, 온도는 85 내지 160℃인 것을 사용한다.1e or the remaining hemispherical polysilicon film 7 is removed and the exposed second oxide film 5 is removed by sequentially using piranha, hydrofluoric acid solution (HF) and an IPA drier. (Cleaning) It is a cross-sectional view, The piranha aqueous solution is a solution mixed in the ratio of H 2 O 2 : H 2 SO 4 = 1 to 4: 1, the temperature is used is 85 to 160 ℃.
제 1f 도는 950 내지 1100℃의 온도상태에서 산화공정을 실시하여 상기 필드영역에 2000 내지 3500Å 두께의 필드산화막(8)을 형성시킨 상태의 단면도이고, 제 1g 도는 잔류된 제 2 질화막(4) 및 제 1 산화막(3)을 순차적으로 제거하고 상기 제 1 질화막(2)을 피란하, 불산수용액, IPA 드라이어를 순차적으로 사용하여 제거시키므로써 필드산화막(8)의 형성이 완료된 상태인데, 상기 피란하 수용액은 H2O2: H2SO4= 1 내지 4 : 1의 비율로 혼합된 용액이며, 온도는 85 내지 160℃인 것을 사용한다.FIG. 1F is a cross-sectional view of a field oxide film 8 having a thickness of 2000 to 3500 kPa formed in the field region by performing an oxidation process at a temperature of 950 to 1100 ° C., and FIG. 1G is a view of the remaining second nitride film 4 and The formation of the field oxide film 8 is completed by sequentially removing the first oxide film 3 and sequentially removing the first nitride film 2 using piranha, hydrofluoric acid solution and IPA drier. The aqueous solution is a solution mixed in a ratio of H 2 O 2 : H 2 SO 4 = 1 to 4: 1, and a temperature of 85 to 160 ° C is used.
상술한 바와 같이 본 발명에 의하면 반구형폴리실리콘막을 이용하여 필드영역의 실리콘기판에 다수의 미세트랜치를 형성한 후 산화공정을 실시하므로써 필드산화막의 단차를 향상시키고 버즈빅의 발생을 최소화시키며 체적비를 증대시킬 수 있는 탁월한 효과가 있다. 또한 좁은 필드영역에서 스트레스(stress)와 산소플럭스(O2Flux)에 의해 나타나는 필드디닝(thinning)의 현상개선에 효과가 있다.As described above, according to the present invention, a number of fine trenches are formed on the silicon substrate in the field region by using the hemispherical polysilicon film, and the oxidation process is performed to improve the step difference of the field oxide film, to minimize the occurrence of buzz big, and to increase the volume ratio. It has an excellent effect. In addition, there is an effect on improvement of the symptoms in a small area, the stress field (stress) and the oxygen flux (O 2 Flux) field dining (thinning) indicated by the.
Claims (9)
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