JPS62232141A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62232141A JPS62232141A JP7479586A JP7479586A JPS62232141A JP S62232141 A JPS62232141 A JP S62232141A JP 7479586 A JP7479586 A JP 7479586A JP 7479586 A JP7479586 A JP 7479586A JP S62232141 A JPS62232141 A JP S62232141A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- oxide film
- silicon nitride
- nitride film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 30
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 abstract description 14
- 238000007254 oxidation reaction Methods 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 239000007864 aqueous solution Substances 0.000 abstract description 3
- 210000003323 beak Anatomy 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 241000293849 Cordylanthus Species 0.000 description 7
- 239000007789 gas Substances 0.000 description 5
- -1 Boron-gold ions Chemical class 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に8択酸化
によるフィールド酸化膜で、半導体基板上の各素子を互
いに絶縁する素子分離技術に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to an element isolation technique for insulating each element on a semiconductor substrate from each other using a field oxide film using 8-selective oxidation. It is.
本発明は、半導体装置の製造に於いて、素子分離用フィ
ールド酸化膜全選択酸化する際、下地酸化膜を薄く、酸
化マスク用のシリコン窒化at厚くならしめる事業可能
とし、バーズビーク?減少させると共に、素子の1気的
特性全改善したものである。The present invention makes it possible to thin the base oxide film and thicken the silicon nitride film for the oxidation mask when selectively oxidizing the entire field oxide film for element isolation in the manufacture of semiconductor devices, thereby making it possible to make a bird's beak? At the same time, the one-temperature characteristics of the device are completely improved.
従来、例えばMO8半導体装置の製造に於いて素子分離
は、特開昭47−2517号にある様に、シリコン窓化
膜を酸化マスクとしたLocos法と呼ばれる選択酸化
技術が多く用いらnている。Conventionally, for element isolation in the manufacture of MO8 semiconductor devices, for example, a selective oxidation technique called the Locos method using a silicon window film as an oxidation mask has often been used, as described in Japanese Patent Laid-Open No. 47-2517. .
これは第2図の如く、例えばP型シリコン基板21に8
00〜1000Aの下地となる第1のシリコン酸化膜2
2を形成した後、気相底長によるシリコン窒化膜23を
1400〜160QA堆積させ、バターニングしたフォ
トレジスト24t−マスクにし、OF、とOlの混合ガ
スプラズマでドライエツチングし、その後チャンネルス
トッパー25の為のボロン金イオン注入する(第2図−
a)。For example, as shown in FIG.
First silicon oxide film 2 serving as a base of 00 to 1000A
After forming 2, a silicon nitride film 23 of 1400 to 160 QA is deposited depending on the vapor phase bottom length, a patterned photoresist 24t-mask is used, and dry etching is performed using a mixed gas plasma of OF and OL. Boron-gold ions are implanted (Figure 2-
a).
次に水蒸気酸化でiII記シリコン窒化膜25’(マス
クにし選択酸化して約6000−800OA程度のフィ
ールド酸化膜26′に形成しく第2図−b)、その後該
シリコン窒化膜23は熱リン酸で、又第1のシリコン酸
化膜22は弗才でエツチングする(第217−c)。続
いてゲート酸化膜27を形成シ友上に多結4隻シリコン
等でなるゲート電極28をバターニングし、リン全イオ
ン注入しセルファライン的にノース。ドレイン領域29
−z形成しNチャンネルのλ4013)ランシスターが
形成される(第2図−d)。Next, the silicon nitride film 25' described above is formed by water vapor oxidation (selectively oxidized using a mask to form a field oxide film 26' of about 6000 to 800 OA (FIG. 2-b)), and then the silicon nitride film 23 is heated using hot phosphoric acid. Then, the first silicon oxide film 22 is etched by etching (step 217-c). Subsequently, a gate oxide film 27 is formed, and a gate electrode 28 made of multilayer silicon or the like is patterned on top of the gate oxide film 27, and all phosphorous ions are implanted to form a self-aligned gate electrode. drain region 29
-z formation and N-channel λ4013) run sister is formed (Fig. 2-d).
しかしながら、従来の方法に於いては、以下の様な問題
点がある。まずシリコンM化膜25?!−エツチングす
るしJ々、CF4 とOtの混合ガスプラズマのエツチ
ングでは、シリコン酸化膜に対する選択比が12.0程
度の為、下地となる工1のシリコン酸化膜22の厚みは
、シリコン窒化膜25の捧以上の厚みにしなくてはなら
ない事と、シリコン窒化膜のエツチング速度は900A
/分;1度であり、装置のスループット上の問題と、エ
ツチング時間カニ2分以上になるとレジストが変貿して
一般の硫酸ハクリ等が出来なくなる為、厚み[1400
〜1600A程度に規制される。ところがこの偽造で選
択酸化全行うとフィールド酸化膜がシリコン窒化膜の下
にくい込むバーズビークが1.2〜1.5μmVC−達
し、LSIの微細化金山難にしている。However, the conventional method has the following problems. First of all, silicon M film 25? ! - In the case of etching with a mixed gas plasma of CF4 and Ot, the selectivity to the silicon oxide film is about 12.0, so the thickness of the silicon oxide film 22 of process 1, which is the base layer, is equal to that of the silicon nitride film 25. The etching speed of the silicon nitride film is 900A.
/ minute; 1 degree, which causes problems with the throughput of the equipment, and if the etching time exceeds 2 minutes, the resist will be damaged and general sulfuric acid peeling etc. will not be possible, so the thickness [1400
It is regulated to about ~1600A. However, if all selective oxidation is performed with this forgery, the bird's beak in which the field oxide film sinks under the silicon nitride film reaches 1.2 to 1.5 μm VC-, making it difficult to miniaturize LSI.
又下地となる第1のシリコン酸化fi22i薄くし、シ
リコン窒化膜’a−J蓼<する4でバーズビークの長さ
自体は減少出来るものの、シリコン窒化膜のエツチング
の際にシリコン基板がプラズマに直接的されエッチビッ
トや結晶欠陥が生じたシ、シリコン窒化膜自身のストレ
スやホワイトリボン等vctす、トランジスターのゲー
ト耐圧の劣化や接合リークの増大等諸問題【主じてしま
う。Furthermore, although the length of the bird's beak itself can be reduced by thinning the first silicon oxide film serving as the base and by making the silicon nitride film 'a-J' thinner, the silicon substrate is exposed directly to the plasma during etching of the silicon nitride film. This leads to various problems such as etch bits and crystal defects, stress on the silicon nitride film itself, white ribbon, etc., deterioration of transistor gate breakdown voltage, and increase in junction leakage.
L、カるに本発明は、以上の如き欠点をなくし、下地の
シリコン酸化膜を薄く、シリコン窒化膜を厚くする構底
を可能にせしめ、素子特性の同上を図り、バーズビーク
を工す減少させ、微細ルールのLSI?安定供給するも
のである。The present invention eliminates the above-mentioned drawbacks, makes it possible to create a structure in which the underlying silicon oxide film is made thinner and the silicon nitride film is made thicker, thereby improving the device characteristics and reducing the need for bird's beak. , LSI with minute rules? It is a stable supply.
本発明の半導体装置の製造方法は、少なく共、600A
以下の第1シリコン酸化[と1800Å以上のシリコン
窒化膜を形成する工程と、8FaとHeの混合ガスで所
望パターンにドライエツチングした該シ、リコン窒化膜
tマスクに選択酸化する工程と、i+I jieシリコ
ン窒化膜と第1シリコン酸化膜を全面除去する工程と、
活性領域のシリコン表面上に第2シリコン酸化膜全形成
する工程と、u1第2シリコン酸化膜に全面除去後、ゲ
ート酸化膜全形成丁心工程EVする事を特徴とする。The method for manufacturing a semiconductor device of the present invention includes at least 600A
A step of forming a silicon nitride film with a thickness of 1800 Å or more with the following first silicon oxidation process, a step of selectively oxidizing the silicon nitride film t mask by dry etching it into a desired pattern using a mixed gas of 8Fa and He, and a step of selectively oxidizing the silicon nitride film t mask. a step of completely removing the silicon nitride film and the first silicon oxide film;
The method is characterized by a step of completely forming a second silicon oxide film on the silicon surface of the active region, and after removing the entire surface of the second silicon oxide film u1, a step EV is performed to form the entire gate oxide film.
以下、央^例に基づき本発明の詳細な説明する。 Hereinafter, the present invention will be explained in detail based on a central example.
第1図は、本発明によるMO8型半導体装置の製造方法
を示すが、例えばPウェルが形成さfLtシリコン基板
11を熱酸化して約60OAの第1シリコン酸化膜12
を形成しその上に減圧気相w長で1800Åのシリコン
窒化膜13’、(堆積しt後、バターニングしたフオト
レジス)14ivスクにして該シリコン窒化膜13をド
ライエツチングする(第1図−a)。この時、ドライエ
ツチングのφ件は、平行平板のドライエツチング装置で
、SFa とBθの混合ガスを用い、α4tOrrニジ
低い圧力で、SF6の混合比20φす、下でA択比が5
〜4.01でとり、エッチ速度も140OA1分以上で
行った。この時従来の様に、レジスト表面が変スしたり
、シリコン基板にエッチピント等は認められなかった。FIG. 1 shows a method of manufacturing an MO8 type semiconductor device according to the present invention. For example, a P-well is formed and a first silicon oxide film 12 of about 60 OA is thermally oxidized on a fLt silicon substrate 11.
A silicon nitride film 13' having a length of 1800 Å (photoresist which was deposited and buttered after being deposited) is dry etched on the silicon nitride film 13' in a reduced pressure vapor phase (Fig. 1-a). ). At this time, the φ condition of dry etching is a parallel plate dry etching device, using a mixed gas of SFa and Bθ, a pressure lower than α4tOrr, a mixture ratio of SF6 of 20φ, and an A selection ratio of 5.
-4.01, and the etch rate was also 140OA for 1 minute or more. At this time, unlike conventional methods, no deformation of the resist surface or etch focus on the silicon substrate was observed.
尚15は、ボロンをイオン注入したチャンネルストッパ
ー領域である。次にシリコン窒化膜137マスクにして
高圧水蒸気酸化炉で800OAのフィールド酸化膜16
を成長しく第1図−b)、その後熱リン酸でシリコン窒
化膜15を弗酸水溶液で第1シリコン酸化膜12?除去
し活性領域のシリコン表面?露出させてから、1000
’C酸素雰囲気で熱酸化して400〜600Aの第2シ
リコン酸化膜10i形成させ(第1図−c)、再度弗酸
水溶液で該第2シリコン酸化膜10を除去する(11図
−d)。この酸化トエッチングにL9ホワイトリボンが
除去され、又史に賃化の時、塩素を含む酸素雰囲気を用
いれば、活性領域の積層欠陥が減少する事が確認された
。次に40OAのゲートα化膜1711−成長し、多+
結dムシリコンでなるゲート1m1B?rパターニング
後、リンtイオン注入しセルファライン的にソース、ド
レイン197形尻しく第1図−e)、Nffン、ネルの
mob)ランシスター?製造しfc0上aじの工捏r経
て製造され7CMO8半導体装置Iよ、バーズビークが
18μm程度と減少し九上に、ゲート耐圧の劣化や接せ
リークの問題もみられなρ為った。又この他に、下地の
第1シリコン酸化膜1200〜400Aでシリコン窒化
膜の厚みt2000Aのものも本発明の工at経て製造
したが、バーズビークは05μm8度であシ、電気的特
性も問題なく、微細MO8)ランシスターを製造出来念
。尚本発明の実抱例では、NチャンネルのMOS半導体
装置について説明し次が、2手ヤンネルやC!MO8半
導体装置でも工く、又ゲート構造が、シリサイド、サリ
サイドでも適用出来る。Note that 15 is a channel stopper region into which boron ions are implanted. Next, using a silicon nitride film 137 mask, a field oxide film 16 of 800 OA was formed in a high-pressure steam oxidation furnace.
After growing the silicon nitride film 15 using hot phosphoric acid (FIG. 1-b), the first silicon oxide film 12 is grown using a hydrofluoric acid aqueous solution. Remove active area silicon surface? After exposing, 1000
A second silicon oxide film 10i of 400 to 600 A is formed by thermal oxidation in an oxygen atmosphere (Fig. 1-c), and the second silicon oxide film 10 is removed again with a hydrofluoric acid aqueous solution (Fig. 11-d). . It was confirmed that the L9 white ribbon was removed by this oxide etching, and that stacking faults in the active region were reduced if an oxygen atmosphere containing chlorine was used during etching. Next, a gate alpha film 1711 of 40OA is grown, and a multilayer film 1711 is grown.
1m1B gate made of DM silicon? After r patterning, phosphorous ions are implanted to form the source and drain 197 shapes in a self-aligned manner (Fig. The 7CMO8 semiconductor device I was manufactured through the same engineering process as above, and the bird's beak was reduced to about 18 μm, and there were no problems with gate breakdown voltage deterioration or contact leakage. In addition, a silicon nitride film with a thickness of 2000 A and a first silicon oxide film as the base of 1200 to 400 A was also manufactured through the process of the present invention, but the bird's beak was 05 μm and 8 degrees, and there were no problems with the electrical characteristics. Fine MO8) Successful production of Run Sister. In the practical example of the present invention, an N-channel MOS semiconductor device will be explained, and next, a two-way MOS semiconductor device and a C! An MO8 semiconductor device can also be fabricated, and the gate structure can also be applied to silicide or salicide.
本発明の効果は、SF、とnuのガスによりエツチング
されtシリコン窒化膜倉用いて1択酸化し、ゲート酸化
膜を形成する前にシリコン表面?酸化、エツチングする
事に工す、バーズビークtα5μm以下に減少させ、電
気的特性を同上させ、簡単な工程で、微細な半導体装置
の供給が出来る。The effect of the present invention is that the silicon nitride film is selectively oxidized by etching with SF and nu gases, and the silicon surface is selectively oxidized before forming the gate oxide film. Through oxidation and etching, the bird's beak tα can be reduced to 5 μm or less, the electrical characteristics can be improved, and fine semiconductor devices can be supplied with a simple process.
第1図a −eは、本発明の半導体装置の製造工程を示
す概略断面図。
巣2図a−dは、従来の半導体装置の製造工程で示す概
略断面図。
10・・・第2シリコン酸化膜
11.21・・・シリコン基板
12.22・・・第1シリコン酸化膜
15.25・・・シリコン窒化膜
14.24・・・フォトレジスト
15.25・・・チャンネルストッパー16 、26・
・・フィールド酸化膜
17.27・・・ゲート酸化膜
18.28・・・ゲート電極
19.29・・・ンース、ドレイン
以上1A to 1E are schematic cross-sectional views showing the manufacturing process of the semiconductor device of the present invention. Figures 2a to 2d are schematic cross-sectional views showing the manufacturing process of a conventional semiconductor device. 10... Second silicon oxide film 11.21... Silicon substrate 12.22... First silicon oxide film 15.25... Silicon nitride film 14.24... Photoresist 15.25...・Channel stopper 16, 26・
...Field oxide film 17.27...Gate oxide film 18.28...Gate electrode 19.29...More than source and drain
Claims (1)
ン酸化膜と1800Å以上のシリコン窒化膜を形成する
工程と、SF_6とHeの混合ガスで所望パターンにド
ライエッチングした該シリコン窒化膜をマスクに選択酸
化する工程と、前記シリコン窒化膜と第1シリコン酸化
膜を全面除去する工程と、活性領域のシリコン表面に第
2シリコン酸化膜を形成する工程と、該第2シリコン酸
化膜を全面除去後、ゲート酸化膜を形成する工程を有す
る事を特徴とする半導体装置の製造方法。Step of forming at least a first silicon oxide film with a thickness of 600 Å or less and a silicon nitride film with a thickness of 1800 Å or more on a semiconductor substrate, and select the silicon nitride film dry-etched into a desired pattern with a mixed gas of SF_6 and He as a mask. a step of oxidizing, a step of completely removing the silicon nitride film and the first silicon oxide film, a step of forming a second silicon oxide film on the silicon surface of the active region, and after completely removing the second silicon oxide film, A method for manufacturing a semiconductor device, comprising the step of forming a gate oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7479586A JPS62232141A (en) | 1986-04-01 | 1986-04-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7479586A JPS62232141A (en) | 1986-04-01 | 1986-04-01 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62232141A true JPS62232141A (en) | 1987-10-12 |
Family
ID=13557594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7479586A Pending JPS62232141A (en) | 1986-04-01 | 1986-04-01 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62232141A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6509279B2 (en) * | 2000-07-24 | 2003-01-21 | Tokyo Ohka Kogyo Co., Ltd. | Methods for processing a coating film and for manufacturing a semiconductor element |
-
1986
- 1986-04-01 JP JP7479586A patent/JPS62232141A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6509279B2 (en) * | 2000-07-24 | 2003-01-21 | Tokyo Ohka Kogyo Co., Ltd. | Methods for processing a coating film and for manufacturing a semiconductor element |
US6649534B2 (en) | 2000-07-24 | 2003-11-18 | Tokyo Ohka Kogyo Co., Ltd. | Methods for processing a coating film and for manufacturing a semiconductor element |
US6664199B2 (en) | 2000-07-24 | 2003-12-16 | Tokyo Ohka Kogyo Co., Ltd. | Coating liquid for forming a silica group coating film having a small dielectric constant |
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