JPH036815A - Manufacture of semiconductor device and semiconductor device - Google Patents
Manufacture of semiconductor device and semiconductor deviceInfo
- Publication number
- JPH036815A JPH036815A JP14252489A JP14252489A JPH036815A JP H036815 A JPH036815 A JP H036815A JP 14252489 A JP14252489 A JP 14252489A JP 14252489 A JP14252489 A JP 14252489A JP H036815 A JPH036815 A JP H036815A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- semiconductor
- pattern
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 239000002344 surface layer Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 24
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 12
- 239000000377 silicon dioxide Substances 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法及び半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.
従来の技術
第3図は従来の多結晶シリコン膜のパターン形成方法を
示す工程図である。第3図(a)に示すように段差を有
するシリコン基板20上に形成された多結晶シリコン膜
21上にレジストパターン22を形成する。その後、レ
ジストパターン22をマスクとしてレジストパターン2
2かない領域の多結晶シリコン1llj21をエツチン
グして除去することにより、レジストパターン22と同
じパターンを有する多結晶シリコン膜21を形成する。BACKGROUND OF THE INVENTION FIG. 3 is a process diagram showing a conventional method of patterning a polycrystalline silicon film. As shown in FIG. 3(a), a resist pattern 22 is formed on a polycrystalline silicon film 21 formed on a silicon substrate 20 having steps. After that, the resist pattern 22 is used as a mask.
The polycrystalline silicon film 21 having the same pattern as the resist pattern 22 is formed by etching and removing the polycrystalline silicon 1llj21 in the area where the resist pattern 22 does not exist.
この時のエツチングは微細なパターン形成が困難である
ウェットエツチングの代わりに、微細なパターン形成が
可能なドライエツチングを用いている(第3図(b))
。At this time, instead of wet etching, which is difficult to form fine patterns, dry etching is used, which can form fine patterns (Figure 3 (b)).
.
発明が解決しようとする課題
しかし、従来のドライエツチングを用いたバタ−ン形成
方法によれば、プラズマを構成するイオンや電子の衝撃
によって、被エツチング膜の下地にダメージを与え、そ
のため結晶欠陥23が発生する。また微細パターンの形
成のため、異方性エツチングを行なうと段差側壁部にエ
ツチング残り24が発生するという問題があった。Problems to be Solved by the Invention However, according to the conventional pattern forming method using dry etching, the underlying layer of the film to be etched is damaged by the bombardment of ions and electrons constituting the plasma, resulting in crystal defects 23 occurs. Further, when anisotropic etching is performed to form a fine pattern, there is a problem in that etching residue 24 is generated on the side wall portion of the step.
本発明は上述の課題に鑑みて試されたもので、ダメージ
が発生することなく、パターン形成が可能な半導体装置
の製造方法及び半導体装置を提供することを目的とする
。The present invention has been attempted in view of the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device that allow pattern formation without causing damage.
課題を解決するための手段
本発明は、上述の課題を解決するため、半導体基板上に
半導体膜を形成後、前記半導体膜上に不純物を含む絶縁
膜を形成する工程と、前記絶縁膜をバターニングした後
、酸化性雰囲気で熱処理することにより前記絶縁膜下の
半導体膜を全て第1の酸化膜に変換し、前記絶縁膜のな
い領域の半導体膜表面層だけを第2の酸化膜に変換する
工程とを備えたものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a step of forming a semiconductor film on a semiconductor substrate, then forming an insulating film containing impurities on the semiconductor film, and converting the insulating film into butter. After the coating, all of the semiconductor film under the insulating film is converted into a first oxide film by heat treatment in an oxidizing atmosphere, and only the surface layer of the semiconductor film in the area where there is no insulating film is converted into a second oxide film. It is equipped with a process of.
作用
本発明は上述の構成によって、不純物を含む絶縁膜下の
半導体膜中に前記絶縁膜から不純物が拡散し、また酸化
種が前記絶縁膜中を容易に拡散するため、前記絶縁膜下
の半導体膜は絶縁膜のない領域下の半導体膜に比べ酸化
レートが大きい。そのため、絶縁膜下の半導体膜が全て
酸化されるのに対して、絶縁膜のない領域における半導
体膜はその表面層のみが酸化され、ダメージが発生する
ことなく絶縁膜のパターンを反転させたパターンを有す
る半導体膜を形成することが可能となる。Effect of the present invention With the above-described structure, impurities are diffused from the insulating film into the semiconductor film under the insulating film containing impurities, and oxidizing species are easily diffused into the insulating film. The film has a higher oxidation rate than the semiconductor film below the region without the insulating film. Therefore, while the entire semiconductor film under the insulating film is oxidized, only the surface layer of the semiconductor film in areas without the insulating film is oxidized, resulting in a pattern that reverses the pattern of the insulating film without causing damage. It becomes possible to form a semiconductor film having the following properties.
実施例
(実施例1)
第1図は本発明の第1の実施例における多結晶シリコン
膜のパターン形成方法を示す工程図である。以下、第1
図を用いて本発明による多結晶シリコン膜のパターン形
成方法を説明する。Example (Example 1) FIG. 1 is a process diagram showing a method for forming a pattern of a polycrystalline silicon film in a first example of the present invention. Below, the first
A method of patterning a polycrystalline silicon film according to the present invention will be explained with reference to the drawings.
第1図(a)に示すように、シリコン基板1上にCVD
法により多結晶シリコン膜2を堆積し、更に多結晶シリ
コン膜2上にCVD法により不純物、例えばボロン、砒
素、リン等を含む絶縁膜3である二酸化シリコンを堆積
する。次に通常のフォトリングラフィとエツチングを用
いて不純物を含む絶縁膜3をバターニングする(第1図
(b))。次に酸化性を有する雰囲気、例えば酸素ガス
雰囲気中で熱処理を行なう。熱処理は電気炉を用いて7
00〜l!00°Cの温度で数分から数時間行なう。そ
の結果、第1図(C)に示すように不純物を含む絶縁膜
3下の多結晶シリコン膜2だけが完全に二酸化シリコン
4に変化し、絶縁膜3のない領域の多結晶シリコン膜2
は、その表面層のみが二酸化シリコン4に変化し、その
下では酸化されずに多結晶シリコン膜2が残こる。As shown in FIG. 1(a), CVD is applied onto a silicon substrate 1.
A polycrystalline silicon film 2 is deposited by a method, and silicon dioxide, which is an insulating film 3 containing impurities such as boron, arsenic, phosphorus, etc., is further deposited on the polycrystalline silicon film 2 by a CVD method. Next, the impurity-containing insulating film 3 is patterned using conventional photolithography and etching (FIG. 1(b)). Next, heat treatment is performed in an oxidizing atmosphere, for example, an oxygen gas atmosphere. Heat treatment is performed using an electric furnace.
00~l! It is carried out for several minutes to several hours at a temperature of 00°C. As a result, as shown in FIG. 1(C), only the polycrystalline silicon film 2 under the insulating film 3 containing impurities is completely changed to silicon dioxide 4, and the polycrystalline silicon film 2 in the area without the insulating film 3
Only the surface layer changes to silicon dioxide 4, and the polycrystalline silicon film 2 remains without being oxidized underneath.
以上のように、ダメージが発生することなく絶縁膜のパ
ターンを反転させたパターンを有する半導体膜を形成す
るができる。As described above, a semiconductor film having a pattern that is an inversion of the pattern of an insulating film can be formed without causing damage.
(実施例2)
第2図は本発明の第2の実施例におけるMOSトランジ
スタの工程断面図である。以下、第2図を用いて本発明
によるMOSトランジスタの製造方法を説明する。(Example 2) FIG. 2 is a process cross-sectional view of a MOS transistor in a second example of the present invention. Hereinafter, a method for manufacturing a MOS transistor according to the present invention will be explained using FIG.
第2図(a)に示すようにシリコン基板10上に通常の
方法を用いて、分離酸化膜11によって分離された領域
にソース−ドレイン領域を形成する不純物領域f2とゲ
ート電極I3を有するMOSトランジスタを形成する。As shown in FIG. 2(a), a MOS transistor having an impurity region f2 forming a source-drain region and a gate electrode I3 in a region separated by an isolation oxide film 11 is formed on a silicon substrate 10 using a conventional method. form.
またゲート電極13の上側部には酸化膜I4を形成する
。次に第2図(b)に示すように、ソース・ドレインI
2に接するように、多結晶シリコン15を堆積する。次
いで不純物を含んだ絶縁膜IBを堆積しバターニングす
る(第2図(C))。このバターニングは、ソース・ド
レイン12上に、配線とのコンタクト穴17を開孔する
ことを兼ねている。Further, an oxide film I4 is formed on the upper side of the gate electrode 13. Next, as shown in FIG. 2(b), the source/drain I
Polycrystalline silicon 15 is deposited so as to be in contact with 2. Next, an insulating film IB containing impurities is deposited and patterned (FIG. 2(C)). This patterning also serves to form a contact hole 17 on the source/drain 12 to connect to the wiring.
次に実施例1で述べたように酸化性を有する雰囲気中で
熱処理を行うことで、その結果、不純物を含む絶縁膜1
B下の多結晶シリコン膜15だけが完全に二酸化シリコ
ン18に変化し、絶縁膜16のない領域の多結晶シリコ
ン膜15は、その表面層のみが二酸化シリコン18に変
化し、その下では酸化されずに多結晶シリコン膜15が
残こる。絶縁物1Bが不純物として、ボロンとリンをそ
れぞれ5〜8%含む二酸化シリコンの場合、熱処理温度
が850℃以上で流動し第2図(d)のような形状とな
る。次に、弗酸系溶液を用いたウェットエツチング工程
によって第2図(e)に示すように、ソース・ドレイン
12に接する多結晶シリコン15の表面に形成された二
酸化シリコン18を除去する。続いて配線19を形成す
る(第2図(f))。Next, as described in Example 1, by performing heat treatment in an oxidizing atmosphere, as a result, the insulating film 1 containing impurities
Only the polycrystalline silicon film 15 under B completely changes to silicon dioxide 18, and only the surface layer of the polycrystalline silicon film 15 in the area where there is no insulating film 16 changes to silicon dioxide 18, and the area below it is not oxidized. However, the polycrystalline silicon film 15 remains. If the insulator 1B is silicon dioxide containing 5 to 8% each of boron and phosphorus as impurities, it will flow at a heat treatment temperature of 850° C. or higher, resulting in a shape as shown in FIG. 2(d). Next, as shown in FIG. 2(e), the silicon dioxide 18 formed on the surface of the polycrystalline silicon 15 in contact with the source/drain 12 is removed by a wet etching process using a hydrofluoric acid solution. Subsequently, wiring 19 is formed (FIG. 2(f)).
以上のように、本発明の半導体装置ではソース・ドレイ
ンに接する多結晶シリコンを、下地シリコン表面の性質
を劣化させずに形成でき、しかも配線とソース−ドレイ
ンを接続するコンタクト穴のバターニングと、多結晶シ
リコンのバターニングを1回のフォト工程によって自己
整合的に形成できる。また不純物を含んだ絶縁膜をその
まま配線とトランジスタの絶縁膜として利用し、特に、
その絶縁膜がボロン、リンを数パーセント含んだ二酸化
シリコンの場合、多結晶シリコンの酸化の工程で平坦化
され、配線の断線が生じにくい構造となる。さらに配線
とソース・ドレインの接触面積が、多結晶シリコン膜に
よって増加し、低抵抗のコンタクト構造となる。As described above, in the semiconductor device of the present invention, polycrystalline silicon in contact with the source/drain can be formed without deteriorating the properties of the underlying silicon surface, and the contact hole connecting the wiring and the source/drain can be patterned. Patterning of polycrystalline silicon can be formed in a self-aligned manner by a single photo process. In addition, insulating films containing impurities can be used as they are for wiring and transistor insulating films, and in particular,
If the insulating film is made of silicon dioxide containing a few percent of boron and phosphorus, it will be flattened during the oxidation process of polycrystalline silicon, resulting in a structure that is less prone to disconnections. Furthermore, the contact area between the wiring and the source/drain is increased by the polycrystalline silicon film, resulting in a contact structure with low resistance.
発明の詳細
な説明したように本発明によれば、不純物を含む絶縁体
をバターニングして用いることで、多結晶シリコン膜の
酸化レートを制御し多結晶シリコン膜のパターンを形成
でき、下地が単結晶シリコン基板の場合、その表面形状
・結晶性を劣化させず、その実用的効果は大きなもので
ある。DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by buttering an insulator containing impurities, it is possible to control the oxidation rate of a polycrystalline silicon film and form a pattern of the polycrystalline silicon film. In the case of a single-crystal silicon substrate, its surface shape and crystallinity do not deteriorate, and its practical effects are great.
第1図は本発明の第1の実施例における多結晶シリコン
膜のパターン形成方法を示す工程図、第2図は本発明の
第2の実施例におけるMOSトランジスタの工程断面図
、第3図は従来の多結晶シリコン膜のパターン形成方法
を示す工程図である。
1.10・・・シリコン基板、2,15・・・多結晶シ
リコン膜、3,1lli・・・不純物を含む絶縁膜、4
.18・・・二酸化シリコン膜。FIG. 1 is a process diagram showing a method of patterning a polycrystalline silicon film in a first embodiment of the present invention, FIG. 2 is a process cross-sectional view of a MOS transistor in a second embodiment of the present invention, and FIG. FIG. 3 is a process diagram showing a conventional method for forming a pattern of a polycrystalline silicon film. 1.10...Silicon substrate, 2,15...Polycrystalline silicon film, 3,1lli...Insulating film containing impurities, 4
.. 18...Silicon dioxide film.
Claims (2)
上に不純物を含む絶縁膜を形成する工程と、前記絶縁膜
をパターニングした後、酸化性雰囲気で熱処理すること
により前記絶縁膜下の半導体膜を全て第1の酸化膜に変
換し、前記絶縁膜のない領域の半導体膜表面層だけを第
2の酸化膜に変換する工程を備えた半導体装置の製造方
法。(1) After forming a semiconductor film on a semiconductor substrate, forming an insulating film containing impurities on the semiconductor film, and after patterning the insulating film, heat treatment is performed in an oxidizing atmosphere so that the area under the insulating film is A method for manufacturing a semiconductor device, comprising the steps of converting all of the semiconductor film into a first oxide film, and converting only the surface layer of the semiconductor film in a region where the insulating film is not present into a second oxide film.
、前記MOSトランジスタを互いに電気的に分離する分
離領域と、前記MOSトランジスタのソースまたはドレ
インを形成する不純物領域とを接続する配線との間に前
記MOSトランジスタのゲート及び前記分離領域上まで
広がる半導体膜パターンとを有し、前記半導体膜パター
ン以外の領域にある不純物を含む絶縁膜の端部と前記半
導体膜パターン端部とが自己整合的に形成されることを
特徴とする半導体装置。(2) between a MOS transistor formed on a semiconductor substrate, an isolation region that electrically isolates the MOS transistors from each other, and a wiring that connects an impurity region that forms the source or drain of the MOS transistor; A gate of a MOS transistor and a semiconductor film pattern extending above the isolation region, wherein an end of an insulating film containing impurities in a region other than the semiconductor film pattern and an end of the semiconductor film pattern are formed in a self-aligned manner. A semiconductor device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14252489A JPH036815A (en) | 1989-06-05 | 1989-06-05 | Manufacture of semiconductor device and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14252489A JPH036815A (en) | 1989-06-05 | 1989-06-05 | Manufacture of semiconductor device and semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH036815A true JPH036815A (en) | 1991-01-14 |
Family
ID=15317362
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14252489A Pending JPH036815A (en) | 1989-06-05 | 1989-06-05 | Manufacture of semiconductor device and semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH036815A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5358881A (en) * | 1993-05-19 | 1994-10-25 | Hewlett-Packard Company | Silicon topography control method |
-
1989
- 1989-06-05 JP JP14252489A patent/JPH036815A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5358881A (en) * | 1993-05-19 | 1994-10-25 | Hewlett-Packard Company | Silicon topography control method |
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