JPS5923476B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5923476B2 JPS5923476B2 JP53085789A JP8578978A JPS5923476B2 JP S5923476 B2 JPS5923476 B2 JP S5923476B2 JP 53085789 A JP53085789 A JP 53085789A JP 8578978 A JP8578978 A JP 8578978A JP S5923476 B2 JPS5923476 B2 JP S5923476B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- polycrystalline silicon
- silicon substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- -1 nitrogen ions Chemical class 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 34
- 229910052681 coesite Inorganic materials 0.000 description 17
- 229910052906 cristobalite Inorganic materials 0.000 description 17
- 239000000377 silicon dioxide Substances 0.000 description 17
- 235000012239 silicon dioxide Nutrition 0.000 description 17
- 229910052682 stishovite Inorganic materials 0.000 description 17
- 229910052905 tridymite Inorganic materials 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
この発明は、２層ゲート構造を有する半導体装置に関し
、特に２層ゲート間の耐圧および動作速度に優れた半導
体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a two-layer gate structure, and more particularly to a method for manufacturing a semiconductor device with excellent breakdown voltage and operating speed between two-layer gates.
最近、２層ゲート構造を有する半導体装置、特に半導体
記憶装置がある。Recently, there have been semiconductor devices, particularly semiconductor memory devices, having a two-layer gate structure.
この種の半導体装置は、例えば、次のような構造をもつ
ている。第１図ａ−ｃは２層ゲート構造を有する半導体
記憶装置の代表的な例をその主要部の製造工程に従つて
示したものである。This type of semiconductor device has, for example, the following structure. FIGS. 1a to 1c show a typical example of a semiconductor memory device having a two-layer gate structure according to the manufacturing process of its main parts.
以下これによつて従来の半導体装置を説明する。一導電
型の単結晶シリコン基板１の上に絶縁層であるＳｉＯ２
膜２を形成し、この上に第１導体層である多結晶シリコ
ン膜３を所定のパターンに成形する（第１図ａ）。Hereinafter, a conventional semiconductor device will be explained based on this. An insulating layer of SiO2 is formed on a single-crystal silicon substrate 1 of one conductivity type.
A film 2 is formed, and a polycrystalline silicon film 3 serving as a first conductor layer is formed on the film into a predetermined pattern (FIG. 1a).
その後、多結晶シリコン膜３をマスクとしてＳｉＯ２膜
２の露出部分を除去すると、多結晶シリコン膜３の端部
の下に、ＳｉＯ２膜２の切り込み部が形成される（第１
図ｂ）。その後、高温、酸化性雰囲気中で多結晶シリコ
ン膜３を酸化し、ＳｉＯ２膜４を形成する。次に、Ｓｉ
Ｏ２膜４の上に、第２導体層となるべき多結晶シリコン
膜５を形成した後、この多結晶シリコン膜５を所望のパ
ターンに成形し、ＳｉＯ２膜４の露出部分を除去して部
分的に単結晶シリコン基板１の表面６を露出させ、、こ
の部分にソースまたはドレインとなるべき不純物拡散層
Ｔを形成する（第１図ｃ）。この後、単結晶シリコン基
板１、ソースおよびドレインとなる不純物拡散層Ｔ、多
結晶シリコン膜３、５にそれぞれ周知の方法で電極部を
設けて半導体装置が完成する。上記のような製造工程に
よると、多結晶シリコン膜３を酸化して形成されるＳｉ
Ｏ２膜４の単結晶シリコン基板１上での厚さｄと、多結
晶シリコン膜３上での厚さをとの比１がせいぜい１．５
〜２．０ぐらいであり、例えばｄ二１０００λの場合、
を＝１５００〜２０００λ程度になることが知られてい
る。Thereafter, when the exposed portion of the SiO2 film 2 is removed using the polycrystalline silicon film 3 as a mask, a notch in the SiO2 film 2 is formed under the edge of the polycrystalline silicon film 3 (first
Figure b). Thereafter, the polycrystalline silicon film 3 is oxidized in an oxidizing atmosphere at a high temperature to form a SiO2 film 4. Next, Si
After forming a polycrystalline silicon film 5 to become a second conductor layer on the O2 film 4, the polycrystalline silicon film 5 is formed into a desired pattern, and the exposed portion of the SiO2 film 4 is removed to partially form the polycrystalline silicon film 5. The surface 6 of the single-crystal silicon substrate 1 is exposed, and an impurity diffusion layer T to become a source or drain is formed in this portion (FIG. 1c). Thereafter, electrode portions are provided on the single crystal silicon substrate 1, the impurity diffusion layers T serving as sources and drains, and the polycrystalline silicon films 3 and 5, respectively, by well-known methods to complete the semiconductor device. According to the above manufacturing process, Si formed by oxidizing the polycrystalline silicon film 3
The ratio 1 between the thickness d of the O2 film 4 on the single crystal silicon substrate 1 and the thickness on the polycrystalline silicon film 3 is at most 1.5.
~2.0, for example, in the case of d21000λ,
is known to be approximately 1500 to 2000λ.
このため、多結晶シリコン膜３，５が重なる部分の面積
が大きなＩＣチツプになれば、２層ゲート間の浮遊容量
によつて、動作速度は大きく影響されることになる。そ
こで、動作速度を向上させるためには、第１図ｃにおけ
るｔを大きくする必要がある。従来、このｔを大きくし
ようとすると、同時に酸化されるｄも大きくなり、半導
体装置の特性に悪影響がでてくるという欠点があつた。
また、第１導体層である多結晶シリコン膜３の端部にお
ける段差に、第２導体層である多結晶シリコン膜５がか
ぶさる部分において、２層ゲート間にリーク電流が発生
しやすい部分ができ、耐圧不良を起すこともよく知られ
ている。この発明は上記のような欠点を除去するために
なされたもので、従来の製造工程を大幅に変えることな
く、２層ゲート間距離、すなわち、第１導体層である多
結晶シリコン膜上のＳｉＯ２膜の厚さのみを大きくして
浮遊容量を減らし、半導体装置の動作速度を向上させる
とともに、２層ゲート間の絶縁耐圧をも向上させる方法
を提供するものである。Therefore, if the IC chip has a large area where the polycrystalline silicon films 3 and 5 overlap, the operating speed will be greatly affected by the stray capacitance between the two-layer gates. Therefore, in order to improve the operating speed, it is necessary to increase t in FIG. 1c. Conventionally, when trying to increase t, d, which is oxidized, also increases, which has the disadvantage of adversely affecting the characteristics of the semiconductor device.
In addition, in the part where the polycrystalline silicon film 5, which is the second conductive layer, overlaps the step at the end of the polycrystalline silicon film 3, which is the first conductive layer, there is a part where leakage current is likely to occur between the two layer gates. It is also well known that this can cause breakdown voltage failure. This invention was made to eliminate the above-mentioned drawbacks, and without significantly changing the conventional manufacturing process, the distance between the two-layer gate, that is, the SiO2 on the polycrystalline silicon film that is the first conductor layer, The present invention provides a method of reducing stray capacitance by increasing only the thickness of the film, improving the operating speed of a semiconductor device, and also improving the dielectric breakdown voltage between two-layer gates.
以下この発明の一実施例を第２図ａ−ｆによつて説明す
る。単結晶シリコン基板１１上に、高温、酸化性雰囲気
中でＳｉＯ２膜１２を厚さ７００〜１５００λ成長させ
る。An embodiment of the present invention will be described below with reference to FIGS. 2a to 2f. An SiO2 film 12 is grown to a thickness of 700 to 1500 λ on a single crystal silicon substrate 11 at a high temperature in an oxidizing atmosphere.
その上に、第１導体層となるべき多結晶シリコン膜１３
を５０００〜７５００λ成長させる。次に、ホトレジス
ト１４を用いて、多結晶シリコン膜１３上に所望のパタ
ーンを形成する（第２図ａ）。その後、ＣＦ４等のガス
プラズマあるいはフツ酸系エツチング液中において、ホ
トシジスト１４を保護膜として多結晶シリコン膜１３の
露出部分をエツチングする（第２図ｂ）。その後、窒素
をイオン化、加速してイオン注入を行う。なお、その際
の加速エネルギーは、多結晶シリコン膜１３の露出部分
を除去した下の部分のＳｉＯ２膜１２と単結晶シリコン
基板１１の界面に最大の窒素濃度をもつような値に設定
する。そして、打込み量は１０１７〜１０１８個／Ｃｄ
程度とする。その後、１０００〜１２００℃の高温で処
理すれば、ＳｉＯ２膜１２と単結晶シリコン基板１１と
の界面にはＳｉ原子とＮ原子の複合体の薄い窒化シリコ
ン層１５が形成される（第２図ｃ）。次にホトレジスト
１４を除去した後、９５０〜１０００℃の酸化性雰囲気
中で酸化する。この際、複合体の窒化シリコン層１５が
あるために、単結晶シリコン基板１１上のＳｉＯ２膜１
２は、成長速度が抑制され、第１導体層となるべき多結
晶シリコン膜１３上のＳｉＯ２膜１６のみが成長する。
こうして窒化シリコン層１５が酸化されてＳｉＯ２膜１
６に変わるまで酸化を続ければ、多結晶シリコン膜１３
上に成長したＳｉＯ２膜１６の厚みｍと窒化シリコン層
１５が形成された単結晶シリコン基板１１上のＳｉＯ２
膜ｎとの比ｗは７〜１０となつて、従来の方法に比べ上
記膜厚比は非常に大きくなる（第２図ｄ）。この後、多
結晶シリコン膜１７を形成して第２導体層となし、この
多結晶シリコン膜１７を所望のパターンに成形した後、
ＳｉＯ２膜１６の露出部分を除去して単結晶シリコン基
板１１の表面１１′を露出させる（第２図ｅ）。その後
、ソースまたはドレインとなるべき不純物拡散層１８を
形成する。（第２図ｆ）。こうした後、単結晶シリコン
基板１１．ソースおよびドレインとなる不純物拡散層１
８、第１導体層となる多結晶シリコン膜１３、第２導体
層となる多結晶シリコン膜１７にそれぞれ周知の方法で
電極部を設けて半導体装置が完成する。以上説明したよ
うにこの発明は、２層ゲート部分の第１導体層となる多
結晶シリコン膜上に形成されるＳｉＯ２膜の厚みをこの
ＳｉＯ２膜が単結晶シリコン基板上に形成される部分の
厚みより大きく形成するようにしたので、２層ゲート間
の浮遊容量が大幅に減少することにより動作速度が向上
するとともに、２層ゲート間の絶縁耐圧にもすぐれた半
導体装置が得られる利点がある。On top of that, a polycrystalline silicon film 13 to become the first conductor layer
is grown to 5000-7500λ. Next, a desired pattern is formed on the polycrystalline silicon film 13 using a photoresist 14 (FIG. 2a). Thereafter, the exposed portion of the polycrystalline silicon film 13 is etched in a gas plasma such as CF4 or in a hydrofluoric acid etching solution, using the photocidist 14 as a protective film (FIG. 2b). Thereafter, nitrogen is ionized and accelerated to perform ion implantation. Incidentally, the acceleration energy at this time is set to a value such that the maximum nitrogen concentration is obtained at the interface between the SiO2 film 12 and the single crystal silicon substrate 11 in the lower part where the exposed part of the polycrystalline silicon film 13 has been removed. And the implantation amount is 1017~1018 pieces/Cd
degree. Thereafter, by processing at a high temperature of 1000 to 1200°C, a thin silicon nitride layer 15 made of a composite of Si atoms and N atoms is formed at the interface between the SiO2 film 12 and the single crystal silicon substrate 11 (Fig. 2c). ). Next, after removing the photoresist 14, it is oxidized in an oxidizing atmosphere at 950 to 1000°C. At this time, since the composite silicon nitride layer 15 is present, the SiO2 film 1 on the single crystal silicon substrate 11 is
In No. 2, the growth rate is suppressed, and only the SiO2 film 16 on the polycrystalline silicon film 13, which is to become the first conductor layer, grows.
In this way, the silicon nitride layer 15 is oxidized and the SiO2 film 1
If oxidation is continued until it changes to 6, the polycrystalline silicon film 13
The thickness m of the SiO2 film 16 grown thereon and the SiO2 on the single crystal silicon substrate 11 on which the silicon nitride layer 15 is formed.
The ratio w to the film n is 7 to 10, and the film thickness ratio is much larger than in the conventional method (FIG. 2d). After this, a polycrystalline silicon film 17 is formed to serve as a second conductor layer, and after forming this polycrystalline silicon film 17 into a desired pattern,
The exposed portion of the SiO2 film 16 is removed to expose the surface 11' of the single crystal silicon substrate 11 (FIG. 2e). Thereafter, an impurity diffusion layer 18 to become a source or drain is formed. (Fig. 2 f). After this, the single crystal silicon substrate 11. Impurity diffusion layer 1 that becomes source and drain
8. Electrode portions are provided on the polycrystalline silicon film 13, which will become the first conductor layer, and the polycrystalline silicon film 17, which will become the second conductor layer, respectively, by a well-known method, and the semiconductor device is completed. As explained above, in the present invention, the thickness of the SiO2 film formed on the polycrystalline silicon film which becomes the first conductor layer of the two-layer gate portion is the thickness of the portion where this SiO2 film is formed on the single crystal silicon substrate. Since it is made larger, there is an advantage that the stray capacitance between the two-layer gates is significantly reduced, thereby improving the operating speed and providing a semiconductor device with excellent dielectric strength between the two-layer gates.
第１図ａ−ｃは従来の２層ゲート構造の半導体装置の製
造工程を説明するための断面図、第２図ａ−ｆはこの発
明の一実施例を示す２層ゲート構造の半導体装置の製造
工程を説明するための断面図である。
図中、１１は単結晶シリコン基板、１２，１６はＳｌＯ
２膜、１３，１７は多結晶シリコン膜、１４はホトレジ
スト、１５は窒化シリコン層、１８は不純物拡散層であ
る。1a-c are cross-sectional views for explaining the manufacturing process of a conventional semiconductor device with a two-layer gate structure, and FIGS. 2a-f are cross-sectional views of a semiconductor device with a two-layer gate structure showing an embodiment of the present invention. It is a sectional view for explaining a manufacturing process. In the figure, 11 is a single crystal silicon substrate, 12 and 16 are SlO
2, 13 and 17 are polycrystalline silicon films, 14 is a photoresist, 15 is a silicon nitride layer, and 18 is an impurity diffusion layer.
Claims (1)
この絶縁層に接して多結晶シリコン膜を成長させた後、
所定部分を除去して第１導体層を形成する工程と、前記
多結晶シリコン膜の除去部分に窒素イオン注入を行い、
前記絶縁層と単結晶シリコン基板の界面に薄い窒化シリ
コン層を形成する工程と、酸化性雰囲気中で酸化し、前
記単結晶シリコン基板上の絶縁膜厚に比べ前記第１導体
層上に膜厚の大きい絶縁膜を形成する工程と、前記第１
導体層上および単結晶シリコン基板上の絶縁膜上に第２
導体層を形成する工程とを含むことを特徴とする半導体
装置の製造方法。1 After forming an insulating layer on a single conductivity type single crystal silicon substrate and growing a polycrystalline silicon film in contact with this insulating layer,
forming a first conductor layer by removing a predetermined portion; and implanting nitrogen ions into the removed portion of the polycrystalline silicon film;
forming a thin silicon nitride layer at the interface between the insulating layer and the single-crystal silicon substrate; and oxidizing in an oxidizing atmosphere to increase the thickness of the silicon nitride layer on the first conductor layer compared to the thickness of the insulating layer on the single-crystal silicon substrate. a step of forming an insulating film with a large
A second layer is formed on the conductor layer and the insulating film on the single crystal silicon substrate.
A method for manufacturing a semiconductor device, comprising the step of forming a conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53085789A JPS5923476B2 (en) | 1978-07-13 | 1978-07-13 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53085789A JPS5923476B2 (en) | 1978-07-13 | 1978-07-13 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5512767A JPS5512767A (en) | 1980-01-29 |
| JPS5923476B2 true JPS5923476B2 (en) | 1984-06-02 |
Family
ID=13868647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53085789A Expired JPS5923476B2 (en) | 1978-07-13 | 1978-07-13 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923476B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56160062A (en) * | 1980-05-14 | 1981-12-09 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS57197911A (en) * | 1981-05-29 | 1982-12-04 | Sanyo Electric Co Ltd | Schmitt circuit |
| JPS5850771A (en) * | 1981-09-21 | 1983-03-25 | Hitachi Ltd | High integration rom enable of rewriting and manufacture thereof |
| JPS59188962A (en) * | 1983-04-12 | 1984-10-26 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JP2503621B2 (en) * | 1989-01-23 | 1996-06-05 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH0613344U (en) * | 1992-07-15 | 1994-02-18 | 東京電力株式会社 | Adapter for drawing out the ground wire of the power cable connection |
-
1978
- 1978-07-13 JP JP53085789A patent/JPS5923476B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5512767A (en) | 1980-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6072268A (en) | Method of producing bipolar transistor structure | |
| JPH04102317A (en) | Manufacture of semiconductor device | |
| US4497108A (en) | Method for manufacturing semiconductor device by controlling thickness of insulating film at peripheral portion of element formation region | |
| JPS5923476B2 (en) | Manufacturing method of semiconductor device | |
| JPS5843912B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| EP0023528A1 (en) | Double diffused transistor structure and method of making same | |
| KR910000020B1 (en) | Manufacture of semiconductor device | |
| JPS6252950B2 (en) | ||
| JPH06302826A (en) | Insulated gate field-effect transistor and preparation thereof | |
| JPH0298939A (en) | Manufacture of semiconductor device | |
| JPH02130852A (en) | Semiconductor device | |
| JPS5828734B2 (en) | hand tai souchi no seizou houhou | |
| JPH02153534A (en) | Manufacture of semiconductor device | |
| KR100265824B1 (en) | Method for fabricating transistor of ldd structure | |
| JPH0252859B2 (en) | ||
| JPS6115372A (en) | Semiconductor device and manufacture thereof | |
| JPH11354650A (en) | Semiconductor device and its manufacture | |
| JPH0429224B2 (en) | ||
| JPH02134827A (en) | Semiconductor device and its manufacture | |
| JPS6077460A (en) | Manufacture of semiconductor device | |
| JPH06196635A (en) | Semiconductor device and manufacture thereof | |
| JPH06188259A (en) | Manufacture of semiconductor device | |
| JPS61129869A (en) | Manufacture of semiconductor device | |
| JPH0240921A (en) | Manufacture of bipolar transistor | |
| JPH07161963A (en) | Manufacture of quantum wire structure |