JPS5850771A - High integration rom enable of rewriting and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture an EPROM which can erase by ultraviolet rays with less leak of accumulated charges even when formed in high integration with a good reprducibility, by forming the film thickness of oxide films formed from the surface of a gate to the both sides equivalent to the gate oxide film one or over that particularly in the periphery of a floating gate. CONSTITUTION:Of the SiO2 film 14 formed from the surface of each gate to source and drain regions, the film thickness of the periphery 14a of the floating gate FG in particular is formed equivalent to the film thickness (500Angstrom or less) of the gate oxide film 1 or larger, e.g. 800-1,000Angstrom . This oxide film 14 is adhered approximately in evenness and has a very good film quality. The growth of the SiO2 film 14 on the surface of each gate is performed by applying an oxidation treatmet, e.g. at 1,000 deg.C for 30min in dry O2. Thereat, simultaneously, the film thickness of the SiO2 film 14a in the periphery of the floating gate FG becomes much larger than that of the gate oxide film 1. Therefore, even when contriving to the high integration of an EPROM by forming a gate length or channel length and a gate oxide film thickness respectively to small sizes, leak decrease resulting in the good retention of charges.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a rewritable collection $lJt OM (R@a
dOnly Malnory), especially ipROM that can be erased by ultraviolet rays (j[1rable and P
rogrammable Jio M) and its manufacturing method.

As gpRoM becomes more highly integrated, there is a tendency for the channel length of the gate-type field effect semiconductor transistor constituting the memory cell to become shorter and the gate oxide film to become thinner. In this IPROM, charge is injected from the substrate side to the floating gate by a write voltage to the control gate, and the shoulder # of this injection is used to distinguish whether information has been written or not. Regarding this injected charge, (1) the amount of injected charge depends on the area of the floating gate. (2) The injected charge leaks through the gate oxide film over time. (3) The amount of leakage depends on the thickness of the gate oxide film, and the number of square meters per unit area is constant! ill! It's cold.

As a result of conducting a study on IIPROM with such a two-layer gate structure, the present inventor discovered that in order to improve the retention characteristics of the injected charge, the surface of each polysilicon gate was oxidized to 810*g The following problems were found when covering with That is, in a B device with a relatively large channel length, for example, 5μ, the amount of stored charge is large and most of the leakage of the injected charge is caused by the gate oxidation 1111 as shown in FIG.
Since the leakage occurs in the vertical direction 2 through the floating gate IFG, the leakage from the periphery 5 of the floating gate IFG is negligible or negligible. The amount of leakage has increased relatively and can no longer be ignored. This tendency becomes more pronounced as the thickness of the gate oxide film 1 increases.In this case, either the above table 1111m or etching is performed after the two-layer polysilicon layer and the underlying gate oxide film are etched into the same shape. The grown aiol film 4
(Floating Game) It was found that the ridges around the PG became distorted and became very thin. As a result, the amount of charge injected into the floating gate (PC) by applying the oatic write voltage t to the polysilicon control gate, or the amount of leakage through the 810 snow in the periphery 5, which has a small film thickness, further increases. The memory retention function will further deteriorate.

Therefore, the present invention provides an IPROM with less leakage of accumulated charges due to high integration, and with
The purpose of this paper is to provide a method for fabricating OMi with good reproducibility.

To achieve this objective, according to the present invention, an oxide film is formed from the surface of the gate to both sides of the gate.
i% is equal to or higher than that of the gate oxide film around the floating gate. In other words, the inventors have found that the charge leakage as described above is almost constant at the periphery of the floating gate regardless of the channel length, but in the case of a distorted oxide film as described above, the leakage of charge becomes larger than that of the gate oxide film. This was discovered for the first time, and in order to prevent this, the thickness of the oxide film around the floating gate was actively increased.

Such an oxide film structure cannot be achieved using conventional manufacturing processes, and has only become possible based on the method of the present invention.

That is, according to the method of the present invention, when patterning the first and second semiconductor films uniformly stacked on the gate oxide film into substantially the same shape, the gate oxide film is not etched at all;
In this state, surface oxidation is applied so that the surface of each gate is almost uniform with the gate oxide film on both sides! Since C and K continue to grow new oxide NI4, a relatively thick oxide film is left in the vicinity of the floating gate due to the new oxide film and the gate oxide film.

Hereinafter, embodiments of the invention will be explained in detail with reference to the drawings.

The IIIFROM according to this embodiment is of the ultraviolet erasing type, and the seventh memory cell has a polygon film on the −i plane of the PfJ semiconductor substrate 3, as shown in FIGS. The silicon floating gate (IFG and control gate) OG is shouldered, and on both sides of this 21-gate are source or train regions +N! Jl regions 6.7.8.9... are selectively formed and are companions. However, it is important to note that among the aiQs films 14 formed from the e-plane of each gate to the source and drain regions, the thickness of the aiQs film 14, especially the surrounding area 14 of the floating gate (FG), is 4 times larger than the 1ll of smell (below SOON); example 8
00~1ooo; Moreover, this oxidized film [14] does not have a distorted shape as shown in FIG. 1, but is more or less uniformly deposited and has a very good film quality.

In this way, especially control games) 81 around PG
0! By making the gate oxide film 14a thicker than the gate oxide film WX1, the leakage of charges injected (storage tank) into the gate oxide film PG due to writing can be made smaller than the leakage (3t-gate oxide film IK). In other words, by making the film thicker and of better quality in the periphery, the insulation isolation effect there can be improved dramatically, and the charge retention function can be dramatically improved. Therefore, even if the gate length or channel length and gate oxide film thickness are miniaturized to achieve high integration of the 1PROM, leakage can be reduced and charge retention can be performed well, so that the requirements for high integration can be satisfactorily met. Satisfied Nine IFROMt
Can be provided.

Note that, for example, a write circuit is also not shown in FIG. 2 as a peripheral circuit section. In the figure, 1G and 11 are T-type regions that are the source or train regions, and 12 is a polysilicon gate. In addition, 15 is a field 5iol film, 16#N
+ type channel stopper, 17 is a phosphosilicate glass film, 18 is data (bit li), 19 is a source electrode, 2
0 is a train electrode.

Next, the manufacturing process of the structure shown in FIG. 1 and FIG. 2 will be explained with reference to FIG.

First, as shown in FIG. 5A, a P-type channel stopper 16 is formed on the entire surface of the silicon substrate 3 using known ion implantation technology, selective oxidation technology, and gate oxidation technology.
1011[15, Gate oxidation Il! 1) Then, polysilicon is deposited on the entire surface using a known chemical vapor deposition technique (OVD), followed by a known phosphorus treatment 3! lt
After this, the polysilicon film 12, 21 is patterned by a known photoetching method to form a polysilicon film 12, 21 in a predetermined shape as shown in FIG. 5B.
The remaining knife.

Next, as shown in FIG. 50, polysilicon Ps12.21
The thin surface is heat treated in an oxidizing atmosphere.

G22 was grown, and then a second layer of polysilicon M23TX was applied over the entire surface using OVD.

Next, as shown in FIG. 5D, the photoresist 24 coated on the entire surface is patterned by known exposure and drying processes, and this is used as a neat mask to form the polysilicon film 23 in the memory area.
．． 81 (h[22, the polysilicon film 21'i is etched into substantially the same shape to form each control gate OG1 floating gate) IFGt-, respectively. This etching is particularly suitable for plasma etching (anti-broad gas is e.g. 0I
The etched gate oxide film 1 is not etched at all, leaving only a portion of the gate oxide film 1 remaining.

Next, as shown in FIG. 511c, the new photoresist 25'f, the polysilicon M23 in the peripheral circuit area, and the underlying EliO3 film are etched in the same manner as above.

Next, as shown in FIG. 51F, the photoresist is removed and the entire surface is irradiated with an ion beam 26 of arsenic or phosphorous, and an ion implantation layer 6. is selectively formed on both sides of each polysilicon gate.
7.8.9.10.11f: Form respectively. These ion implantation layers are formed in a self-aligned manner so that each polysilicon gate acts as a mask.

Then, as shown in Fig. 5G, for example, at 1000°C for 30 minutes,
By applying oxidation treatment (light oxidation) in dry Os, a 14tP gill film is grown on the false surface of each gate.

At this time, 8103 also grows on the gate oxide film in the region where FG and OG are not present, and the film thickness becomes 5ill or 800 to IGOOA, which is sufficiently large. In other words, the film thickness of aiosl[141L around the floating gate IPG is much larger than that of the gate oxide film 1, and the above oxidation conditions make it uniform in shape and of good quality.

Then, as shown in Figure 5H, apply one layer of phosphosilicate glass J [17
And the underlying JiiOsMl[e is patterned by known photoetching to form each contact hole. Then, apply aluminum to the entire surface using a known vacuum evaporation technique, and form 18 to 20 fathoms of aluminum electrodes or wiring as shown in Figure 2 by photo-etching. 810, the henchman! Since the film can be formed almost uniformly,
It is possible to create an older brother PROM with high integration (channel length, for example, 3 μm or less) and excellent storage retention function with good reproducibility. No, in the process shown in Figure 5α, floating game) P
Since GK already contains a predetermined concentration of phosphorus in the phosphorus treatment, the growth rate of 1iio on the surface of No.
In order to grow new, floating game) IFG
810t of the periphery 14a [the thickness is sufficiently larger than the gate oxide film as a whole].

The nine embodiments of the present invention have been described above, and further modifications can be made to the embodiments described above based on the technical idea of the present invention.

For example, 81 (hJl[
From the purpose of reducing the film thickness alJ-rit* of 14&, there is no problem even if the film thickness is the same as that of gate oxidation M1. In this case as well, compared to the case of the bear t1s rhinoceros mentioned in the '-i' diagram, -
storage retention is much better. In terms of process, the ion implantation shown in FIG. 51' can also be performed after the light oxidation shown in FIG. 5G. In this case, 810. on the relatively thick source and drain regions 6-9. The implantation energy can be selected to allow ions to pass through the membrane.

[Brief explanation of drawings]

The drawings are for explaining the present invention.6 Figure 1 shows the leakage pattern when light oxidation is performed using the conventional method.
FIG. 2 is a cross-sectional view of the main part of the IaFROM according to the embodiment of the present invention, and FIG. 3 is a schematic cross-sectional view of the main part of the memory cell according to the embodiment.
t--D schematic cross-sectional view, FIG. 4 is a plan view of the memory cell section,
FIG. 5 is a cross-sectional view showing the manufacturing method of the structure shown in FIG. In addition, in the symbols shown in the drawings, 1 is a gate oxidizer;
2 and 3 are leakage of injected charge, 1 oxide 5to = film, 14a
t; EIiO1% IFG around floating gate
is a bloating gate, and OG- is a control gate. Agent Patent Attorney Usui 1) Li ^ Figure 1 Figure 3 ゛・ Figure 4

Claims (1)

[Claims] 1. A rewritable high-integration device consisting of a memory cell supporting a gate structure consisting of a floating gate and a control gate, and having a microscopic channel length and gate oxide film thickness. In the ROM, among the oxide films formed from the surface of each gate to the surface K of the source and drain regions, the thickness of at least the portion T existing around the floating gate is equal to or greater than the gate oxide film. The film thickness is set to riiJIlp or more, so that the charge injected into the floating gate during writing is difficult to leak from the peripheral part of the floating gate through the oxidized alt-. Structure W, rewritable, highly integrated RO that makes leakage a beast
M0 2, a thin oxide film is formed on the whole surface of the semiconductor substrate by oxidation.
Ia is sequentially laminated on this thin oxide film with an I-interval insulation M interposed between the first semiconductor film, the second semiconductor film, and tcn et al. 21, and after this lamination. ζ of successively patterning the second semiconductor film, interlayer insulating film, and first semiconductor film into substantially the same shape to form a control gate and a floating gate, respectively; a step of growing a new oxide film almost uniformly continuous with the thin oxide film on both sides of the gates by oxidizing the entire surface; A method for manufacturing a rewritable highly integrated ROM, comprising the steps of: selectively forming source and drain regions by introducing impurities into the substrate at certain locations.