JPH05347416A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To shift the floating gates and the control gates of a non-volatile memory from each other with a high accuracy. CONSTITUTION:A first insulating film 2, a first semiconductor layer 3, a second insulating film 4, a second semiconductor layer 5, a first positive-type resist layer 6 and a second positive-type resist layer 7 are successively built up on a semiconductor substrate 1. The first resist layer 6 and the second resist layer 7 are exposed and patterned. The second semiconductor layer 5, the second insulating film 4 and the first semiconductor layer 3 are selectively removed by using the first resist layer 6 and the second resist layer 7 as masks to form floating gates 3a and control gates 5a. One conductivity type impurities are implanted into the substrate 1 by using the control gates 5a as a mask. Then a thermal treatment is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a flash EEPROM (Electric).
ally Erasable Programmable Read Only Memory). In recent years, a nonvolatile memory (EEPRO) that electrically writes and erases data in byte units
Among M), a flash EEPROM that can collectively erase data is drawing attention.

A flash EEPROM stores data by accumulating electric charges in a floating gate. When writing data, the source voltage is increased to inject high-energy electrons into the floating gate, and when erasing data, the drain voltage is increased. Then, the data is erased at once by the tunneling operation between the floating gate and the drain.

However, when a high electric field is applied between the drain and the substrate, band-to-band tunneling occurs between the valence band and the conduction band. This band-to-band tunneling causes a band-to-band tunneling current to flow from the drain to the substrate. Since all elements of the chip are erased at the same time in the flash EEPROM, a large current flows in the chip due to this band-to-band tunneling current, which is a problem.

[0004]

2. Description of the Related Art In a flash EEPROM, an electric field concentrated in the vicinity of a drain junction may be relaxed in order to suppress a band-to-band tunneling current. For this purpose, there is a method of making the slope of the impurity distribution in the lateral direction of the drain gentle. Conventionally, the impurity distribution of the source and drain is LDD.
(Lightly Doped Drain) structure was used to relax the electric field.

However, when the LDD structure is used, the electric fields on the source side (during a write operation) and the drain side (during an erase operation) are relaxed at the same time. When the electric field on the source side is relaxed during the writing operation, it is possible to suppress high energy of the electrons and the efficiency of writing deteriorates. Therefore, in order to relax the electric field only on the drain side, the floating gate is formed longer on the drain side than the control gate,
A source / drain is formed by ion implantation using the control gate as a mask. At this time, if the implantation energy is optimized, some of the ions implanted in the floating gate extending longer than the control gate penetrate through the floating gate. As a result, a diffusion layer having a low impurity concentration is formed in a region where the floating gate and the control gate do not overlap each other, so that the electric field on the drain side is relaxed.

A method of manufacturing the floating gate and the control gate in such a manner as described above is described in, for example, Japanese Patent Laid-Open No. 3-181175. Hereinafter, a method of manufacturing the conventional flash EEPROM will be described with reference to FIG. 4A to 4D are process sectional views of a conventional flash EEPROM, in which the same reference numerals indicate the same components.

See FIG. 4 (a). A field oxide film 22 is formed on the p-type silicon substrate 21 by known LOCOS separation (selective oxidation) at appropriate intervals, and a gate oxide film 23 having a thickness of 70 to 120Å is formed on the entire surface by thermal oxidation. Then, a polycrystalline silicon layer 24 having a thickness of 500 to 1000Å for forming a floating gate is laminated by CVD (Chemical Vapor Deposition) method, and impurities such as phosphorus are thermally diffused in the polycrystalline silicon layer 24. Although not shown, the polycrystalline silicon layer 24 is etched according to the length of the floating gate by a known photolithography technique. Further, a gate oxide film 25 and a polycrystalline silicon layer 26 for forming a control gate are sequentially laminated on the polycrystalline silicon layer 24 by thermal oxidation, and an impurity such as phosphorus is heated on the polycrystalline silicon layer 24. To spread.

See FIG. 4 (b). After patterning a resist 27 on the polycrystalline silicon layer 26 using photolithography to determine the source / drain spacing,
The polycrystalline silicon layer 26 and the gate oxide film 25 are sequentially etched to form the control gate 260 and expose the polycrystalline silicon layer 24. Next, the resist 28 is patterned on the exposed polycrystalline silicon layer 24 in order to form the extended portion 24a on the side where the drain is to be formed again by using the photolithography technique, and the polycrystalline silicon is formed using the resists 27 and 28 as a mask. After the silicon layer 24 and the gate oxide film 23 are sequentially etched to form the floating gate 240 and the surface of the p-type silicon substrate 21 is exposed, the resists 27 and 28 are removed.

See FIG. 4 (c). Control gate 26
Arsenic is ion-implanted into the p-type silicon substrate 21 using 0 as a mask. The conditions at this time are energy 120 keV,
The dose is about 5 × 10 ¹⁵ cm ^-2 . As a result, arsenic is injected at a high concentration into the first drain region 29 and the source region 30 where the floating gate 240 does not exist, and the portion (second drain region 31) corresponding to the extending portion 24a of the floating gate 240 is formed. The arsenic is implanted at a low concentration through the thin polycrystalline silicon layer 24 and the gate oxide film 23.

See FIG. 4 (d). The p-type silicon substrate 21 is heat-treated at 950 ° C. for about 20 minutes to diffuse the arsenic implanted in the p-type silicon substrate 21, and the first drain diffusion layer 290 is formed in the first drain region 29 as the source. A source diffusion layer 300 is formed in the region 30, and a second drain diffusion layer 310 is formed in the second drain region 31.

Next, PSG (Phospho
A Silicate Glass) film 33 is stacked, a contact hole 34 is formed at an appropriate position, an aluminum wiring 35 is provided, and a passivation film 36 is further stacked so as to cover the entire surface.

[0012]

However, in the conventional manufacturing method described above, in order to shift the floating gate and the control gate, the resist 27 is formed to form the control gate 260 as shown in FIG. 4B. A mask for patterning, a mask for patterning the resist 28 in order to form the extended portion 24a of the floating gate, and their alignment are required. Due to device miniaturization, even when the gate length is about 0.5 μm, the right end of the resist 28 reaches the gate oxide film 23 beyond the right end of the resist 27 due to variations in alignment when patterning the resist 28. However, there is a problem that a desired floating gate cannot be obtained.

Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which the floating gate and the control gate can be accurately displaced.

[0014]

The above problems can be solved by the following method of manufacturing a semiconductor memory device. That is, in a non-volatile memory that includes a memory cell having a structure including a floating gate and a control gate, injects electrons into the floating gate when writing data, and emits electrons from the floating gate when erasing data, the semiconductor substrate 1 A step of forming a first insulating film 2 thereon, a step of forming a first semiconductor layer 3 on the first insulating film 2, and a second insulating film 4 on the first semiconductor layer 3. Forming the second semiconductor layer 5 on the second insulating film 4, and forming the second semiconductor layer 5 on the second insulating film 4.
A step of forming a first positive resist 6 on the first positive resist 6, a step of forming a second positive resist 7 on the first positive resist 6, the first positive resist 6 and the second positive resist 6. Exposing and patterning the positive resist 7 of
Using the first positive resist 6 and the second positive resist 7 as a mask, the second semiconductor layer 5, the second insulating film 4, and the first semiconductor layer 3 are selectively removed. Then, the step of forming the floating gate 3a and the control gate 5a, the step of introducing an impurity of one conductivity type into the semiconductor substrate 1 using the control gate 5a as a mask, and the step of heat treatment thereafter And a method of manufacturing a semiconductor memory device.

[0015]

In the present invention, a mask having a three-layer structure as shown in FIG. 3 (a) is used, and as shown in FIG. 2 (b), a first positive resist 6 and a second positive resist 7 are used. The following effects are obtained by exposing the layer resist. That is, in the mask having the three-layer structure, light is transmitted where Ta and Cr are removed, half light is transmitted where Ta is removed and Cr remains, and light is not transmitted where Ta and Cr remain. Further, the material of the positive resist is selected so that the second positive resist 7 is exposed to light and the first positive resist 6 is not exposed to half the amount of light.

Then, the first positive resist 6 and the second positive resist 7 are patterned at the same time, and the polycrystalline silicon layers 3 and 5 are etched by using the patterned two-layer resist as a mask. The gate 5a, the floating gate 3a, and the extension 3b of the floating gate can be formed at the same time.

Therefore, a mask for patterning the resist for forming the control gate,
A mask for patterning a resist for forming the extended portion 3b of the floating gate and its alignment are not required, the number of steps can be reduced, and the floating gate and the control gate can be accurately displaced. ..

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to an embodiment with reference to the drawings. One embodiment of the present invention is shown in FIGS. FIG. 1A is a plan view of a flash EEPROM according to the present invention. FIG. 1B is a sectional view of the flash EEPROM according to the present invention.
The AA cross section of (a) is shown.

2A to 2D are process sectional views for explaining one embodiment of the present invention. In the figure, 1 is a p-type silicon substrate, 2 is a gate oxide film (SiO ₂ ), 3a is a floating gate,
Reference numeral 3b is an extension portion, 4 is a gate oxide film (SiO ₂ ), 5a is a control gate, 6 is a first positive resist, 7 is a second positive resist, 8 is a first drain diffusion layer, and 9 is a drain.
Indicates a source diffusion layer, and 10 indicates a second drain diffusion layer. In the drawings, the same reference numerals indicate the same.

FIG. 3A is a cross-sectional view showing a mask having a three-layer structure. In the figure, the lower layer is a glass plate with a thickness of 1 mm, the middle layer is Ta with a thickness of 1000 Å, and the upper layer is Cr with a thickness of 200 Å. Is. The lengths of the arrows D0, D1 and D2 indicate the intensity of light. FIG. 3B is a graph in which the vertical axis represents the remaining amount of resist (Å) and the horizontal axis represents the amount of light (mJ / cm ² ). The first positive resist 6 and the second positive resist 7 are shown. Shows the photosensitivity characteristics of.

Next, a flash EE according to one embodiment of the present invention
A method of manufacturing the PROM will be described. See FIG. 2 (a). A field oxide film (not shown) for element isolation is formed on the p-type silicon substrate 1 by known LOCOS isolation (selective oxidation), and the entire surface is 100 Å thick by thermal oxidation.
Of the gate oxide film 2 is formed, and a polycrystalline silicon layer 3 having a thickness of 1000 Å to be a floating gate is laminated on the entire surface by the CVD method, and impurities such as phosphorus are thermally diffused in the polycrystalline silicon layer 3. .. Then, a 100 Å-thick gate oxide film 4 is formed on the entire surface by thermal oxidation, and a 1000 Å-thick polycrystalline silicon layer 5 to be a control gate is sequentially laminated on the entire surface by a CVD method. Thermally diffuses impurities. Furthermore, the first positive type resist 6 (CM with a thickness of 5000 Å is formed on the entire surface by spin coating.
R: manufactured by Zeon Corporation) and a second positive resist 7 (EBR-9: manufactured by Toray) having a thickness of 5000Å are sequentially laminated.

See FIG. 2 (b). The first positive type resist 6 and the second positive type resist 7 are exposed using the mask of the three-layer structure shown in FIG. Exposure is ultraviolet rays (i line, g
Line) or an excimer laser, etc., and the light intensity is 100 m
J / cm ² . When the mask of this three-layer structure is exposed to light, light is transmitted where Ta and Cr are removed, half is transmitted where Ta is removed and Cr is left, and light is transmitted where Ta and Cr are left. Absent. Therefore, the second positive resist 7 is exposed to light and the first positive resist 6 is not exposed to half the amount of light.

See FIGS. 2 (c) and 2 (d). Using the patterned first positive resist 6 and second positive resist 7, the polycrystalline silicon layer 5, the gate oxide film 4, and the polycrystalline silicon layer 3 are selectively removed by RIE (reactive ion etching). By removing by etching,
Control gate 5a, floating gate 3a and its extension 3b are formed. The RIE conditions are: atmospheric pressure 0.2 Torr, energy 1 W / cm ² , gas chlorine or fluorine, temperature 50 ° C., time 15 seconds.

When etching is performed under the above conditions, the first positive resist 6 and the second positive resist 7 having a thickness of 5000Å and the polycrystalline silicon layers 3 and 5 having a thickness of 1000Å are formed. The etching rates become almost equal. Therefore, when the second positive resist 7 is completely etched, the exposed first positive resist 6 and the exposed polycrystalline silicon layer 5 are also etched (FIG. 2).
(See (c)). Further, when the first positive type resist 6 is completely etched, the exposed polycrystalline silicon layers 5 and 3 are also etched (see FIG. 2D).

See FIG. 2 (e). Control gate 5a
Is used as a mask to ion-implant an impurity forming a conductivity type opposite to that of the p-type silicon substrate 1, for example, arsenic, into the surface of the p-type silicon substrate 1 under the conditions of energy of 50 keV and dose of 3 × 10 ¹⁵ cm ⁻² . As a result, arsenic is not implanted into the portion of the p-type silicon substrate 1 where the control gate 5a exists, and arsenic is implanted at a high concentration in the region where the floating gate 3a does not exist. Arsenic is implanted at a low concentration into the portion of floating gate 3a corresponding to extension 3b, penetrating extension 3b and gate oxide film 2.

Next, the p-type silicon substrate 1 is heat-treated,
Arsenic implanted into the p-type silicon substrate 1 is diffused to form the first drain diffusion layer 8, the source diffusion layer 9, and the second drain diffusion layer 10, respectively. A channel region not implanted with arsenic is formed between the second drain diffusion layer 10 and the source diffusion layer 9. After that, as shown in FIG. 1B, a PSG film 11 which is an interlayer isolation film is laminated, and a contact hole 12 is formed at an appropriate position, and then the aluminum wiring 1 is formed.
3 is provided, and the PSG film 14 is further laminated so as to cover the entire surface.

Through the above steps, the flash EEPROM of one embodiment of the present invention is manufactured. In each of the above-described embodiments, the structure in which the extending portion 3b of the floating gate 3a is provided on the first drain diffusion layer 8 side has been described, but the present invention is not limited to this.
For example, EE for writing and erasing by tunneling operation
In the case of PROM, the extension portion is formed on the source diffusion layer 9 side. In addition, although the above-described one embodiment has been described with respect to the n-channel transistor using the p-type silicon substrate, it is needless to say that it can be applied to the p-channel transistor.

Further, Ta, C are used as a mask having a three-layer structure.
Although r and glass are used, the material is not limited thereto, and any material can be used, as in the embodiment, where light can pass, light can pass a little, and light cannot pass. Further, in one embodiment, materials such as CMR and EBR-9 are used as the two-layer resist, but one positive type resist is exposed and the other positive type resist is not exposed to a certain amount of light. The material of such a positive resist may be selected. Further, although the control gate 5a and the floating gate 3a have the same thickness, the thickness is not limited to this, and the thickness of the control gate 5a and the floating gate 3a can be controlled by the film thickness of the resist.

[0029]

As described above, according to the present invention, 3
By exposing and patterning a two-layer resist using a layered mask, it is not necessary to align the two masks and the control gate and floating gate can be shifted as designed without increasing the number of steps. Is. As a result, the impurity distribution in the drain remains the same as before, and the slope (horizontal direction) of the impurity distribution in the source can be manufactured gently, so that only the band-to-band tunneling current can be suppressed without changing other performances.

Therefore, it is possible to stably manufacture a fine flash EEPROM having improved reliability and yield, which greatly contributes to high performance and high density of the semiconductor integrated circuit.

[Brief description of drawings]

1 (a) and 1 (b): Flash EE in the present invention
It is the top view and sectional drawing of PROM.

2A to 2E are process cross-sectional views for explaining an embodiment of the present invention.

3A and 3B are cross-sectional views of a mask having a three-layer structure,
It is a graph which showed the photosensitivity characteristic of a resist.

4 (a) to 4 (e): Conventional flash EEPRO
It is a process sectional view of M.

[Explanation of symbols]

2 SiO ₂ film serving as a gate oxide film 3 Polycrystalline silicon layer serving as a floating gate 3a Floating gate 3b Extension part of a floating gate 4 SiO ₂ film serving as a gate oxide film 5 Polycrystalline silicon layer serving as a control gate 5a Control gate 6 First Positive Resist 7 Second Positive Resist 8 High Concentration First Drain Diffusion Layer 9 High Concentration Source Diffusion Layer 10 Low Concentration Second Drain Diffusion Layer

Claims (2)

[Claims] 1. A non-volatile memory comprising a memory cell having a structure comprising a floating gate and a control gate, wherein electrons are injected into the floating gate when writing data, and electrons are emitted from the floating gate when erasing data. Forming a first insulating film (2) on the semiconductor substrate (1); forming a first semiconductor layer (3) on the first insulating film (2); Forming a second insulating film (4) on the semiconductor layer (3); forming a second semiconductor layer (5) on the second insulating film (4); Forming a first positive resist (6) on the semiconductor layer (5); forming a second positive resist (7) on the first positive resist (6); First positive resist (6) and second positive resist Exposing and patterning the positive resist (7); and using the first positive resist (6) and the second positive resist (7) as masks, the second semiconductor layer (5), Selectively removing the second insulating film (4) and the first semiconductor layer (3) to form the floating gate (3a) and the control gate (5a), and the control gate (5a) (2) is used as a mask, and a step of introducing an impurity of one conductivity type into the semiconductor substrate (1), and a step of performing heat treatment thereafter are included. 2. The semiconductor according to claim 1, wherein a mask for exposing the first positive resist (6) and the second positive resist (7) has at least three layers. Storage device manufacturing method.