KR960043090A - Device Separation Method of Semiconductor Device - Google Patents
Device Separation Method of Semiconductor Device Download PDFInfo
- Publication number
- KR960043090A KR960043090A KR1019950011621A KR19950011621A KR960043090A KR 960043090 A KR960043090 A KR 960043090A KR 1019950011621 A KR1019950011621 A KR 1019950011621A KR 19950011621 A KR19950011621 A KR 19950011621A KR 960043090 A KR960043090 A KR 960043090A
- Authority
- KR
- South Korea
- Prior art keywords
- peripheral circuit
- cell array
- circuit portion
- trench
- oxide film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract 10
- 238000000926 separation method Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 20
- 230000002093 peripheral effect Effects 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims abstract 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract 4
- 239000000758 substrate Substances 0.000 claims abstract 4
- 150000004767 nitrides Chemical class 0.000 claims 7
- 239000011810 insulating material Substances 0.000 claims 2
- 238000005498 polishing Methods 0.000 claims 2
- 239000000126 substance Substances 0.000 claims 2
- 238000001312 dry etching Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000001020 plasma etching Methods 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
넓은 비활성영역을 갖는 주변회로부와 좁은 비활성영역을 갖는 셀 배열부를 각각 국부적 산화(Local Oxidation ofSilicon : LOCOS)방법 및 트렌치 격리방법에 의해 반도체장치를 분리하는 방법에 관하여 개시한다. 본 발명은 반도체 기판상에 셀 배열부와 주변회로부를 갖는 반도체장치의 소자 분리방법에 있어서, 셀 배열부 및 주변회로부의 각 활성영역을 1회의 포토리쏘그래피 공정을 이용하여 한정하고, 상기 셀 배열부의 활성영역간의 트렌치 격리방법을 이용한 트렌치에 의해 격리되며, 상기 주변회로부의 활성영역간은 국부적 산화(LOCOS) 방법을 이용한 필드산화막에 의해격리된다. 이에 따라, 안정한 소자분리 특성을 그대로 이용하면서 제조공정을 단순화 시킬 수 있는 효과를 발휘한다.Disclosed are a method of separating a semiconductor device by a local oxidation method (LOCOS) method and a trench isolation method, respectively, of a peripheral circuit part having a wide inactive area and a cell array part having a narrow inactive area. The present invention provides a device isolation method for a semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, wherein each active region of the cell array portion and the peripheral circuit portion is defined using one photolithography process, and the cell array It is isolated by a trench using a trench isolation method between negative active regions, and between the active regions of the peripheral circuit portion is separated by a field oxide film using a local oxidation (LOCOS) method. Accordingly, the present invention can simplify the manufacturing process while using stable device isolation characteristics.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제3도는 본 발명에 있어서 셀 배열부 및 주변회로부의 각 활성영역을 한정하기 위한 포토리쏘그래피 공정후의 셀 평면도이다. 제4A도 내지 4H도는 본 발명에 의한 LOCOS 및 트렌치 조합형 소자 분리방법을 각 단계별로 도시한 공정단면도.3 is a plan view of a cell after a photolithography process for defining respective active regions of the cell array unit and the peripheral circuit unit in the present invention. 4A to 4H are process cross-sectional views showing the LOCOS and trench combination device isolation method according to the present invention in each step.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950011621A KR0151040B1 (en) | 1995-05-11 | 1995-05-11 | Method of semiconductor device isolation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950011621A KR0151040B1 (en) | 1995-05-11 | 1995-05-11 | Method of semiconductor device isolation |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960043090A true KR960043090A (en) | 1996-12-23 |
KR0151040B1 KR0151040B1 (en) | 1998-12-01 |
Family
ID=19414243
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950011621A KR0151040B1 (en) | 1995-05-11 | 1995-05-11 | Method of semiconductor device isolation |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0151040B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR970023978A (en) * | 1995-10-04 | 1997-05-30 | 김주용 | Method for manufacturing planar device isolation film of semiconductor device |
-
1995
- 1995-05-11 KR KR1019950011621A patent/KR0151040B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0151040B1 (en) | 1998-12-01 |
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