KR960043090A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR960043090A
KR960043090A KR1019950011621A KR19950011621A KR960043090A KR 960043090 A KR960043090 A KR 960043090A KR 1019950011621 A KR1019950011621 A KR 1019950011621A KR 19950011621 A KR19950011621 A KR 19950011621A KR 960043090 A KR960043090 A KR 960043090A
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South Korea
Prior art keywords
peripheral circuit
cell array
circuit portion
trench
oxide film
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KR1019950011621A
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Korean (ko)
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KR0151040B1 (en
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안동호
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

넓은 비활성영역을 갖는 주변회로부와 좁은 비활성영역을 갖는 셀 배열부를 각각 국부적 산화(Local Oxidation ofSilicon : LOCOS)방법 및 트렌치 격리방법에 의해 반도체장치를 분리하는 방법에 관하여 개시한다. 본 발명은 반도체 기판상에 셀 배열부와 주변회로부를 갖는 반도체장치의 소자 분리방법에 있어서, 셀 배열부 및 주변회로부의 각 활성영역을 1회의 포토리쏘그래피 공정을 이용하여 한정하고, 상기 셀 배열부의 활성영역간의 트렌치 격리방법을 이용한 트렌치에 의해 격리되며, 상기 주변회로부의 활성영역간은 국부적 산화(LOCOS) 방법을 이용한 필드산화막에 의해격리된다. 이에 따라, 안정한 소자분리 특성을 그대로 이용하면서 제조공정을 단순화 시킬 수 있는 효과를 발휘한다.Disclosed are a method of separating a semiconductor device by a local oxidation method (LOCOS) method and a trench isolation method, respectively, of a peripheral circuit part having a wide inactive area and a cell array part having a narrow inactive area. The present invention provides a device isolation method for a semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, wherein each active region of the cell array portion and the peripheral circuit portion is defined using one photolithography process, and the cell array It is isolated by a trench using a trench isolation method between negative active regions, and between the active regions of the peripheral circuit portion is separated by a field oxide film using a local oxidation (LOCOS) method. Accordingly, the present invention can simplify the manufacturing process while using stable device isolation characteristics.

Description

반도체장치의 소자분리방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 있어서 셀 배열부 및 주변회로부의 각 활성영역을 한정하기 위한 포토리쏘그래피 공정후의 셀 평면도이다. 제4A도 내지 4H도는 본 발명에 의한 LOCOS 및 트렌치 조합형 소자 분리방법을 각 단계별로 도시한 공정단면도.3 is a plan view of a cell after a photolithography process for defining respective active regions of the cell array unit and the peripheral circuit unit in the present invention. 4A to 4H are process cross-sectional views showing the LOCOS and trench combination device isolation method according to the present invention in each step.

Claims (9)

반도체 기판상에 셀 배열부와 주변회로부를 갖는 반도체 장치의 소자 분리방법에 있어서, 상기 셀 배열부및 주변회로부의 각 활성영역을 1회의 포토리쏘그래피 공정을 이용하여 한정하고, 상기 셀 배열부의 활성영역간은 트렌치격리방법을 이용한 트렌치에 의해 격리되며, 상기 주변회로부의 활성영역간은 국부적 산화(LOCOS) 방법을 이용한 필드산화막에 의해 격리되는 것을 특징으로 하는 반도체장치의 소자 분리방법.In a device isolation method of a semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, each active region of the cell array portion and the peripheral circuit portion is defined using a single photolithography process, and the cell array portion is activated. Wherein the regions are isolated by trenches using a trench isolation method, and the active regions of the peripheral circuit portion are separated by field oxide films using a local oxidation (LOCOS) method. 제1항에 있어서, 상기 셀 배열부의 셀과 셀 사이가 셀의 폭보다 좁은 라인으로 서로 연결는 것을 특징으로하는 반도체장치의 소자분리방법.The method of claim 1, wherein the cell and the cell of the cell array unit are connected to each other by a line narrower than a cell width. 반도체 기판상에 셀 배열부와 주변회로부를 갖는 반도체 장치의 소자 분리방법에 있어서, a) 상기 반도체기판의 전면에 패드 산화막, 제1 질화막 및 CVD 산화막을 순차적으로 형성하는 공정; b) 상기 주변회로부 및 셀 배열부의각 활성영역과 각 비활성영역을 한정하기 위하여 상기 제 1질화막 및 CVD산화막을 1회의 포토리쏘그래피 공정을 이용하여패터닝하는 공정; c) 상기 패턴닝된 주변회로부의 비활성영역에 국부적 산화(LOCOS)를 이용하여 필드산화막을 형성하는공정; d) 상기 셀 배열부의 비활성영역에 트렌치를 형성하는 공정; e) 상기 트렌치간을 서로 연결하기 위하여 트렌치 폭을 넓히는 공정; f) 상기 트렌치의 내벽에 절연층을 형성하는 공정; 및 e) 결과물 전면에 절연물을 도포한 후, 상기 제1질화막을 연마중지막으로 사용하여 상기 절연물을 CMP(Chemical Mechanical Polishing)하는 공정으로 이루어진 것을 특징으로 하는 반도체장치의 소자분리방법.A device isolation method for a semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, comprising: a) sequentially forming a pad oxide film, a first nitride film, and a CVD oxide film on an entire surface of the semiconductor substrate; b) patterning the first nitride film and the CVD oxide film using a single photolithography process to define each active region and each inactive region of the peripheral circuit portion and the cell arrangement portion; c) forming a field oxide film using local oxidation (LOCOS) in the inactive region of the patterned peripheral circuit portion; d) forming a trench in an inactive region of the cell array; e) widening the trench width to connect the trenches with each other; f) forming an insulating layer on an inner wall of the trench; And e) applying the insulating material to the entire surface of the resultant, and then using the first nitride film as a polishing stop film, and performing the chemical mechanical polishing (CMP) of the insulating material. 제3항에 있어서, 상기 (c)공정 전, 상기 필드산화막 형성을 위한 고온의 LOCOS공정으로 부터 소자를 보호하기 위하여, 좁은 간격을 갖는 상기 셀 배열부의 셀과 셀사이에 매립되고 상기 주변회로부의 측벽에는 스페이서로 남는제 2질화막을 형성하는 공정을 부가하는 것을 특징으로 하는 반도체장치의 소자분리방법.4. The method of claim 3, wherein, before the step (c), in order to protect the device from the high temperature LOCOS process for forming the field oxide film, the peripheral circuit portion is embedded between the cells and the cells of the cell array portion having a narrow spacing. And forming a second nitride film remaining as a spacer on the sidewalls. 제4항에 있어서, 상기 제 2질화막은 에치-백(etchp-back) 공정에 의해 형성되는 것을 특징으로 하는 반도체장치의 소자분리방법.The method of claim 4, wherein the second nitride layer is formed by an etch-back process. 제3항에 있어서, 상기 (e)공정의 트렌치 폭을 넓히는 공정은 CDE(Chemical Dry Etch)를 이용한 동방성 식각으로 수행되는 것을 특징으로 하는 반도체장치의 소자분리방법.4. The method of claim 3, wherein the step (e) of widening the trench width is performed by isotropic etching using chemical dry etching (CDE). 제3항 또는 제 6항에 있어서, 상기 CDE 공정은 인접한 트렌치들이 서로 연결될 때까지 수행되는 것을 특징으로 하는 반도체장치의 소자분리방법.7. The method of claim 3 or 6, wherein the CDE process is performed until adjacent trenches are connected to each other. 제3항에 있어서, 상기 (e)공정의 CMP공정 후, 잔류하는 상기 제1 질화막 및 패드산화막 패턴을 제거하는 공정을 부가하는 것을 특징으로 하는 반도체장치의 소자분리방법.4. The device isolation method according to claim 3, further comprising a step of removing the remaining first nitride film and pad oxide film pattern after the CMP process of step (e). 제8항에 있어서, 상기 제1 질화막 패턴은 반응성 이온식각법을 이용하여 제거하고, 상기 패드산화막은 희석된 HF 및 BOE(Buffered Oxide Etchant) 중의 어느 하나의 용액을 이용한 습식식각에 의해 제거되는 것을 특징으로 하는 반도체장치의 소자분리방법.The method of claim 8, wherein the first nitride layer pattern is removed by using reactive ion etching, and the pad oxide layer is removed by wet etching using a solution of any one of diluted HF and buffered oxide etchant (BOE). A device isolation method for a semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950011621A 1995-05-11 1995-05-11 Method of semiconductor device isolation KR0151040B1 (en)

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