KR100536027B1 - Transistor for a semiconductor device and method of manufacturing the same - Google Patents

Abstract

In a transistor prepared for high integration of a semiconductor device and a manufacturing method thereof, first, an active pattern is formed so as to protrude from a semiconductor substrate and surrounded by an isolation layer. Subsequently, a lower gate structure through which the gate structure passes through the active pattern, an upper gate structure extending in the same direction as the lower gate structure on the active pattern, and extending in the vertical direction from both ends of the lower gate structure, respectively. And a pair of connecting portions connecting the upper gate structure and the lower gate structure. By manufacturing a transistor having excellent gate control, the saturation current is increased, and the short channel effect due to the integration of the semiconductor device can be minimized.

Description

      Transistor of semiconductor device and its manufacturing method {TRANSISTOR FOR A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a transistor prepared for high integration of a semiconductor device and a method of manufacturing the same.

1 is a cross-sectional view of a prior art MOS transistor.

Referring to FIG. 1, a MOS transistor is spaced apart from each other with a gate electrode 14 stacked on the semiconductor substrate 10 with a gate oxide layer 12 interposed therebetween with the gate electrode 14 therebetween. Source 16a and drain 16b formed below the surface of the < RTI ID = 0.0 > Source 16a supplies a carrier (electrons or holes), drain 16b draws the carrier supplied from source 16a out, and gate electrode 14 electrically connects source 16a and drain 16b. It serves to form a channel (A) for connecting to. Gate spacers 18 are formed on sidewalls of the gate electrode 14.

In the above-described MOS transistor, the size of the active region is decreasing as the semiconductor device is highly integrated. In addition, the length of the channel A of the MOS transistor formed in the active region is decreasing. As the length of the channel A of the MOS transistor decreases, the influence of the source / drain on the electric field or the potential in the channel A region becomes worse. This phenomenon is called a short channel effect.

Accordingly, various methods for maximizing device performance while reducing the size of devices formed on a substrate have been researched and developed. For example, various embodiments and modifications including a recess channel transistor (RCAT) structure have been proposed.

However, as the integration of semiconductor devices proceeds, it may be expected that the above-described recess channel transistor (RCAT) structure will also encounter limitations. For example, in the case of a DRAM device, when the design rule becomes 0.06 μm or less, a problem such as an increase in manufacturing cost is encountered when applying a recess channel transistor (RCAT) structure.

In order to solve such problems of the prior art, it is an object of the present invention to provide a novel semiconductor device that is prepared for high integration of semiconductor devices.

Another object of the present invention is to provide a method of manufacturing a semiconductor device which is particularly suitable for manufacturing the above-described semiconductor device.

        In order to achieve the object of the present invention, the transistor of the semiconductor device according to an embodiment of the present invention, first, the active pattern is formed so as to protrude from the semiconductor substrate, surrounded by the isolation layer. Subsequently, a lower gate structure through which the gate structure passes through the active pattern, an upper gate structure extending in the same direction as the lower gate structure on the active pattern, and extending in the vertical direction from both ends of the lower gate structure, respectively. And a pair of connecting portions connecting the upper gate structure and the lower gate structure.

In addition, according to the method of manufacturing a semiconductor device according to an embodiment of the present invention, first, an etching mask is performed on a semiconductor substrate on which a first hard mask layer pattern and an antireflection layer pattern are sequentially formed. The first trench is formed by dry etching using a film to form a preliminary active region defined by the first trench. Subsequently, the first hard mask layer pattern is selectively isotropically etched to form an undercut space to form a second hard mask layer pattern, and the reflection to fill the first trench and the undercut space. An insulating film is formed over the protective film. Subsequently, a planarization process is performed to remove the upper portion of the insulating film and the anti-reflection film so that the surface of the second hard mask film pattern is exposed. Subsequently, a photoresist pattern defining a gate structure is formed on the planarized insulating layer and the second hard mask layer pattern, and the planarized insulating layer and the second hard mask layer pattern are used as an etch mask. The preliminary active pattern is dry-etched to form preliminary second trenches on both sides of the second hard mask layer, and the photoresist pattern is removed. Next, by selectively isotropically etching the preliminary active pattern on which the preliminary second trenches are formed, a cavity penetrating the preliminary active pattern and second trenches having a space connected to the hole and having a narrower upper portion than the lower portion are formed. Form. Subsequently, the second hard mask layer pattern and the insulating layer are etched to complete the device isolation layer and the active pattern. Subsequently, a gate insulating layer is formed on the active pattern, the lower gate structure penetrating the active pattern, the upper gate structure extending in the same direction as the lower gate structure on the active pattern, and the lower gate structure. A gate structure including a pair of connecting portions extending from the end portions in both vertical directions to connect the upper gate structure and the lower gate structure, respectively.

According to the present invention, in the transistor of the semiconductor device, channel regions are formed not only in the lower portion of the upper gate structure but also in various regions of the lower gate structure. . Therefore, the saturation current rises, and the short channel effect due to the integration of the semiconductor device can be minimized.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a plan view illustrating a transistor 100 of a semiconductor device of an embodiment of the present invention.

Referring to FIG. 2, in the transistor 100 of the semiconductor device, an active pattern 110b and an isolation layer 120c are formed on a semiconductor substrate. The gate structure 130 is formed across the active pattern 110, and the gate structure 130 is formed with a lower gate structure 140 (dashed line) and an upper gate structure 150. A connection part (not shown) connecting the lower gate structure 140 and the upper gate structure 150 is formed. The gate spacer 170 is formed on the sidewall of the upper gate structure 150.

FIG. 3 is a cross-sectional view taken along line II ′ of the transistor 100 of the semiconductor device illustrated in FIG. 2.

4 is a cross-sectional view taken along the line II-II 'of the transistor 100 of the semiconductor device shown in FIG.

FIG. 5 is a cross-sectional view taken along line III-III ′ of the transistor 100 of the semiconductor device shown in FIG. 2.

3 to 5, the transistor 100 of the semiconductor device includes an active pattern 110b and a gate structure 130.

The active pattern 110b protrudes from the semiconductor substrate 200 and is formed to be surrounded by the device isolation layer 120c.

The gate structure 130 may include a lower gate structure 140 passing through the active pattern 110b, an upper gate structure 150 extending in the same direction as the lower gate structure 140 on the active pattern 110b, and a lower portion thereof. It is formed to include a pair of connecting portions 160 extending in the vertical direction from both ends of the gate structure 140 to connect the upper gate structure 150 and the lower gate structure 140, respectively.

The lower gate structure 140 may include a gate insulating layer pattern 142a and a first gate conductive layer pattern 144a, and the upper gate structure 150 may include a gate insulating layer pattern 142a and a first gate conductive layer pattern ( 144a, the second gate conductive film pattern 146a, and the hard mask film pattern 148a, and the connection portion 160 includes the gate insulating film pattern 142a and the first gate conductive film pattern 144a.

Gate spacers 170 are formed on sidewalls of the upper gate structure 150.

Thus, the transistor of the semiconductor device according to the present invention forms a source (not shown) / drain region (not shown) in the designed region, and when a voltage is subsequently applied to the gate structure 130, FIGS. 3 and 5 As shown in FIG. 4, channels C and D are formed in various regions of the lower gate structure 140 as well as the lower portion B of the upper gate structure 150, and as shown in FIG. 4, an electric field is formed on the slope of the active pattern 110b. The negative potential is applied to provide excellent gate control.

6 to 34 are cross-sectional views for explaining a method according to the present embodiment suitable for manufacturing a transistor of the semiconductor device shown in FIG.

6, 8, 11, 14, 17, 23, 24, 26, 29, and 32 are cross-sectional views taken along the line II ′ of FIG. 2, and FIGS. 6, 9, 12, 15, 18, 21, 24, 27, 30, and 33 are cross-sectional views taken along the line II-II 'of FIG. 2, and FIGS. 7, 10, 13, 16, 19, 22, 25, 28, 31, and 34 show the line III-III' of FIG. The cross sections are cut along.

6 to 7, the first hard mask layer 202 is formed on the semiconductor substrate 200, which is a silicon substrate. The first hard mask film 202 is preferably formed by depositing a silicon nitride film by LPCVD (Low Pressure Chemical Vapor Deposition) method. Subsequently, an anti-reflection film 204 is formed on the first hard mask film 202.

Subsequently, after the photoresist is applied on the antireflection film 204, a photoresist pattern (not shown) defining an active pattern is formed by a photolithography process. Subsequently, the anti-reflection film 204 and the first hard mask film 202 are dry-etched using the photoresist pattern as an etching mask to form the anti-reflection film pattern 204a and the first hard mask pattern 202a. Next, the photoresist pattern is removed. Next, the preliminary active pattern 110 is formed while the first substrate 206 is formed by dry etching the semiconductor substrate 200 using the first hard mask pattern 202a as an etching mask.

8 through 10, the first hard mask layer pattern 202a may be formed by using the anti-reflection layer pattern 204a as an etching mask to form a cavity penetrating the preliminary active pattern 110 later. Isotropically etched to form an undercut space E, thereby forming a second hard mask film pattern 202b. At this time, the anti-reflection film pattern 204a selects an etching process so as not to be etched. As isotropic etching, wet etching is preferably used.

11 to 13, a first insulating layer 120 is formed on the anti-reflective layer pattern 204a to fill the first trench 206 and the undercut space E. FIG.

As the first insulating layer 120, an insulating material having excellent gap filling characteristics is used. For example, a first insulating layer 120 using an insulating material such as USG (Undoped Silicate Glass), BPSG (BoroPhosphoSilicate Glass), or the like is formed.

14 to 16, the surface of the second hard mask layer pattern 202b is exposed by performing a planarization process using a chemical mechanical polishing (CMP) process on the first insulating layer 120 and the antireflection layer pattern 204a. Let's do it.

17 to 19, a photoresist pattern defining a gate structure by a photo process after applying photoresist on the planarized first insulating layer 120a and the second hard mask pattern 202b (not shown) ). Subsequently, a preliminary second trench may be formed by dry etching the planarized first insulating layer pattern 120a and the preliminary active pattern 110 using the photoresist pattern and the second hard mask pattern 202b as an etch mask. And form 208. In this case, the dry etching process is selected so that the second hard mask layer pattern 202b is not etched. Subsequently, the photoresist pattern is removed.

20 to 22, after the second insulating layer (not shown) is formed on the dry-etched first insulating layer pattern 120b and the preliminary active pattern 110a, the anisotropic etching is performed on the preliminary second trench ( The insulating film spacer 210 is formed on the sidewall of the 208.

23 to 25, a hole F, a cavity, and a hole penetrating through the inside of the preliminary active pattern 110a by selectively isotropically etching the preliminary active pattern 110a using the insulating layer spacer 210 as an etching mask. 23) and the second trench 208a having a narrower upper portion than the lower portion is completed.

26 to 28, the second hard mask layer pattern 202b and the insulating layer spacer are removed using a wet etching process. Next, the insulating film 208b is etched using a wet etching process. As a result, the device isolation layer 120c and the active pattern 110b are completed.

Next, although not shown, a process for forming a source / drain region may be performed by injecting impurities into the designed region.

29 to 31, a gate insulating layer 142 is formed on the exposed active pattern. Subsequently, the first gate conductive layer 144 is formed on the active pattern so as to fill the holes F and the second trenches 208a. Subsequently, a second gate conductive layer 146 is formed on the first gate conductive layer 144. Subsequently, a third hard mask layer 148 is formed on the second gate conductive layer 146.

32 to 34, after the photoresist is applied on the third hard mask layer 148, a photoresist pattern (not shown) defining the gate structure 130 is formed by a photolithography process. Subsequently, the third hard mask layer 148 is dry-etched using the photoresist pattern as an etching mask to form a third hard mask pattern 148a. Next, the photoresist pattern is removed.

Subsequently, the second gate conductive layer 146, the first gate conductive layer 144, and the gate insulating layer 142 are dry-etched using the third hard mask pattern 148a as an etch mask to penetrate the active pattern 110b. The lower gate structure 140, the upper gate structure 150 extending in the same direction as the lower gate structure 140 on the active pattern 110b, and from both ends of the lower gate structure 140 in a vertical direction. Each extends to form a gate structure 130 including a pair of connecting portions 160 connecting the upper gate structure 150 and the lower gate structure 140.

The lower gate structure 140 includes a gate insulating layer pattern 142a and a first gate conductive layer pattern 144a, and the upper gate structure 150 includes a gate insulating layer pattern 142a and a first gate conductive layer pattern 144a. And a second gate conductive film pattern 146a and a hard mask film pattern 148a, and the connection portion 160 is a gate insulating film pattern 142a and a first gate conductive film pattern 144a.

Next, although not shown, a process for forming a source / drain region may be performed by injecting impurities into the designed region.

Subsequently, after forming a third insulating layer (not shown) on the active pattern 110b having the gate structure 130 formed thereon, anisotropic etching is performed to form the gate spacer 170 on the sidewall of the upper gate structure 150. do.

Next, although not shown, a process for forming a source / drain region may be performed by injecting impurities into the designed region. This completes the transistor of the semiconductor device.

As a result, when the transistor of the semiconductor device manufactured according to this embodiment forms a source (not shown) / drain region (not shown) in the designed region, and subsequently a voltage is applied to the gate structure 130, 32 and 34, channels C and D are formed in various regions of the lower gate structure 140 as well as the lower portion B of the upper gate structure 150, and the active pattern 110b is illustrated in FIG. 33. An electric field or potential is applied at the slope of the gate, so the gate control is excellent.

In the transistor of the semiconductor device according to the present invention as described above, channel regions are formed not only in the lower portion of the upper gate structure but also in various regions of the lower gate structure, and an electric field or a potential is applied on four sides of the active pattern, thereby providing excellent gate control. As a result, the saturation current rises and is operated at high speed. In addition, it is possible to minimize the short channel effect due to the integration of the semiconductor device.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

1 is a cross-sectional view of a prior art MOS transistor.

2 is a plan view illustrating a transistor 100 of a semiconductor device of an embodiment of the present invention.

FIG. 3 is a cross-sectional view taken along line II ′ of the transistor 100 of the semiconductor device illustrated in FIG. 2.

4 is a cross-sectional view taken along the line II-II 'of the transistor 100 of the semiconductor device shown in FIG.

FIG. 5 is a cross-sectional view taken along line III-III ′ of the transistor 100 of the semiconductor device shown in FIG. 2.

6 to 34 are cross-sectional views for describing a method according to an example embodiment for manufacturing a transistor of the semiconductor device shown in FIG. 2.

<Explanation of symbols for the main parts of the drawings>

10, 200: semiconductor substrate 12: gate oxide film

14 gate electrode 16a source region

16b: drain region 18, 210: gate spacer

100 transistor 110 of the semiconductor device: preliminary active pattern

110a: dry-etched preliminary active pattern 110b: active pattern

120: first insulating film 120a: planarized first insulating film

120b: dry-etched first insulating layer pattern 120c: device isolation layer

130: gate structure 140: lower gate structure

142: gate insulating film 142a: gate insulating film pattern

144: first gate conductive layer 144a: first gate conductive layer pattern

146: second gate conductive film 146a: second gate conductive film pattern

148: Third Hard Mask Film 148a: Third Hard Mask Pattern

150: upper gate structure 160: connection portion

202a: first hard mask pattern 202b: second hard mask pattern

204a: antireflection film pattern 206: first trench

208: preliminary second trench 208a: second trench

Claims (8)

An active pattern protruding from the semiconductor substrate and surrounded by the device isolation layer; And A lower gate structure penetrating through the active pattern, an upper gate structure extending over the active pattern in the same direction as the lower gate structure, and extending from the opposite ends of the lower gate structure in a vertical direction, respectively; And a gate structure including a pair of connecting portions connecting the lower gate structure to each other. The transistor of claim 1, further comprising a gate spacer formed on sidewalls of the upper gate structure. The transistor of claim 1, wherein the lower gate structure comprises a gate insulating layer pattern and a first gate conductive layer pattern. The transistor of claim 1, wherein the connection part comprises a gate insulating film pattern and a first gate conductive film pattern. The semiconductor substrate on which the first hard mask layer pattern and the antireflective layer pattern are sequentially formed is dry-etched using the first hard mask layer pattern and the anti-reflective layer pattern as an etch mask layer to form a first trench to form the first trench. Forming a preliminary active region defined; Selectively isotropically etching the first hard mask film pattern to form a second hard mask film pattern while forming an undercut space; Forming an insulating film on the anti-reflection film to fill the first trench and the undercut space; Performing a planarization process to remove the upper portion of the insulating film and the anti-reflection film so that the surface of the second hard mask film pattern is exposed;  Forming a photoresist pattern defining a gate structure on the planarization insulating layer and the second hard mask layer pattern; Dry etching the planarized insulating layer and the preliminary active pattern using the photoresist pattern and the second hard mask layer pattern as an etch mask to form preliminary second trenches on both sides of the second hard mask layer; Removing the photoresist pattern; Selectively isotropically etching the preliminary active pattern in which the preliminary second trenches are formed to form a cavity penetrating the preliminary active pattern and second trenches having a space connected to the hole and having a narrower upper portion than the lower portion; Etching the second hard mask layer pattern and the insulating layer to complete an isolation layer and an active pattern; Forming a gate insulating layer on the active pattern; And A lower gate structure penetrating through the active pattern, an upper gate structure extending in the same direction as the lower gate structure on the active pattern, and extending in a vertical direction from both ends of the lower gate structure, respectively; And forming a gate structure including a pair of connecting portions connecting the lower gate structure. The method of claim 5, wherein after forming the gate structure: And forming a gate spacer on sidewalls of the upper gate structure. The method of claim 5, wherein before forming the second trench, And forming a spacer on sidewalls of the preliminary second trenches. The method of claim 5, wherein the forming of the gate structure, Forming a first gate conductive layer on the active pattern on which the gate insulating layer is formed so as to fill the cavity and the second trench; Forming a second gate conductive layer on the first gate conductive layer; Forming a hard mask layer on the second gate conductive layer; Forming a photoresist pattern on the hard mask layer by a photo process; Etching the hard mask layer by using the photoresist pattern as an etch mask layer to form a hard mask layer pattern; Removing the photoresist pattern; And And etching the second gate conductive layer, the first gate conductive layer, and the gate insulating layer using the hard mask layer pattern as an etch mask layer.