KR0168198B1 - Method for forming trench isolation on a semiconductor device - Google Patents

Abstract

A method of trench isolation of a semiconductor device is disclosed in which an impurity region is formed only in a portion of a trench sidewall to reduce junction capacitance and leakage current. The present invention provides a method of forming an insulating film on a semiconductor substrate, forming an insulating film pattern to expose a predetermined region of the semiconductor substrate by patterning the insulating film, and etching the exposed semiconductor substrate using the insulating film pattern as an etching mask. Forming a first trench, forming an impurity region surrounding the first trench, and etching the first trench using the insulating layer pattern as an etch mask to form a second trench in which residual impurity regions are formed on the trench sidewalls. It provides a trench type device isolation method for a semiconductor device comprising the step of forming a. According to the present invention, since the residual impurity region is extinguished by counter doping, there is no interface between the residual impurity region and the active region, thereby preventing generation of junction capacitance and leakage current at the junction interface.

Description

Trench type isolation method for semiconductor devices

1 to 5 are cross-sectional views illustrating a trench type device isolation method of a semiconductor device according to the prior art.

6 to 11 are cross-sectional views illustrating a trench type device isolation method of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device using trenches, and more particularly, to a trench type device isolation method of a semiconductor device in which an impurity region is formed only in a portion of a trench sidewall to reduce junction capacitance and leakage current.

The device isolation method of a semiconductor device can be classified into a local oxidation of silicon (LOCOS) device isolation method and a trench type device isolation method.

Locus device isolation method has the advantage of simple process and the ability to separate devices at large and narrow areas at the same time, but a bird's beak is formed to increase the width of the device isolation area to dedicate the source / drain area. Reduce the area. In addition, when the field oxide film is formed, stress is concentrated at the edge of the oxide film due to the difference in thermal expansion coefficient, so that a crystal defect occurs in the silicon substrate, thereby increasing the leakage current.

Therefore, there is an increasing demand for a trench type isolation method for semiconductor devices. However, one of the biggest problems in implementing trench type isolation is that a locally strong field is formed in the channel region adjacent to the trench sidewalls, which easily inversions at low gate voltages and increases the current flowing between the source and drain. will be. As a result, an inverse narrow width effect occurs in which the threshold voltage of the transistor is lowered.

To solve this problem, a method of implanting impurities, such as a substrate, into the trench sidewalls after trench formation [G. Fuse, et. al A Practical Trench Isolation Technology With a Novel Planarization Process IEDM, 1987, p732-735] and a method of forming a trench after forming an impurity region deeper and wider than a portion where a trench is to be formed before trench formation (US Pat. No. 5,118,636). Has been presented.

1 to 5 are cross-sectional views for explaining a trench type device isolation method of a semiconductor device according to the prior art described in the aforementioned US Patent No. 5,118.636.

1 is a cross-sectional view for describing a step of forming the pad insulating layer pattern 20 and the etch stop layer pattern 30. First, a pad insulating film and an etch stop layer are sequentially formed on the semiconductor substrate 10. Subsequently, the pad insulating layer and the etch stop layer are patterned to form a pad insulating layer pattern 20 and an etch stop layer pattern 30 exposing a predetermined region of the semiconductor substrate 10.

FIG. 2 is a cross-sectional view for explaining the step of forming the impurity region 40. First, an impurity is formed on the exposed semiconductor substrate using the pad insulating film pattern 20 and the etch stop layer pattern 30 as ion implantation masks. By implanting the impurity region 40 having a width wider than the width of the exposed semiconductor substrate. In this case, the impurity region 40 may dopants of the same conductivity type as the semiconductor substrate 10 to a concentration higher than that of the impurity doped in the semiconductor substrate 10.

3 is a cross-sectional view illustrating a process of forming the trench 50 and the residual impurity region 60. First, an anisotropic etching of the impurity region 40 using the etch stop layer pattern 30 as an etch mask is performed. A trench 50 having residual impurity regions 60 is formed in the trenches.

FIG. 4 is a cross-sectional view for describing the forming of the device isolation layer 70. First, a trench filling material layer is formed on the entire surface of the substrate on which the trench 50 is formed. Next, the trench filling material layer is planarized by a chemical mechanical polishing (CMP) method, and the etch stop layer pattern 30 and the pad insulating layer pattern 20 are sequentially removed, thereby forming the trench filling material layer pattern inside the trench 50. Form 70.

FIG. 5 is a cross-sectional view illustrating an operation of forming the active region 80 and the remaining impurity region 60a. The trench filling material layer pattern 70 is formed by using the trench filling material layer pattern 70 as an ion implantation mask. The active region 80 is formed by implanting impurities into the entire surface of the formed substrate. In this case, the active region 80 is formed by counter doping, that is, by implanting impurities having a conductivity type opposite to that of the residual impurity region 60 at a higher concentration than when the residual impurity region 60 is formed. . Therefore, the remaining impurity region 60a in which the upper part of the residual impurity region 60 is partially removed is formed.

Therefore, a junction exists between the active region 80 and the residual impurity region 60a, thereby generating a junction capacitance. In addition, since the residual impurity region 60a and the active region 80 are heavily doped, the concentration of a high electric field occurs at the junction interface to increase the leakage current.

According to the above-described trench type device isolation method of a semiconductor device, there is a problem in that the junction capacitance and the leakage current are increased by the residual impurity region 60a in contact with the active region 80.

Accordingly, an object of the present invention is to provide a trench type device isolation method for a semiconductor device capable of reducing junction capacitance and leakage current.

The present invention to achieve the above object,

In the semiconductor device separation method,

Forming an insulating film on the semiconductor substrate;

Forming an insulating film pattern that exposes a predetermined region of the semiconductor substrate by patterning the insulating film;

Forming a first trench by etching the exposed semiconductor substrate using the insulating layer pattern as an etching mask;

Forming an impurity region surrounding the first trench; And

And etching the first trenches using the insulating layer pattern as an etch mask to form second trenches having residual impurity regions formed on upper sidewalls of the trenches.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 to 11 are cross-sectional views illustrating a trench type device isolation method of a semiconductor device according to the present invention.

6 is a cross-sectional view for describing a step of forming the pad insulating layer pattern 21 and the etch stop layer pattern 31. First, an insulating film (not shown), for example, a pad insulating film and an etch stop layer, are sequentially formed on the semiconductor substrate 11. The pad insulating layer and the etch stop layer may be formed of a thermal oxide layer and silicon nitride (SiNx), respectively. Subsequently, the insulating film is patterned to form an insulating film pattern that exposes a predetermined region of the semiconductor substrate 11. The insulating layer pattern may include a pad insulating layer pattern 21 and an etch stop layer pattern 31.

FIG. 7 is a cross-sectional view illustrating a process of forming the first trenches 41 and the impurity regions 51. First, the exposed semiconductor substrates are etched using the insulating layer pattern as an etch mask. Form.

Subsequently, the impurity region 51 surrounding the first trench 41 is formed by any one selected from an ion implantation process and a diffusion process using a solid or gas source. In this case, when the impurity region is formed by the ion implantation process, it is preferable to proceed with a change in the ion implantation incident angle.

In addition, the impurity region 51 may be formed by doping a conductive impurity such as the semiconductor substrate 11 to a concentration higher than that of the impurity doped in the semiconductor substrate 11.

FIG. 8 is a cross-sectional view for explaining a step of forming the second trench 61 and the remaining impurity region 71. The trench is further etched by a predetermined depth using the insulating layer pattern as an etching mask. A second trench 61 in which residual impurity regions 71 are formed only on the sidewalls is formed.

FIG. 9 is a cross-sectional view for describing a step of forming the trench filling material layer 81. A trench filling material layer 81, for example, a CVD oxide layer is formed on the entire surface of the substrate on which the second trench 61 is formed.

FIG. 10 is a cross-sectional view illustrating a step of forming the trench filling material layer pattern 91. The trench filling material layer 81 is planarized using a method such as chemical mechanical polishing (CMP), and a wet etching method is used. The trench filling material layer pattern 91 is formed in the second trench 61 by sequentially removing the insulating layer pattern.

11 is a cross-sectional view for describing a step of forming the active region 101.

Although not shown in the drawing prior to forming the active region 101, a conductive film is deposited after the trench filling material layer pattern 91 is formed.

Subsequently, the conductive film is patterned to form a gate electrode.

Next, an impurity is implanted into the entire surface of the substrate on which the gate electrode is formed using the gate electrode and the trench filling material layer pattern 91 as an ion implantation mask, thereby forming an active region 101 on the surface of the semiconductor substrate adjacent to the second trench 61. ).

In this case, the active region 101 is formed by injecting impurities of a conductivity type opposite to the residual impurity region 71 to a concentration higher than the impurity concentration doped in the residual impurity region 71. In addition, the active region 101 preferably includes the residual impurity region 71. Therefore, the residual impurity region 71 is counter-doped and disappears when the active region 101 is formed.

Meanwhile, since the gate electrode serves as an ion implantation mask, the active region 101 is not formed under the gate electrode.

Therefore, the residual impurity region 71 remains as it is.

As described above, according to the exemplary embodiment of the present invention, since the residual impurity region 71 exists in the lower portion of the gate electrode, that is, in the trench sidewall adjacent to the channel region, the inverse narrow width effect is prevented. can do. In addition, since the residual impurity region 71 of the trench sidewall contacting the active region 101 is extinguished by counter doping, there is no interface between the residual impurity region 71 and the active region 101. Therefore, it is possible to prevent the generation of junction capacitance and leakage current at the junction interface.

The present invention is not limited only to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea.

Claims (7)

A device isolation method for a semiconductor device, comprising: forming an insulating film on a semiconductor substrate; Forming an insulating film pattern that exposes a predetermined region of the semiconductor substrate by patterning the insulating film; Forming a first trench by etching the exposed semiconductor substrate using the insulating layer pattern as an etching mask; Forming an impurity region surrounding the first trench; And forming a second trench having a residual impurity region formed on an upper sidewall of the trench by etching the first trench using the insulating layer pattern as an etch mask. The method of claim 1, further comprising: forming a trench filling material layer on an entire surface of the substrate on which the second trench is formed after the forming of the second trench; Sequentially removing the trench filling material layer and the insulating layer pattern to form a trench filling material layer pattern in the second trench; And forming an active region including the impurity region on a surface of the semiconductor substrate adjacent to the second trench. The method of claim 1, wherein the impurity region is formed by doping a conductive impurity such as the semiconductor substrate to a concentration higher than that of the impurity doped in the semiconductor substrate. . The method of claim 1, wherein the impurity region is formed by any one of an ion implantation process and a diffusion process using a solid or gas source. The method of claim 1, wherein the insulating layer is formed by sequentially stacking a thermal oxide film and silicon nitride. The trench type semiconductor device of claim 2, wherein the active region is formed by doping a conductivity type opposite to the residual impurity region to a concentration higher than an impurity concentration doped in the residual impurity region. Device isolation method. The method of claim 4, wherein the ion implantation process is performed while varying an ion implantation incident angle.