KR20040008618A - Method for isolation in semiconductor device using trench structure - Google Patents

Abstract

PURPOSE: A trench isolation method of a semiconductor device is provided to be capable of preventing moat and INWE(Inverse Narrow Width Effect). CONSTITUTION: A trench mask pattern is formed on a semiconductor substrate(31). A spacer is formed at sidewalls of the trench mask pattern. A trench(37) is formed by etching the substrate using the spacer and the mask pattern. After removing the spacer, an INWE compensation layer(38) is formed by implanting dopants. An oxide liner(39) is formed on the trench. A nitride liner(40b) is formed on the oxide liner. An isolation layer(41) is formed in the trench. After planarizing the isolation layer, the trench mask pattern is removed.

Description

Device isolation method of semiconductor device using trench structure {Method for isolation in semiconductor device using trench structure}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an isolation (ISO) method.

In recent years, as the integration degree of semiconductor devices increases, the design rule decreases. Accordingly, the size of the device isolation film separating the semiconductor devices from the semiconductor devices is also reduced by the same scale, so that the conventional LOCOS method is known. Application has reached its limit.

To solve this problem, the Shallow Trench Isolation (STI) method has been proposed, and the STI method has become an essential element to provide minimum device isolation pitch, a flatter surface, and increased latch-up immunity.

A typical STI method first deposits a pad oxide film and a pad nitride film on a semiconductor substrate, forms a trench through a device isolation mask process and an etching process, and then oxidizes the trench sidewalls. At this time, the reason for oxidizing the trench sidewall is to remove defects that may occur in the sidewalls during the trench etching process. Next, the inside of the trench formed after the trench etching is gap-filled with an oxide (hereinafter referred to as 'field oxide film') and then planarized by chemical mechanical polishing (CMP). Then, the separation between the device and the device is performed while going through a series of processes to remove the pad nitride film in the position where the active region is formed.

1 is a view schematically showing a device isolation method by a general STI method.

Referring to FIG. 1, the trench 12 is formed by etching the semiconductor substrate 11, the field oxide layer 13 is filled in the trench 12, and the gate oxide layer 14 is formed on the active region of the semiconductor substrate. The gate electrode 15 is formed on the gate oxide film 14. The channel region 16 is formed by ion implanting boron, which is a p-type impurity, into the active region of the semiconductor substrate 11.

However, when the devices are separated through the STI method, the nMOSFET exhibits an inverse narrow width effect (INWE) in which the threshold voltage decreases as the channel width decreases in contrast to the LOCOS method. As shown in FIG. 1, when the STI method is applied, there is no Budvik and the active region is formed almost vertically, resulting in an increase in the fringe effect ('F' in FIG. 1) of the gate electric field. Because.

In addition, thinning of the gate oxide film near the edges of the active region results in a decrease in threshold voltage and deterioration of characteristics of the gate oxide film due to electric field concentration.

In addition, the phenomenon of inverse narrowing effect in the nMOSFET is caused by the segmentation into the field oxide layer 13 of boron (B), which is a channel ion implantation dopant implanted for p well and moon voltage control (FIG. There is a problem that is further deepened by S ').

To compensate for this, increasing the injection amount of boron, a channel ion implantation dopant, increases the junction leakage current, which inevitably leads to an increase in standby power and deterioration of refresh characteristics in DRAM. In addition, the change of the threshold voltage for the STI structure is a serious problem in ensuring uniformity by accurately controlling device characteristics.

Another problem of the STI method is that in forming the STI, as shown in FIG. 2, a step may be formed between the field oxide film 22 and the active region 21a of the semiconductor substrate 21. As a result, in the cleaning processes such as pad oxide removal and cleaning performed after pad nitride removal, pre-cleaning for threshold voltage injection screen oxide, and pre-cleaning of gate oxide, the `` moor '' near the edge of the active region and field oxide boundary A field oxide film loss ('M' in FIG. 2) called 'Moat' occurs. Even in this case, there is a possibility that the remaining film of the conductive material may remain on the sidewalls of the field oxide film when the conductive material such as the polysilicon film is deposited and etched while the gate is formed and the threshold voltage is reduced due to the increased fringe effect of the gate electric field. The remaining film, which is a conductive material, may cause a short between neighboring gate electrodes.

The present invention has been made to solve the above problems of the prior art, an object of the present invention is to provide a device separation method of a semiconductor device suitable for preventing the inverse narrow effect and the moat phenomenon at the same time.

1 is a view schematically showing a device isolation method by a general STI method,

2 is a diagram illustrating a moat phenomenon according to the prior art;

3A to 3I are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with a first embodiment of the present invention;

4A to 4I are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 pad oxide film

33: pad nitride film 35: etching stop layer

36: nitride spacer 37: trench

38: inverse narrow effect compensation layer 39: oxide film liner

40: nitride film liner 41: field oxide film

The device isolation method of the semiconductor device of the present invention for achieving the above object is to form a mask layer defining an active region smaller than a value set on a semiconductor substrate, forming a spacer on the sidewall of the mask layer, the mask Forming a trench by etching the semiconductor substrate using an etch mask with a layer and the spacer; exposing the shoulder portion of the trench by removing the spacer; and implanting a dopant with the mask layer as a mask to inverse narrow effect compensation layer Forming an oxide film liner covering the entire region of the trench and the shoulder portion of the trench; forming a nitride film liner on the entire surface including the oxide film liner; and forming the nitride film liner on the nitride film liner until the trench is filled. Forming a field oxide layer until the surface of the mask layer is exposed Characterized in that it comprises the step of flattening the group field oxide film, and removing the mask layer.

In addition, the device isolation method of the semiconductor device of the present invention comprises the steps of forming a mask layer defining an active region smaller than a value set on a semiconductor substrate, forming a spacer on the sidewall of the mask layer, the mask layer and the spacer Forming a trench by etching the semiconductor substrate with an etch mask, exposing the shoulder of the trench by removing the spacer, forming a dopant incubation layer on the entire surface including the exposed trench, and in the dopant incubation layer Forming a reverse narrowing effect compensation layer by driving a dopant toward the trench and the shoulder portion of the trench, forming a nitride film liner on the dopant hatching layer, and forming a field oxide film on the nitride film liner until the trench is filled. Forming the field acid until the surface of the mask layer is exposed; Planarizing the film, and removing the mask layer.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3I are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 3A, a pad oxide film 32 is formed on the semiconductor substrate 31. Here, the pad oxide layer 32 serves as a buffer layer and a stop layer for chemical mechanical polishing (CMP) to protect the interface of the region where the active region is to be formed and to buffer the stress of the subsequent pad nitride layer. do.

Next, after the pad nitride layer 33 is formed on the pad oxide layer 32, a device isolation mask 34 is formed on the pad nitride layer 33 to distinguish the active region from the field region through the photolithography process. . In this case, the size of the active region x ₂ defined by the device isolation mask 34 is smaller than the active region x ₁ to be actually implemented.

Next, the pad isolation layer 33 and the pad oxide layer 32 are sequentially patterned using the device isolation mask 34 as an etching mask. Here, the laminate of the patterned pad oxide layer 32 and the pad nitride layer 33 is used as an etching mask for subsequent trench formation.

As shown in FIG. 3B, after the device isolation mask 34 is removed, an etch stop layer 35 and a nitride film (not shown) are sequentially formed on the entire surface. The nitride film is vertically etched to form a nitride film spacer 36. At this time, the thickness of the nitride film spacer 36 and the etch stop layer 35 becomes a difference between the size of the active region to be actually implemented and the device isolation mask.

Here, the etch stop layer 35 may use an oxide film or a polysilicon film as a material having a selectivity in the vertical etching of the nitride film for forming the nitride film spacer 36, but preferably an oxide film that does not require a subsequent residue removal process may be used. It is suitable. On the other hand, the reason why the etch stop layer 35 is used is to prevent the pad nitride layer 33 from being etched at the same time when the subsequent nitride layer spacer 36 is removed to change the size of the active region.

As illustrated in FIG. 3C, the trench 37 is formed by etching the exposed semiconductor substrate 31 after forming the nitride film spacer 36 using the nitride film spacer 36 and the pad nitride film 33 as an etch mask.

At this time, the etch stop layer 35 not covered by the nitride film spacer 36 is also etched and removed. As a result, the etch stop layer 35 over the pad nitride film 33 and the upper portion of the semiconductor substrate 31 is removed, so that only the portion in contact with the nitride film spacer 36 remains in an L shape. Hereinafter, the remaining etch stop layer is referred to as an 'L-shaped etch stop layer 35a'.

As shown in FIG. 3D, the nitride film spacer 36 is removed through wet etching. At this time, the pad nitride film 33 is also removed by a predetermined thickness so that the retracted pad nitride film 33a remains.

Next, the etch stop layer 35 is removed.

As shown in FIG. 3E, the bottom and sidewalls of the trench 37 are ion-implanted with p-type impurities boron (B) or boron difluoride (BF ₂ ) in front of the retracted pad nitride film 33a using a mask; An inverse narrow effect compensation layer 38 is formed to reach the edge of the active region.

In this case, the ion implantation for forming the inverse narrow effect compensation layer 38 is performed while giving a tilt angle or vertically without a tilt angle.

As shown in FIG. 3F, the thermal oxidation process is performed to compensate for the lattice damage generated during the formation of the trench 37 and the ion implantation of boron (B) or boron difluoride (BF ₂ ). After the oxide liner 39 is formed on the sidewalls and the bottom and the edges of the active region, the nitride liner 40 is formed on the entire surface.

At this time, the oxide liner 38 extends beyond the shoulder portion of the trench where the inverse narrow effect compensation layer 38 exists to meet the pad oxide layer 32.

As shown in FIG. 3G, after forming an oxide to be the field oxide film 41 on the entire surface including the nitride film liner 40, an annealing process is performed to increase the density of the oxide. As the oxide used as the field oxide film 41, a known high density plasma oxide film is used.

Next, chemical mechanical polishing (CMP) is performed to planarize the wafer until the top of the pad nitride film 33a is exposed to planarize the field oxide film 41. At this time, due to the shoulder portion of the trench stepped externally, the upper portion of the field oxide film 41 is formed into a protrusion 41a, the nitride film remaining after the chemical mechanical polishing of the field oxide film 41 having the protrusion 41a The liner 40a is enclosed. Therefore, the edge of the pad nitride film 33a is located outside the trench 37.

As shown in FIG. 3H, wet etching is performed to remove the pad nitride layer 33a. At this time, the nitride film liner 40a adjacent to the pad nitride film 33a is also removed at the same time. However, since the wet etching solution does not reach the nitride film liner 40a under the field oxide film 41, the nitride film liner 40b is disposed below the field oxide film 41. Remains.

Even if the wet etching solution reaches the nitride film liner 40b below the field oxide film 41, since the nitride film liner 40b extends laterally under the protrusion 41a of the field oxide film 41, the wet etching solution is wet. It takes time to penetrate laterally under the protrusion 41a until the solution reaches the upper edge of the nitride film liner 40b. Therefore, when the pad nitride film 33a removal process is completed, the penetration of the wet etching solution stops at a point shorter than the upper edge of the nitride film liner 40b.

Next, as shown in FIG. 3I, additional wet etching is performed to remove portions of the field oxide film 41 lying on the surface of the pad oxide film 32 and the semiconductor substrate 31 until the wafer achieves a substantially flat surface. Proceed with the process. As a result of this additional wet etching, the active regions of the inverse narrow effect compensation layer 38 and the semiconductor substrate 31 are exposed to the outside, and the field oxide film 41 having the flat surface is formed of the nitride film liner 40c and the oxide film liner 39a. Is surrounded.

In a subsequent process, a known semiconductor device manufacturing process is performed to form a channel region, a gate oxide film, a gate electrode, a source and a drain region.

According to the embodiment described above, the nitride film liner 40b remaining in FIG. 3H adds a wet process of the field oxide film 41 or reduces the boundary between the active area and the field oxide film 41 in the cleaning step to reduce the step with the active area. It prevents the moat phenomenon caused by the loss of oxide film in the vicinity.

4A to 4I are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 4A, a pad oxide film 52 is formed on the semiconductor substrate 51. Here, the pad oxide layer 52 serves as a buffer layer for buffering the interface of the region where the active region is to be formed and for buffering the stress of the subsequent pad nitride layer and as a stop layer for chemical mechanical polishing (CMP).

Next, after the pad nitride film 53 is formed on the pad oxide film 52, a device isolation mask 54 is formed on the pad nitride film 53 to distinguish the active region from the field region through the photolithography process. . At this time, the size of the active region x ₂ defined by the device isolation mask 54 is smaller than the active region x ₁ to be actually implemented.

Next, the pad isolation layer 53 and the pad oxide layer 52 are sequentially patterned using the device isolation mask 54 as an etching mask. Here, the laminate of the patterned pad oxide layer 52 and the pad nitride layer 53 is used as an etching mask for subsequent trench formation.

As shown in FIG. 4B, after removing the device isolation mask 54, an etch stop layer 55 and a nitride film (not shown) are sequentially formed on the entire surface. The nitride film is vertically etched to form a nitride film spacer 56. In this case, the thickness of the nitride layer spacer 56 and the etch stop layer 55 is a difference between the size of the active region to be actually implemented and the device isolation mask.

Here, the etch stop layer 55 may use an oxide film or a polysilicon film as a material having a selectivity in the vertical etching of the nitride film for forming the nitride film spacer 56, but an oxide film that does not require a subsequent residue removal process may be used. It is suitable. On the other hand, the reason why the etch stop layer 55 is used is to prevent the pad nitride film 53 from being etched at the same time when the subsequent nitride film spacer 56 is removed to change the size of the active region.

As shown in FIG. 4C, the trench 57 is formed by etching the exposed semiconductor substrate 51 after forming the nitride film spacer 56 with the nitride film spacer 56 and the pad nitride film 53 as an etch mask.

At this time, the etch stop layer 55 not covered by the nitride film spacer 56 is also etched and removed. As a result, the etch stop layer 55 above the pad nitride film 53 and the upper portion of the semiconductor substrate 51 is removed, and only a portion of the pad nitride film 53 contacting the nitride film spacer 56 remains in an L shape. Hereinafter, the remaining etch stop layer is referred to as an 'L-shaped etch stop layer 55a'.

As shown in FIG. 4D, the nitride film spacer 56 is removed through wet etching. At this time, the shoulder portion of the trench 57 is exposed after the nitride film spacer 56 is removed, and the pad nitride film 53 is also removed by a predetermined thickness so that the retracted pad nitride film 53a remains.

Next, the etch stop layer 55 is removed.

As shown in FIG. 4E, an oxidation or cleaning process is performed to eliminate sidewall loss of the trench after trench 57 formation and removal of nitride film spacer 56. In FIG. 5E, the oxide film liner 58 formed after the oxidation process is illustrated.

Next, a BSG (Boro-silicate glass) film 59 is thinly deposited on the entire surface of the semiconductor substrate 51 until the oxide liner 58 has a trench formed therein, and then a drive-in process is performed.

In this case, the BSG film 59 is a dopant rich layer containing a large amount of boron. The dopant enrichment layer may be a dopant implantation process through a drive-in with subsequent heat. That is, the self-doping boron in the BSG film 59 through the heat-induced drive-in to the bottom and sidewalls of the trench, and also diffused to the edge of the active region to inverse narrow effect compensation layer 60 To form.

Applying the BSG film 59 described above can prevent the lattice damage due to ion implantation because the ion implantation process is unnecessary.

As shown in FIG. 4F, a nitride film liner 61 is formed on the entire surface including the BSG film 59. Next, after the oxide to be the field oxide film 62 is formed on the entire surface including the nitride film liner 61, an annealing process is performed to increase the density of the oxide. The oxide used for the field oxide film 62 is a well-known high density plasma oxide film.

As shown in FIG. 4G, the field oxide film 62 is planarized by chemical mechanical polishing (CMP) to planarize the wafer until the top of the pad nitride film 53a is exposed. At this time, due to the externally stepped shoulder of the trench, the upper portion of the field oxide film 62 is formed into a protrusion 62a, and the nitride film remaining after the chemical mechanical polishing of the field oxide film 62 having the protrusion 62a. The liner 61a and the BSG film 59a are surrounded. Therefore, the edge of the pad nitride film 53a is located outside the trench.

As shown in FIG. 4H, wet etching is performed to remove the pad nitride film 53a. At this time, the nitride film liner 61a adjacent to the pad nitride film 53a is also removed at the same time. However, since the wet etching solution does not reach the nitride film liner 61b under the field oxide film 62, the nitride film liner 61b is disposed below the field oxide film 62. Remains.

Even if the wet etching solution reaches the nitride liner 61b below the field oxide film 62, the wet liner 61b extends laterally under the protrusion 62a of the field oxide film 62. It takes time to penetrate laterally under the projection 62a until the solution reaches the upper edge of the nitride film liner 61b. Therefore, when the pad nitride film 53a removal process is completed, the penetration of the wet etching solution stops at a point shorter than the upper edge of the nitride film liner 61b.

Next, as shown in FIG. 4I, an additional wet etching process removes portions of the field oxide film 62 lying on the surface of the pad oxide film 52 and the semiconductor substrate 51 until the wafer achieves a substantially flat surface. Proceed with the process. As a result of the additional wet etching, the active regions of the inverse narrow effect compensation layer 60 and the semiconductor substrate 51 are exposed to the outside, and the field oxide film 62 having the flat surface is formed of the nitride film liner 61c and the BSG film 59b. The oxide film liner 58a is surrounded.

In a subsequent process, a known semiconductor device manufacturing process is performed to form a channel region, a gate oxide film, a gate electrode, a source and a drain region.

According to the above-described embodiment, the nitride film liner 61b remaining in FIG. 4H adds a wet process of the field oxide film 62 to reduce the step with the active area, or boundary between the active area and the field oxide film 62 in the cleaning step. It prevents the moat phenomenon caused by the loss of oxide film in the vicinity. In addition, the nitride film liner 61b prevents the back diffusion of boron in the BSG film 59b due to the introduction of the BSG film 59b into the field oxide film 62.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above is capable of ion implantation to compensate for the inverse narrowing effect without the addition of a mask process, and the effect of ion implantation on the interface between the trench sidewall and the field oxide layer without the ion implantation while giving a tilt angle is effective. have.

In addition, since the nitride liner can be extended horizontally to the active region, the oxide layer can be prevented from being lost near the boundary between the active region and the field oxide layer during the subsequent etching or cleaning process.

Claims (8)

Forming a mask layer defining an active region smaller than a value set on the semiconductor substrate; Forming a spacer on sidewalls of the mask layer; Etching the semiconductor substrate using the mask layer and the spacer as an etch mask to form a trench; Removing the spacer to expose a shoulder portion of the trench; Ion implanting a dopant using the mask layer as a mask to form an inverse narrow effect compensation layer; Forming an oxide liner covering the entire region of the trench and the shoulder portion of the trench; Forming a nitride film liner on the entire surface including the oxide film liner; Forming a field oxide film on the nitride film liner until the trench is filled; Planarizing the field oxide layer until the surface of the mask layer is exposed; And Removing the mask layer Device isolation method of a semiconductor device comprising a. The method of claim 1, Forming the inverse narrow effect compensation layer, Ion implantation of the dopant while giving a tilt angle or ion implantation method of the semiconductor device, characterized in that the. The method of claim 2, And the dopant is boron or boron difluoride. The method of claim 1, And the spacer is a nitride film. Forming a mask layer defining an active region smaller than a value set on the semiconductor substrate; Forming a spacer on sidewalls of the mask layer; Forming a trench by etching the semiconductor substrate using the mask layer and the spacer as an etch mask; Removing the spacer to expose a shoulder portion of the trench; Forming a dopant enrichment layer on the entire surface including the exposed trenches; Driving a dopant in the dopant hatching layer toward the trench and the shoulder portion to form an inverse narrow effect compensation layer; Forming a nitride film liner on the dopant enrichment layer; Forming a field oxide film on the nitride film liner until the trench is filled; Planarizing the field oxide layer until the surface of the mask layer is exposed; And Removing the mask layer Device isolation method of a semiconductor device comprising a. The method of claim 5, Before forming the dopant enrichment layer, And oxidizing the sidewalls of the trench. The method of claim 5, Before forming the dopant enrichment layer, And cleaning the sidewalls of the trench. The method of claim 5, And the dopant enrichment layer is a BSG film.