KR100414742B1 - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor device Download PDFInfo
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- KR100414742B1 KR100414742B1 KR1019960068916A KR19960068916A KR100414742B1 KR 100414742 B1 KR100414742 B1 KR 100414742B1 KR 1019960068916 A KR1019960068916 A KR 1019960068916A KR 19960068916 A KR19960068916 A KR 19960068916A KR 100414742 B1 KR100414742 B1 KR 100414742B1
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- 238000000034 method Methods 0.000 title claims abstract description 89
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000002955 isolation Methods 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000005498 polishing Methods 0.000 claims abstract description 9
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910019142 PO4 Inorganic materials 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 claims description 2
- 239000010452 phosphate Substances 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract 1
- 230000001131 transforming effect Effects 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009271 trench method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 특히 트랜치를 이용한 소자분리절연막 형성공정시 CMP 공정을 이용하여 상부면을 평탄화시킴으로써 후속공정을 용이하게 실시할 수 있도록 하는 기술에 관한 것이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, and more particularly, to a technology for easily performing a subsequent process by planarizing an upper surface by using a CMP process during a device isolation insulating film formation process using a trench.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼 ( dimension ) 을 축소하는 것과, 소자간에 존재하는 분리영역 ( isolation region ) 의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리기술이 메모리 셀 사이즈 ( memory cell size ) 를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. Device isolation technology determines the memory cell size in terms of size.
소자분리절연막을 제조하는 종래기술로는 절연물 분리방식의 로코스 ( LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함 ) 방법, 실리콘기판 상부에 산화막, 다결정실리콘층, 질화막순으로 적층한 구조의 피.비.엘. ( Poly - Buffed LOCOS, 이하에서 PBL 이라 함 ) 방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치 ( trench ) 방법 등이 있다.Conventional methods for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method of insulating material isolation, LOCOS, polycrystalline silicon layer and nitride film on top of silicon substrate. B.L. (Poly-Buffed LOCOS, hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in the substrate, and the like.
그러나, 상기 LOCOS 방법으로 소자분리산화막을 미세화할 때 공정상 또는 전기적인 문제가 발생한다. 그중의 하나는, 소자분리절연막만으로는 전기적으로 소자를 완전히 분리할 수 없다는 것이다.However, a process or electrical problem occurs when the device isolation oxide film is miniaturized by the LOCOS method. One of them is that the device isolation insulating film alone cannot completely separate the device.
그래서, 소자분리산화막을 형성하는 산화공정 직전 또는 이후에 고농도의 B 또는 BF2이온을 소자분리절연막의 하부에 이온주입시켜 격리효과를 보상해 주는데, 이 공정을 N 채널 필드 임플란트 ( N - channel field implant ) 공정, 즉 채널스토퍼 ( channel stopper ) 형성공정이라고 한다.Therefore, a high concentration of B or BF 2 ions are implanted into the lower portion of the device isolation insulating film immediately before or after the oxidation process to form the device isolation oxide film, thereby compensating the isolation effect. It is called an implant) process, that is, a channel stopper forming process.
이때, 채널스토퍼로 사용되는 B 또는 BF2는 소자분리산화 공정 중에 또는 기타 열처리공정시에 활성영역으로 측면확산하여 활성영역이 좁아지며, 활성트랜지스터의 문턱전압 ( threshold voltage ) 을 높이는 내로우 ( narrow ) 채널 효과를 일으키고, 소오스/드레인을 향해 측면확산하여 N+접합과 중첩되면서 일어나는 N+접합 브레이크다운 전압 ( breakdown voltage ) 의 감소나 접합누출의 증대 등의 문제를 일으키며, 소자분리절연막의 형성 후에 채널스톱 불순물을 주입할 경우에는 고에너지의 이온주입을 하기 때문에 소자분리절연막의 끝부분이 손상되어 게이트산화막의 열화를 가져올 수 있다. 그리고, 소자분리절연막의 상층부는 기판과 단차를 형성하여 후속공정의 진행시 어려움이 있다.At this time, B or BF 2, which is used as a channel stopper, is diffused sideways into the active region during the device isolation oxidation process or other heat treatment process, thereby narrowing the active region and narrowing the threshold voltage of the active transistor. ) causing the channel effect, by lateral diffusion toward the source / drain causes problems such as increase in the reduction or junction leakage of the N + junction breakdown voltage (breakdown voltage) occurs while overlapping the N + junction, after formation of the device isolation insulating film In the case of implanting channel stop impurities, high energy ion implantation may damage the tip of the device isolation insulating layer, resulting in deterioration of the gate oxide layer. In addition, the upper layer portion of the device isolation insulating film forms a step with the substrate, and thus there is a difficulty in the subsequent process.
그리고, 상기 PBL 을 사용하는 경우, 필드산화시에 산소의 측면확산에 의하여 버즈빅이 발생한다. 즉, 활성영역이 작아져 활성영역을 효과적으로 활용하지 못하며, 필드산화막의 두께가 두껍기 때문에 단차가 형성되어 후속공정에 어려움을 준다. 그리고, 기판상부의 다결정실리콘층으로 인하여 필드산화시 기판내부로 형성되는 소자분리절연막이 타기법에 비하여 상대적으로 작기 때문에 타기법에 비해 신뢰성을 약화시킬 수 있다.In the case of using the above-mentioned PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. Further, due to the polysilicon layer on the substrate, the device isolation insulating film formed inside the substrate during field oxidation is relatively smaller than that of the hitting method, thereby reducing the reliability of the hitting method.
이상에서 설명한 LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 됨으로써 후속공정을 어렵게 하는 단점이 있다.The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is made difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.
이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고 후속공정을 평탄화시킴으로써 후속공정을 용이하게 실시할 수 있도록 하였다.In order to solve this disadvantage, the semiconductor substrate is etched to form a trench, and the trench is buried, and then the CMP method is used to planarize the top surface and to planarize the subsequent process so that the subsequent process can be easily performed.
도 1 는 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한단면도이다.1 is a cross-sectional view illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.
먼저, 반도체기판(31) 상부에 패드산화막(33)을 형성하고, 상기 패드산화막(33) 상부에 질화막을 형성한다.First, a pad oxide film 33 is formed on the semiconductor substrate 31, and a nitride film is formed on the pad oxide film 33.
그리고, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 질화막(35)과 패드산화막(33) 및 일정두께의 반도체기판(31)을 식각하여 상기 반도체기판(31)에 트렌치(37)를 형성한다.In addition, the trench 37 is formed on the semiconductor substrate 31 by etching the nitride layer 35, the pad oxide layer 33, and the semiconductor substrate 31 having a predetermined thickness by an etching process using an element isolation mask (not shown). do.
그 다음에, 상기 트렌치(37)를 매립하는 산화막(39)을 형성하고, 상기 산화막(39)을 CMP하여 상부면을 평탄하게 형성한다.Next, an oxide film 39 filling the trench 37 is formed, and the oxide film 39 is CMP to form a flat top surface.
그러나, 상기 폭이 넓은 소자분리영역은 CMP 공정시 디싱 ( dishing ) 현상을 발생하여 후속공정인 질화막(35)과 패드산화막(33) 제거함으로써 소자분리절연막을 형성할 때 상기 산화막(39)이 제거되어 상기 트렌치(37)를 완전히 매립하는 소자분리절연막(39)을 형성하지 못한다.However, the wide device isolation region may cause dishing during the CMP process to remove the oxide layer 39 and the pad oxide layer 33 to remove the oxide layer 39. As a result, the device isolation insulating layer 39 may not be formed to completely fill the trench 37.
여기서, 디싱현상은 상기 도 1 의 ⓐ 만큼 발생한다. (도 1)Here, dishing occurs as much as ⓐ in FIG. 1. (Figure 1)
상기한 바와같이 종래기술에 따른 반도체소자의 소자분리절연막 형성방법은, 트렌치를 매립하는 절연막의 상부면을 평탄하게 형성할 수 없어 후속공정을 어렵게하고 소자분리의 특성을 저하시켜 반도체소자의 수율을 저하시키고 반도체소자의 특성 및 신뢰성을 어렵게 하며 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method of forming a device isolation insulating film of a semiconductor device according to the prior art, the upper surface of the insulating film filling the trench cannot be formed flatly, which makes subsequent processing difficult and deteriorates the characteristics of device isolation, thereby improving the yield of the semiconductor device. There is a problem in that it lowers, makes the characteristics and reliability of the semiconductor device difficult, and thus makes the integration of the semiconductor device difficult.
따라서, 본 발명의 상기한 종래기술의 문제점을 해결하기위하여, 트렌치를매립하는 평탄화된 소자분리절연막을 형성하여 후속공정을 용이하게 함으로써 반도체소자의 수율을 향상시키고 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems of the prior art of the present invention, by forming a flattened device isolation insulating film filling the trench to facilitate the subsequent process to improve the yield of the semiconductor device and improve the characteristics and reliability of the semiconductor device Accordingly, an object of the present invention is to provide a method for forming a device isolation insulating film of a semiconductor device, which enables high integration of the semiconductor device.
도 1 은 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method of forming a device isolation insulating film of a semiconductor device according to the prior art.
도 2a 내지 도 2e 는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.2A through 2E are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 반도체기판 13,33 : 패드산화막11,31: semiconductor substrate 13,33: pad oxide film
15,35 : 질화막 17 : 다결정실리콘막15,35 nitride film 17 polycrystalline silicon film
19,37 : 트렌치 21,39 : 산화막19,37: trench 21,39: oxide film
23 : CVD 산화막 35 : 소자분리절연막23 CVD oxide film 35 device isolation insulating film
ⓐ : 디싱(dishing)현상이 발생된 부분Ⓐ: the part where dishing occurs
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은,In order to achieve the above object, a device isolation insulating film forming method of a semiconductor device according to the present invention,
반도체기판을 일정두께 식각하고 이를 매립하는 트렌치형 소자분리절연막 형성방법에 있어서,In the trench type device isolation insulating film forming method of etching a semiconductor substrate to a certain thickness and buried it,
상기 반도체기판 상부에 제1절연막과 제2절연막을 각각 일정두께 형성하는 공정과,Forming a first insulating film and a second insulating film on the semiconductor substrate at a predetermined thickness;
상기 제2절연막 상부에 절연막과 연마속도비가 큰 물질층을 일정두께 형성하는 공정과,Forming a thickness of a material layer having a large polishing rate ratio on the second insulating film, the predetermined thickness;
상기 반도체기판에 트렌치를 형성하는 공정과,Forming a trench in the semiconductor substrate;
상기 반도체기판의 노출된 부분을 산화시켜 제3절연막을 형성하는 공정과,Oxidizing the exposed portion of the semiconductor substrate to form a third insulating film;
상기 트렌치를 매립하는 제4절연막을 형성하는 공정과,Forming a fourth insulating film filling the trench;
상기 제4절연막을 연마하는 제1 CMP 공정을 실시하는 공정과,Performing a first CMP process for polishing the fourth insulating film;
상기 물질층과 제4절연막을 연마하는 제2 CMP 공정을 실시하는 공정과,Performing a second CMP process for polishing the material layer and a fourth insulating film;
상기 제2,1절연막을 제거하는 공정과,Removing the second and first insulating films;
상기 반도체기판 표면 상부를 세정하는 공정을 포함하는 것을 특징으로한다.And cleaning the upper surface of the semiconductor substrate.
한편, 상기한 목적을 달성하기위한 본 발명의 원리는, 종래기술에서 반도체기판 상부에 형성한 질화막 상부에 산화막보다 CMP 공정시의 연마속도가 빠른 다결정실리콘막을 형성하고, 상기 다결정실리콘막을 노출시키는 제1 CMP 공정을 실시한 다음, 제2 CMP 공정을 실시함으로써 상부면을 평탄화시키고 질화막을 제거한 다음, HF 용액을 이용한 두번의 세정공정을 실시하여 상기 반도체기판을 노출시키는 동시에 상기 산화막을 식각하여 상기 트렌치를 매립하는 평탄화된 소자분리절연막을 형성하는 함으로써 후속공정을 용이하게 하는 것이다.On the other hand, the principle of the present invention for achieving the above object is to form a polysilicon film on the nitride film formed on the semiconductor substrate in the prior art faster than the oxide film in the polishing rate at the time of the CMP process, and to expose the polysilicon film After the 1 CMP process, the second CMP process is performed to planarize the upper surface, remove the nitride film, and then perform two cleaning processes using HF solution to expose the semiconductor substrate and simultaneously etch the oxide film to etch the trench. The subsequent process is facilitated by forming a planarized device isolation insulating film to be embedded.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e 는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 패드산화막(13), 질화막(15) 및 다결정실리콘막(17)을 각각 일정두께 형성한다.First, a pad oxide film 13, a nitride film 15, and a polysilicon film 17 are formed to have a predetermined thickness on the semiconductor substrate 11, respectively.
그리고, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 다결정실리콘막(17), 질화막(15), 패드산화막(13) 및 일정두께의 반도체기판(11)을 식각하여 트렌치(19)를 형성한다.The trench 19 is formed by etching the polysilicon layer 17, the nitride layer 15, the pad oxide layer 13, and the semiconductor substrate 11 having a predetermined thickness by an etching process using an element isolation mask (not shown). do.
여기서, 상기 패드산화막(13)은 70 ∼ 300 Å 정도의 두께로 형성한다. 그리고, 상기 질화막(15)은 1000 ∼ 3000 Å 정도의 두께로 형성하며, 상기 다결정실리콘막(17)은 500 ∼ 1500 Å 정도의 두께로 형성한다.Here, the pad oxide film 13 is formed to a thickness of about 70 ~ 300 Å. The nitride film 15 is formed to a thickness of about 1000 to 3000 mm 3, and the polysilicon film 17 is formed to a thickness of about 500 to 1500 mm 3.
상기 트렌치(19)는 반도체기판(11)을 1000 ∼ 4000 Å 제도의 두께만큼 식각하여 형성한 것이다.The trench 19 is formed by etching the semiconductor substrate 11 by a thickness of 1000 to 4000 GPa.
그 다음에, 상기 반도체기판(11)의 노출된 표면을 산화시켜 70 ∼ 300 Å 정도 두께의 산화막(21)을 형성한다. (도 2a)Next, the exposed surface of the semiconductor substrate 11 is oxidized to form an oxide film 21 having a thickness of about 70 to 300 kPa. (FIG. 2A)
그리고, 상기 트렌치(19)를 매립하는 CVD 산화막(23)을 전체표면상부에 도포한다.Then, a CVD oxide film 23 filling the trench 19 is applied over the entire surface.
이때, 상기 CVD 산화막(23)을 4000 ~ 7000 Å 정도의 두께로 증착함으로써 상기 트렌치(19)와 상기 반도체기판(11)의 상부 구조물은 단차를 갖는다. (도 2b)At this time, by depositing the CVD oxide film 23 to a thickness of about 4000 ~ 7000 Å, the upper structure of the trench 19 and the semiconductor substrate 11 has a step. (FIG. 2B)
그 다음에, 상기 CVD 산화막(23)을 연마하는 제1 CMP 공정을 실시한다. 이때, 상기 제1 CMP 공정은 7 ∼ 9 피.에스.아이. ( Pounds per Square Inch, 이하에서 psi 라 함 ) 의 압력으로 상기 다결정실리콘막(17)이 노출될 때까지 실시한다.Next, a first CMP process of polishing the CVD oxide film 23 is performed. In this case, the first CMP process is 7 to 9 P.S. (Pounds per square inch, psi below) until the polysilicon film 17 is exposed.
이때, 상기 CVD 산화막(23)은 약간의 디싱현상이 발생하되, 상기 다결정실리콘막(17)보다 낮은 두께로 발생한다. (도 2c)At this time, the CVD oxide film 23 generates a slight dishing phenomenon, but a lower thickness than the polysilicon film 17. (FIG. 2C)
그 다음에, 상기 질화막(15)을 노출시키는 제2 CMP 공정을 실시한다.Next, a second CMP process is performed in which the nitride film 15 is exposed.
이때, 상기 제2 CMP 공정은 상기 다결정실리콘막(17)과 CVD 산화막(23)이 70 ~ 130 : 1 의 연마속도를 갖도록 압력을 1 ~ 3 psi 로 조절하여 실시한다. 이로인하여, 상기 다결정실리콘막(17)과 약간의 CVD 산화막(23)이 연마된다. (도 2d)In this case, the second CMP process is performed by adjusting the pressure to 1 to 3 psi so that the polysilicon film 17 and the CVD oxide film 23 have a polishing rate of 70 to 130: 1. Thus, the polysilicon film 17 and some CVD oxide films 23 are polished. (FIG. 2D)
그 다음에, 인산용액을 이용한 제1습식식각을 70 ~ 130 분 동안 실시하여 상기 질화막(15)을 제거한다.Then, the first wet etching using the phosphate solution is performed for 70 to 130 minutes to remove the nitride film 15.
이때, 상기 CVD 산화막(23)은 거의 제거되지 않지만, 상기 패드산화막(13)은 상부가 일부 손상된다.At this time, the CVD oxide film 23 is hardly removed, but the pad oxide film 13 is partially damaged.
그 다음에, 상기 패드산화막(13)을 제거하는 제2습식식각공정을 250 ∼ 500초 동안 실시한다. 이때, 상기 CVD 산화막(23) 일정두께가 식각된다.Next, a second wet etching process for removing the pad oxide layer 13 is performed for 250 to 500 seconds. At this time, a predetermined thickness of the CVD oxide film 23 is etched.
그리고, 상기 반도체기판(11)의 활성영역에 게이트산화막(도시안됨)을 형성하기 위하여 상기 반도체기판(11)의 활성영역을 세정할 수 있는 제3습식식각공정을 HF 용액으로 250 ~ 500 초 동안 실시한다. 이때, 상기 반도체기판(11)의 상부로 돌출되어 있는 상기 CVD 산화막(23)이 제거되어 상부면을 평탄하게 형성한다.In addition, a third wet etching process for cleaning the active region of the semiconductor substrate 11 to form a gate oxide layer (not shown) in the active region of the semiconductor substrate 11 for 250 to 500 seconds using HF solution. Conduct. At this time, the CVD oxide film 23 protruding to the upper portion of the semiconductor substrate 11 is removed to form a flat top surface.
이로인하여, 상기 트렌치(19)를 매립하며 상부면이 평탄한 소자분리절연막(25)을 형성한다.As a result, the trench 19 may be filled to form a device isolation insulating film 25 having a flat top surface.
여기서, 상기 제2습식공정과 제3습식공정은 상기와 같이 각각 250 ∼ 500 초 동안 실시할 수도 있으나, 상기 제2습식공정과 제3습식공정의 식각공정시간을 달리하여 전체공정시간이 500 ∼ 1000 초가 되도록 할 수도 있다 (도 2e)Here, the second wet process and the third wet process may be performed for 250 to 500 seconds, respectively, as described above, but the total process time is different from the etching process time of the second wet process and the third wet process. It can also be 1000 seconds (FIG. 2E).
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은, CMP 공정을 이용하여 트렌치형 소자분리절연막을 형성하여 후속공정을 용이하게 실시할 수 있도록 함으로써 반도체소자의 수율을 향상시키고 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, in the method of forming a device isolation insulating film of the semiconductor device according to the present invention, a trench type device isolation insulating film is formed using a CMP process so that subsequent processes can be easily performed, thereby improving the yield of the semiconductor device and the semiconductor. There is an advantage to improve the characteristics and reliability of the device and thereby to enable high integration of the semiconductor device.
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| JPH05315441A (en) * | 1992-01-30 | 1993-11-26 | Sony Corp | Manufacture of semiconductor device provided with polishing process |
| JPH07297274A (en) * | 1994-04-26 | 1995-11-10 | Toshiba Corp | Manufacture of semiconductor device |
| US5492858A (en) * | 1994-04-20 | 1996-02-20 | Digital Equipment Corporation | Shallow trench isolation process for high aspect ratio trenches |
| JPH08181108A (en) * | 1994-12-21 | 1996-07-12 | Sony Corp | Method of manufacturing semiconductor device including step of forming element isolation region |
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| JPH05315441A (en) * | 1992-01-30 | 1993-11-26 | Sony Corp | Manufacture of semiconductor device provided with polishing process |
| US5492858A (en) * | 1994-04-20 | 1996-02-20 | Digital Equipment Corporation | Shallow trench isolation process for high aspect ratio trenches |
| JPH07297274A (en) * | 1994-04-26 | 1995-11-10 | Toshiba Corp | Manufacture of semiconductor device |
| JPH08181108A (en) * | 1994-12-21 | 1996-07-12 | Sony Corp | Method of manufacturing semiconductor device including step of forming element isolation region |
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