KR20000004535A - Method for forming isolating insulator of semiconductor devices - Google Patents

Method for forming isolating insulator of semiconductor devices Download PDF

Info

Publication number
KR20000004535A
KR20000004535A KR1019980025979A KR19980025979A KR20000004535A KR 20000004535 A KR20000004535 A KR 20000004535A KR 1019980025979 A KR1019980025979 A KR 1019980025979A KR 19980025979 A KR19980025979 A KR 19980025979A KR 20000004535 A KR20000004535 A KR 20000004535A
Authority
KR
South Korea
Prior art keywords
forming
semiconductor substrate
insulating film
photoresist pattern
device isolation
Prior art date
Application number
KR1019980025979A
Other languages
Korean (ko)
Inventor
윤현구
강원준
Original Assignee
김영환
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업 주식회사 filed Critical 김영환
Priority to KR1019980025979A priority Critical patent/KR20000004535A/en
Publication of KR20000004535A publication Critical patent/KR20000004535A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose

Abstract

PURPOSE: A method of forming an isolating insulator of semiconductor devices is provided to simplify manufacturing process and improve its performance by using a simple oxidation process without sophisticated trench etching processes. CONSTITUTION: A method comprises several steps of forming a pad insulator(13) on a semiconductor substrate(11); forming an impurity region(19) by implanting oxygen ions(17) into the semiconductor substrate(11) using a photoresist pattern(15) defined an isolation region as an implantation mask; removing the photoresist pattern(15); and forming an isolating insulator(21) by reacting the implanted oxygen ions and the silicon using an oxidation process of the impurity region(19).

Description

반도체소자의 소자분리절연막 형성방법Device isolation insulating film formation method of semiconductor device

본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 특히 마스크를 이용하여 반도체기판에 불순물 주입영역을 형성하고 이를 어닐링공정으로 산화시켜 소자분리절연막을 형성함으로써 공정을 단순화시키고 그에 따른 소자의 특성을 향상시킬 수 있는 기술에 관한 것이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, and in particular, by forming an impurity implantation region in a semiconductor substrate using a mask and oxidizing it by an annealing process to form a device isolation insulating film, thereby simplifying the process and characteristics of the device accordingly. It is about a technology that can improve.

고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼 ( dimension ) 을 축소하는 것과, 소자간에 존재하는 분리영역 ( isolation region ) 의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리기술이 메모리 셀 사이즈 ( memory cell size ) 를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. Device isolation technology determines the memory cell size in terms of size.

소자분리절연막을 제조하는 종래기술로는 절연물 분리방식의 로코스 ( LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함 ) 방법, 실리콘기판상부에 산화막, 다결정실리콘층, 질화막순으로 적층한 구조의 피.비.엘. ( Poly - Buffed LOCOS, 이하에서 PBL 이라 함 ) 방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치 ( trench ) 방법 등이 있다.Conventional techniques for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method, an oxide film, a polysilicon layer, and a nitride film on a silicon substrate. B.L. (Poly-Buffed LOCOS, hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in the substrate, and the like.

그러나, 상기 LOCOS 방법으로 소자분리산화막을 미세화할 때 공정상 또는 전기적인 문제가 발생한다. 그중의 하나는, 소자분리절연막만으로는 전기적으로 소자를 완전히 분리할 수 없다는 것이다.However, a process or electrical problem occurs when the device isolation oxide film is miniaturized by the LOCOS method. One of them is that the device isolation insulating film alone cannot completely separate the device.

그래서, 소자분리산화막을 형성하는 산화공정 직전 또는 이후에 고농도의 B 또는 BF2이온을 소자분리절연막의 하부에 이온주입시켜 격리효과를 보상해 주는데, 이 공정을 N 채널 필드 임플란트 ( N - channel field implant ) 공정, 즉 채널스토퍼 ( channel stopper ) 형성공정이라고 한다.Therefore, a high concentration of B or BF 2 ions are implanted into the lower portion of the device isolation insulating film immediately before or after the oxidation process to form the device isolation oxide film, thereby compensating the isolation effect. It is called an implant) process, that is, a channel stopper forming process.

이때, 채널스토퍼로 사용되는 B 또는 BF2는 소자분리산화공정중에 또는 기타 열처리공정시에 활성영역으로 측면확산하여 활성영역이 좁아지며, 활성트랜지스터의 문턱전압 ( threshold voltage ) 을 높이는 내로우 ( narrow ) 채널 효과를 일으키고, 소오스/드레인을 향해 측면확산하여 N+접합과 중첩되면서 일어나는 N+접합 브레이크다운 전압 ( breakdown voltage ) 의 감소나 접합누출의 증대등의 문제를 일으키며, 소자분리절연막의 형성후에 채널스톱 불순물을 주입할 경우에는 고에너지의 이온주입을 하기 때문에 소자분리절연막의 끝부분이 손상되어 게이트 산화막의 열화를 가져올 수 있다. 그리고, 소자분리절연막의 상층부는 기판과 단차를 형성하여 후속공정의 진행시 어려움이 있다.At this time, B or BF 2 used as a channel stopper is diffused laterally into the active region during the device isolation oxidation process or other heat treatment process, thereby narrowing the active region and narrowing the threshold voltage of the active transistor. ) causing the channel effect, by lateral diffusion toward the source / drain causes problems such as increase in the reduction or junction leakage of the N + junction breakdown voltage (breakdown voltage) occurs while overlapping the N + junction, after formation of the device isolation insulating film In the case of implanting channel stop impurities, ion implantation of high energy is performed, so that the tip of the device isolation insulating layer is damaged, resulting in deterioration of the gate oxide layer. In addition, the upper layer portion of the device isolation insulating film forms a step with the substrate, which makes it difficult to proceed with subsequent processes.

그리고, 상기 PBL 을 사용하는 경우, 필드산화시에 산소의 측면확산에 의하여 버즈빅이 발생한다. 즉, 활성영역이 작아져 활성영역을 효과적으로 활용하지 못하며, 필드산화막의 두께가 두껍기 때문에 단차가 형성되어 후속공정에 어려움을 준다. 그리고, 기판상부의 다결정실리콘층으로 인하여 필드산화시 기판내부로 형성되는 소자분리절연막이 타기법에 비하여 상대적으로 작기 때문에 타기법에 비해 신뢰성을 약화시킬 수 있다.In the case of using the above-mentioned PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. Further, due to the polysilicon layer on the substrate, the device isolation insulating film formed inside the substrate during field oxidation is relatively smaller than that of the hitting method, thereby reducing the reliability of the hitting method.

이상에서 설명한 LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 됨으로써 후속공정을 어렵게 하는 단점이 있다.The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is made difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.

이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 낮은 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고 후속공정을 평탄화시킴으로써 후속공정을 용이하게 실시할 수 있도록 하는 얕은 트렌치 소자분리 ( shallow tranch isolation, 이하에서 STI 라 함 ) 방법을 사용하였다.In order to solve this drawback, the semiconductor substrate is etched to form a low trench, and the trench is buried, and then the shallow process that makes the subsequent process easier by flattening the upper surface and the subsequent process using the CMP method. Trench isolation (hereinafter referred to as STI) method was used.

도 1 은 종래기술에 따른 STI 방법으로 소자분리절연막 형성방법을 설명한 것을 도시한 단면도이다.1 is a cross-sectional view illustrating a method of forming a device isolation insulating film by the STI method according to the related art.

먼저, 반도체기판(31) 상부에 패드산화막(도시안됨)과 패드질화막(도시안됨)의 적층구조로 패드절연막을 형성하고, 소자분리마스크를 이용한 식각공정으로 패드절연막과 일정두께의 반도체기판(31)을 식각하여 트렌치를 형성한 다음, 상기 트렌치 표면을 산화시켜 트렌치 표면의 격자구조를 보상하고 상기 트렌치를 매립하는 CVD 산화막을 형성한 다음, 이를 치밀화시키고 평탄화식각공정과 패드질화막 제거공정을 실시한 다음, 세정공정을 실시하여 STI 형의 소자분리산화막(33)을 형성한다. (도 1)First, a pad insulating film is formed on the semiconductor substrate 31 by a stacked structure of a pad oxide film (not shown) and a pad nitride film (not shown), and the pad insulating film and the semiconductor substrate 31 having a predetermined thickness are formed by an etching process using an element isolation mask. ) To form a trench, and then oxidize the trench surface to compensate for the lattice structure of the trench surface and to form a CVD oxide film filling the trench, densifying it, and performing a planarization etching process and a pad nitride film removing process. A cleaning process is performed to form an element isolation oxide film 33 of STI type. (Figure 1)

상기한 바와같이 종래기술에 따른 반도체소자의 소자분리절연막 형성방법은, 공정이 복잡하고 소자분리절연막의 모서리 부분을 조절하는데 많은 어려움이 있어 반도체소자의 특성 및 신뢰성이 저하되는 문제점이 있다.As described above, the method of forming a device isolation insulating film of a semiconductor device according to the prior art has a problem in that the process is complicated and many difficulties in controlling the corners of the device isolation insulating film are deteriorated, thereby degrading the characteristics and reliability of the semiconductor device.

따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 소자분리영역에 산소이온을 주입하고 이를 어닐링시켜 소자분리절연막을 형성함으로써 공저을 단순화시키고 그에 따른 소자의 특성을 향상시키는 반도체소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above-mentioned problems of the prior art, the device isolation of the semiconductor device is simplified by injecting oxygen ions into the device isolation region and annealing them to form a device isolation insulating film, thereby simplifying the co-operation and improving the characteristics of the device. It is an object of the present invention to provide a method for forming an insulating film.

도 1 은 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method of forming an isolation film in a semiconductor device according to the prior art.

도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.2A to 2C are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device in accordance with an embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11,31 : 반도체기판 13 : 패드산화막11,31: semiconductor substrate 13: pad oxide film

15 : 감광막패턴 17 : 산소이온15: photosensitive film pattern 17: oxygen ion

19 : 불순물 주입영역 21,33 : 소자분리산화막19: impurity implantation area 21,33: device isolation oxide film

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은,In order to achieve the above object, a device isolation insulating film forming method of a semiconductor device according to the present invention,

반도체기판 상부에 패드절연막을 형성하는 공정과,Forming a pad insulating film on the semiconductor substrate;

상기 패드절연막 상부에 소자분리마스크를 이용하여 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the pad insulating layer by using an isolation mask;

상기 감광막패턴을 마스크로하여 상기 반도체기판에 산소이온을 이온주입하여 불순물 주입영역을 형성하는 공정과,Forming an impurity implantation region by ion implanting oxygen ions into the semiconductor substrate using the photoresist pattern as a mask;

상기 감광막패턴을 제거하는 공정과,Removing the photoresist pattern;

상기 반도체기판을 어닐링하여 상기 불순물 주입영역을 산화시킴으로써 소자분리절연막을 형성하는 공정을 포함하는 것을 특징으로한다.And forming an isolation film by annealing the semiconductor substrate to oxidize the impurity implantation region.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to an embodiment of the present invention.

먼저, 반도체기판(11) 상부에 패드산화막(13)을 형성하고 그 상부에 감광막패턴(15)을 형성한다. 이때, 상기 감광막패턴(15)은 소자분리마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다.First, a pad oxide film 13 is formed on the semiconductor substrate 11 and a photoresist pattern 15 is formed on the pad oxide film 13. In this case, the photoresist pattern 15 is formed by an exposure and development process using an element isolation mask (not shown).

그리고, 상기 감광막패턴(15)을 마스크로하여 상기 반도체기판에 산소이온(17)을 이온주입함으로써 불순물 주입영역(19)을 형성한다.The impurity implantation region 19 is formed by ion implanting oxygen ions 17 into the semiconductor substrate using the photoresist pattern 15 as a mask.

그리고, 상기 감광막패턴(15)을 제거한다. (도 2a, 도 2b)Then, the photosensitive film pattern 15 is removed. (FIG. 2A, FIG. 2B)

그 다음에, 상기 반도체기판(11)을 어닐링하여 상기 불순물 주입영역(19)에 주입된 산소이온과 실리콘을 반응시킴으로써 공정을 단순화시켜 소자분리산화막(21)을 형성한다. (도 2c)Then, the semiconductor substrate 11 is annealed to react the oxygen ions injected into the impurity implantation region 19 with silicon to simplify the process to form the device isolation oxide film 21. (FIG. 2C)

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은, 트렌치 식각공정을 생략하여 공정을 단순화시킴으로써 트렌치 식각공정시 유발될 수 있는 문제점을 방지하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method of forming a device isolation insulating film of the semiconductor device according to the present invention may simplify the process by eliminating the trench etching process, thereby preventing problems that may be caused during the trench etching process, thereby improving characteristics and reliability of the semiconductor device. It can be effective.

Claims (2)

반도체기판 상부에 패드절연막을 형성하는 공정과,Forming a pad insulating film on the semiconductor substrate; 상기 패드절연막 상부에 소자분리마스크를 이용하여 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the pad insulating layer by using an isolation mask; 상기 감광막패턴을 마스크로하여 상기 반도체기판에 산소이온을 이온주입하여 불순물 주입영역을 형성하는 공정과,Forming an impurity implantation region by ion implanting oxygen ions into the semiconductor substrate using the photoresist pattern as a mask; 상기 감광막패턴을 제거하는 공정과,Removing the photoresist pattern; 상기 반도체기판을 어닐링하여 상기 불순물 주입영역을 산화시킴으로써 소자분리절연막을 형성하는 공정을 포함하는 반도체소자의 소자분리절연막 형성방법.Forming a device isolation insulating film by annealing the semiconductor substrate to oxidize the impurity implantation region. 제 1 항에 있어서,The method of claim 1, 상기 패드절연막은 패드산화막의 단층구조로 구비되는 것을 특징으로하는 반도체소자의 소자분리절연막 형성방법.And the pad insulating film has a single layer structure of a pad oxide film.
KR1019980025979A 1998-06-30 1998-06-30 Method for forming isolating insulator of semiconductor devices KR20000004535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980025979A KR20000004535A (en) 1998-06-30 1998-06-30 Method for forming isolating insulator of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980025979A KR20000004535A (en) 1998-06-30 1998-06-30 Method for forming isolating insulator of semiconductor devices

Publications (1)

Publication Number Publication Date
KR20000004535A true KR20000004535A (en) 2000-01-25

Family

ID=19542360

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980025979A KR20000004535A (en) 1998-06-30 1998-06-30 Method for forming isolating insulator of semiconductor devices

Country Status (1)

Country Link
KR (1) KR20000004535A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100571412B1 (en) * 2003-12-26 2006-04-14 동부아남반도체 주식회사 Manufacturing Method of Semiconductor Device
KR100763333B1 (en) * 2006-05-16 2007-10-04 삼성전자주식회사 Method of forming an isolation layer of a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100571412B1 (en) * 2003-12-26 2006-04-14 동부아남반도체 주식회사 Manufacturing Method of Semiconductor Device
KR100763333B1 (en) * 2006-05-16 2007-10-04 삼성전자주식회사 Method of forming an isolation layer of a semiconductor device
US7781302B2 (en) 2006-05-16 2010-08-24 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having isolation regions formed from annealed oxygen ion implanted regions

Similar Documents

Publication Publication Date Title
KR0150105B1 (en) Method of fabricating transistor of semiconductor device
KR20000004535A (en) Method for forming isolating insulator of semiconductor devices
KR100281272B1 (en) Method for forming element isolation insulating film of semiconductor element
KR100622754B1 (en) A method for forming a field oxide of a semiconductor device
KR20000003571A (en) Method for forming element separating insulating film of semiconductor element
KR100632043B1 (en) Method for manufacturing mos transistor
KR100310173B1 (en) Method for manufacturing ldd type cmos transistor
KR100220251B1 (en) Semiconductor device and method of manufacturing the same
KR20000004528A (en) Method for forming an isolating layer of semiconductor devices
KR20000004536A (en) Method for forming an isolating insulator of semiconductor devices
KR20000003574A (en) Element isolating insulating film forming method of semiconductor
KR100414742B1 (en) Method for forming isolation layer of semiconductor device
KR100271801B1 (en) Manufacturing Method of Semiconductor Device
KR100218739B1 (en) Method of forming a device isolation film of semiconductor device
KR100305018B1 (en) Device Separation Method of Semiconductor Devices
JP2005032997A (en) Method for manufacturing semiconductor device having shallow trench isolation structure
KR960013502B1 (en) Field isolated film forming method of semiconductor device
KR100225383B1 (en) Method of manufacturing semiconductor device
KR930001290B1 (en) Mos transistor with high junction voltage and its manufacturing method
KR19980029591A (en) Manufacturing Method of Dual Gate SeaMOS Transistor
KR20000004537A (en) Method for forming an isolating insulator of semiconductor devices
KR100325444B1 (en) Method for fabricating metal oxide semiconductor transistor of low doping drain structure
KR100357173B1 (en) Method for manufacturing thin film transistor
KR100264079B1 (en) Manufacturing method of a semiconductor device
KR100569570B1 (en) Manufacturing method of MOS field effect transistor of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination