KR100271801B1 - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR100271801B1 KR100271801B1 KR1019980016694A KR19980016694A KR100271801B1 KR 100271801 B1 KR100271801 B1 KR 100271801B1 KR 1019980016694 A KR1019980016694 A KR 1019980016694A KR 19980016694 A KR19980016694 A KR 19980016694A KR 100271801 B1 KR100271801 B1 KR 100271801B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000005468 ion implantation Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 32
- 239000012535 impurity Substances 0.000 claims description 15
- 239000010410 layer Substances 0.000 abstract description 43
- 230000000694 effects Effects 0.000 abstract description 17
- 125000001475 halogen functional group Chemical group 0.000 abstract description 14
- 230000005465 channeling Effects 0.000 abstract description 6
- -1 Halo ions Chemical class 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 29
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 고집적소자의 소스/드레인에 적당하도록 종래의 에이치엘디디 방식의 소스/드레인 형성시 문제점으로 나타나는 게이트 라인의 단차가 높아져 소스/드레인 형성용 불순물 이온과 반대 타입의 이온주입을 실시하는 할로이온주입 방식에 있어서 쉐도우효과로 인한 바람직하지 못한 결과를 초래하여 쇼트채널효과(short channel effect)를 효과적으로 억제하지 못하는 문제를 게이트라인 형성 후 종래의 할로이온주입을 실시하고 다시 박막을 형성하여 게이트측벽의 두께를 연장시킨 후 엘디디를 형성하므로서 쇼트채널효과를 억제함은 물론 엘디디 이온주입이나 소스/드레인 이온주입시 채널링효과(channeling effect)를 방지하도록한 더블셀프 에이치엘디디(double self HLDD) 트랜지스터 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, an impurity for forming a source / drain due to an increase in the level of a gate line, which is a problem when forming a source / drain of a conventional HDL type so as to be suitable for a source / drain of a highly integrated device. In the halo ion implantation method that performs ion implantation of the opposite type to the ion, the conventional halo ion after the gate line is formed, which causes undesirable effects due to the shadow effect, and thus does not effectively suppress the short channel effect. Injecting and forming a thin film to extend the thickness of the gate sidewall and then forming an LED to suppress the short channel effect and to prevent the channeling effect during the LED injection or source / drain ion injection. A method of forming a double self HLDD transistor The.
반도체장치가 고집적화 됨에 따라 각각의 셀은 미세해져 내부의 전계 강도가 증가된다. 이러한 전계 강도의 증가는 소자 동작시 드레인 부근의 공핍층에서 채널영역의 캐리어를 가속시켜 게이트산화막으로 주입시키는 핫-캐리어 효과(hot-carrier effect)를 일으킨다. 상기 게이트산화막에 주입된 캐리어는 반도체기판과 게이트산화막의 계면에 준위를 생성시켜 드레쉬홀드전압(threshold voltage : VTH)을 변화시키거나 상호 컨덕턴스를 저하시켜 소자 특성을 저하시킨다. 그러므로, 핫-캐리어 효과에 의한 소자 특성의 저하를 감소시키기 위해 LDD(Lightly Doped Drain) 등과 같이 드레인 구조를 변화시킨 구조를 사용하여야 한다.As the semiconductor device is highly integrated, each cell becomes finer and the internal electric field strength is increased. This increase in electric field strength causes a hot-carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film creates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (VTH) or decreasing mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot-carrier effect, a structure in which the drain structure is changed such as a lightly doped drain (LDD) or the like should be used.
그리고, 채널의 길이가 짧아짐에 따른 펀치-스루 현상을 방지하기 위하여 게이트 형성 후 엘디디 형성전에 기판의 활성영역의 농도를 높이기 위하여 소스/드레인 형성용 불순물 이온과 반대 타입의 할로이온주입을 실시한다.In order to prevent the punch-through phenomenon due to the shortening of the channel, halo ion implantation of the source / drain formation impurity ions is performed to increase the concentration of the active region of the substrate after the gate formation and before the LED formation. .
소자의 고집적도가 요구됨에 따라 종래 엘디디 방식의 솟/드레인 형성방법 역시 쇼트채널효과로 인하여 그 한계에 이르게 되었다. 이 문제를 해결하기 위하여 할로 엘디디방식을 도입하고 있으나, 소자 형성에 있어서 워드 라인으로 사용하는 게이트 라인의 단차가 커지게 되어 할로이온주입시 게이트라인에 의한 쉐도우 효과로 인하여 원하는 이온주입부위인 게이트측벽 하단부의 기판에 이온주입이 효과적으로 이루어지지 아니한다.그리고 엘디디이온주입 후 좁은 거리에서 pn 졍션 또는 np 졍션이 형성되므로 졍션누설전류가 발생한다.As the high integration of the device is required, the conventional method of forming the soot / drain of the LED method also reaches its limit due to the short channel effect. In order to solve this problem, a halo aldi method is introduced, but the step of the gate line used as a word line increases in forming a device, and the gate, which is a desired ion implantation region, is increased due to the shadow effect caused by the gate line when the halo ion is injected. Ion implantation is not effectively performed on the substrate at the lower side of the sidewall, and a pn caption or an np caption is formed at a narrow distance after the insertion of the eldiion, causing a leakage current.
종래의 에이치엘디디 방식의 MISFET(Metal Insulated Semiconductor Field Effect Transistor) 소자 형성 방법은 다음과 같다.A conventional method of forming a MEDI element of a metal insulated semiconductor field effect transistor (MISFET) is as follows.
도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 에이치엘디디(Halo Lightly Doped Drain) 트랜지스터 제조공정 단면도이다.1A to 1C are cross-sectional views illustrating a process of manufacturing a halo lightly doped drain transistor of a semiconductor device according to the related art.
도 1a를 참조하면, 반도체기판(1) 표면의 소정 부분에 STI(Shallow Trench Isolation) 등의 통상적인 선택산화방법에 의해 필드산화막(2)을 형성하여 소자의 활성영역 및 필드영역을 한정한다.Referring to FIG. 1A, a field oxide film 2 is formed on a predetermined portion of the surface of a semiconductor substrate 1 by a conventional selective oxidation method such as shallow trench isolation (STI) to define an active region and a field region of a device.
그 다음, 반도체기판(1)의 표면을 열산화하여 게이트산화막(3)을 형성한다.Then, the surface of the semiconductor substrate 1 is thermally oxidized to form a gate oxide film 3.
게이트산화막(3)의 상부에 도핑된 다결정실리콘층(4)을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착한 다음 다시 그 위에 게이트금속층(5)과 캡핑용 질화막(6)을 차례로 증착하여 형성한다. 이때 질화막 대신 에이치엘디(high temperature low pressure dielectric)를 이용할 수 있다.The doped polysilicon layer 4 on the gate oxide film 3 is deposited by chemical vapor deposition (CVD), and then the gate metal layer 5 and the capping nitride film 6 are deposited thereon. ) Is formed by depositing one after the other. In this case, a high temperature low pressure dielectric (HL) may be used instead of the nitride film.
그리고, 포토리쏘그래피(photolithography) 방법으로 패터닝하여 즉 질화막(6)과 게이트금속층(5) 그리고 다결정실리콘층(4) 및 게이트산화막(3)의 일부를 제거하여 게이트(5, 4)를 한정한다.The gates 5 and 4 are defined by patterning by photolithography, i.e., removing the nitride film 6, the gate metal layer 5, and a part of the polysilicon layer 4 and the gate oxide film 3. .
그 다음 마스킹공정을 실시하고 할로이온주입을 노출된 기판(1)의 전면에 실시하여 게이트 하단 모서리 부위의 기판의 불순물 농도를 높인다. 이때 주입되는 이온은 소스/드레인 형성용 이온과 반대 타입의 이온으로서 p 채널인 경우에는 P+ 혹은 As+ 이온을 사용하고, n 채널인 경우에는 B+ 또는 BF2+를 5E14 ions/㎠ 이하의 농도로 기판에 비스듬히 이온주입을 실시한다.Then, a masking process is performed and a halo ion implantation is performed on the entire surface of the exposed substrate 1 to increase the impurity concentration of the substrate at the lower edge portion of the gate. In this case, the implanted ions are opposite to the source / drain formation ions, and P + or As + ions are used in the p-channel, and B + or BF2 + is inclined to the substrate at a concentration of 5E14 ions / cm 2 or less in the n-channel. Ion implantation is performed.
도 1b에 있어서, 게이트 alc 잔류한 질화막(6)을 마스크로 사용하여 반도체기판(11)의 노출된 부분에 n 채널인 경우에는 P+ 혹은 As+ 이온을 사용하고, p 채널인 경우에는 B+ 또는 BF2+를 1E15 ions/㎠ 이하의 농도로 기판에 엘디디 이온주입을 실시한다.In FIG. 1B, P + or As + ions are used for the n-channel exposed portion of the semiconductor substrate 11 using the nitride film 6 remaining in the gate alc as a mask, and B + or BF2 + for the p-channel. LED implantation is performed on the substrate at a concentration of 1E15 ions / cm 2 or less.
도 1c에 있어서, 이와 같은 기판(1)의 전면에 질화막 또는 산화막을 증착한 다음 이를 에치백하여 게이트측벽(9)을 형성한다.In FIG. 1C, a nitride film or an oxide film is deposited on the entire surface of the substrate 1 and then etched back to form the gate side wall 9.
그리고 게이트 및 게이트측벽(9)을 마스크로 이용한 이온주입을 실시하여 소스/드레인을 형성한다. 이때 n 채널인 경우에는 P+ 혹은 As+ 이온을 사용하고, p 채널인 경우에는 B+ 또는 BF2+를 사용하여 1E17 ions/㎠ 이하의 농도로 기판에 소스/드레인 형성용 이온주입을 실시한다.Then, ion implantation using the gate and the gate side wall 9 as a mask is performed to form a source / drain. In the case of n channel, P + or As + ions are used, and in the case of p channel, B + or BF2 + is used to perform ion implantation for source / drain formation on a substrate at a concentration of 1E17 ions / cm 2 or less.
그리고 층간절연층(도시안함)을 형성한 다음 소스/드레인전극을 연결하는 금속배선(도시 안함)을 형성한 다음 보호막으로 패시베이션층(도시안함)을 형성한다.Then, an interlayer insulating layer (not shown) is formed, a metal wiring (not shown) connecting source / drain electrodes is formed, and then a passivation layer (not shown) is formed of a protective film.
그러나, 상술한 바와 같이 종래 기술에서는 소자가 고집적화 됨에 따라 엘디디방식을 사용하지만 쇼트채널효과로 인하여 한계에 이르러 할로 엘디디 방식을 도입하였지만, 소자형성에 있어서 워드라인으로 사용되는 게이트라인의 단차가 커져서 할로 이온주입시 게이트 라인에 의한 쉐도우 효과로 인하여 원하는 부위인 게이트측벽 아래에 할로 이온주입이 되지 아니하고 엘디디 형성부위와 동일한 장소에 할로 이온주입이 되어 쇼트채널효과를 억제하기 곤란하고, 또한 엘디디 이온주입 후 좁은 공간에서 np 혹은 pn 졍션을 형성하게 되어 졍션누설전류가 증가하는 문제점이 있다.However, as described above, in the prior art, the LED is used as the device is highly integrated. However, due to the short channel effect, the LED is introduced. However, the step of the gate line used as the word line in forming the device is increased. It is difficult to suppress the short channel effect due to the halo ion implantation at the same place as the LED formation site, instead of the halo ion implantation under the gate side wall, which is a desired part, due to the shadow effect caused by the gate line during the halo ion implantation. Since the np or pn caption is formed in the narrow space after the DI ion implantation, there is a problem that the caption leakage current increases.
따라서, 본 발명의 목적은 고집적소자의 소스/드레인에 적당하도록 종래의 에이치엘디디 방식의 소스/드레인 형성시 문제점으로 나타나는 게이트 라인의 단차가 높아져 소스/드레인 형성용 불순물 이온과 반대 타입의 이온주입을 실시하는 할로이온주입 방식에 있어서 쉐도우효과로 인한 바람직하지 못한 결과를 초래하여 쇼트채널효과(short channel effect)를 효과적으로 억제하지 못하는 문제를 게이트라인 형성 후 종래의 할로이온주입을 실시하고 다시 박막을 형성하여 게이트측벽의 두께를 연장시킨 후 엘디디를 형성하므로서 쇼트채널효과를 억제함은 물론 엘디디 이온주입이나 소스/드레인 이온주입시 채널링효과(channeling effect)를 방지하도록한 더블셀프 에이치엘디디(double self HLDD) 트랜지스터 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to increase the level of the gate line, which is a problem in the formation of a source of the conventional HDL-type method, so as to be suitable for the source / drain of the highly integrated device, so that the ion implantation of the opposite type to the impurity ion for the source / drain formation In the halo ion implantation method, which causes undesired effects due to the shadow effect, the short channel effect is not effectively suppressed. Double-self HMD to prevent short channel effects and to prevent channeling effects during the injection of ELD ions or source / drain ions. It provides a method of forming a double self HLDD) transistor.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 활성영역과 필드영역을 격리한 제 1 도전형 반도체기판상의 소정부위에 게이트절연막/게이트/캡절연층으로 이루어진 게이트 패턴을 형성하는 단계와, 게이트 하단 모서리 부위의 기판에 제 1 도전형 불순물 제 1 이온층을 형성하는 단계와, 노출된 기판 표면 및 게이트 패턴의 표면 및 측면에 제 1 절연막을 형성하는 단계와, 기판의 전면에 저농도로 제 2 도전형 불순물 이온주입하는 단계와, 게이트 패턴 측면에 형성된 절연막 표면에 제 2 절연막으로 이루어진 게이트측벽을 형성하는 단계와, 기판의 전면에 고농도로 제 2 도전형 불순물 이온주입하는 단계와, 불순물 이온을 확산시키는 단계를 포함하여 이루어진다.A semiconductor device manufacturing method according to the present invention for achieving the above object is formed by forming a gate pattern consisting of a gate insulating film / gate / cap insulating layer on a predetermined portion on a first conductive type semiconductor substrate isolating the active region and the field region Forming a first conductivity type impurity first ion layer on the substrate at the lower edge portion of the gate; forming a first insulating film on the exposed substrate surface and on the surface and side surfaces of the gate pattern; Implanting a second conductivity type impurity ion, forming a gate side wall made of a second insulating film on the surface of the insulating film formed on the side of the gate pattern, implanting a second conductivity type impurity ion on the entire surface of the substrate, and Diffusing ions.
도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 에이치엘디디(Halo Lightly Doped Drain) 트랜지스터 제조공정 단면도1A to 1C are cross-sectional views of a halo lightly doped drain transistor manufacturing process of a semiconductor device according to the related art.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 에이치엘디디(Halo Lightly Doped Drain) 트랜지스터 제조공정 단면도2A to 2C are cross-sectional views of a halo lightly doped drain transistor manufacturing process of a semiconductor device according to the present invention.
본 발명은 더블 셀프 에이치엘디디 트랜지스터 형성방법에 관한 것으로서 MISFET 소자형성을 실시예로 한다.The present invention relates to a method of forming a double self-HDD transistor, and the MISFET device formation is an embodiment.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 에이치엘디디(Halo Lightly Doped Drain) 트랜지스터 제조공정 단면도이다.2A to 2C are cross-sectional views of a halo lightly doped drain transistor manufacturing process of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판(21) 표면의 소정 부분에 STI(Shallow Trench Isolation) 등의 통상적인 선택산화방법에 의해 필드산화막(22)을 형성하여 소자의 활성영역 및 필드영역을 한정한다.Referring to FIG. 2A, a field oxide film 22 is formed on a predetermined portion of the surface of the semiconductor substrate 21 by a conventional selective oxidation method such as shallow trench isolation (STI) to define an active region and a field region of the device.
그 다음, 반도체기판(21)의 표면을 열산화하여 게이트산화막(23)을 형성한다.Thereafter, the surface of the semiconductor substrate 21 is thermally oxidized to form a gate oxide film 23.
게이트산화막(23)의 상부에 불순물이 도핑된 다결정실리콘층(24)을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착한 다음 다시 그 위에 게이트금속층(25)과 캡핑용 질화막(26)을 차례로 증착하여 형성한다. 이때 질화막 대신 에이치엘디(high temperature low pressure dielectric)를 이용할 수 있다.A polysilicon layer 24 doped with impurities on the gate oxide layer 23 is deposited by chemical vapor deposition (CVD), and then the gate metal layer 25 and the capping nitride layer are formed thereon. (26) is formed by depositing one after another. In this case, a high temperature low pressure dielectric (HL) may be used instead of the nitride film.
그리고, 포토리쏘그래피(photolithography) 방법으로 패터닝하여 즉 질화막(26)과 게이트금속층(25) 그리고 다결정실리콘층(24) 및 게이트산화막(23)의 일부를 제거하여 게이트(25, 24)를 한정한다.The gates 25 and 24 are defined by patterning by photolithography, that is, removing part of the nitride film 26, the gate metal layer 25, and the polysilicon layer 24 and the gate oxide film 23. .
그 다음 할로이온주입(27)을 노출된 기판(21)의 전면에 실시하여 게이트 하단 모서리 부위의 기판의 불순물 농도를 높인다. 이때 주입되는 이온은 소스/드레인 형성용 이온과 반대 타입의 이온으로서 p 채널인 경우에는 P+ 혹은 As+ 이온을 사용하고, n 채널인 경우에는 B+ 또는 BF2+를 5E14 ions/㎠ 이하의 농도로 기판에 경사지게 이온주입을 실시하며, 이러한 이온들은 기판 자체의 불순물 농도를 높여서 펀치-스루 현상을 방지하는 역할을 한다.The haloion implant 27 is then applied to the entire surface of the exposed substrate 21 to increase the impurity concentration of the substrate at the bottom edge of the gate. In this case, the implanted ions are opposite to the source / drain formation ions, and P + or As + ions are used in the p-channel and B + or BF2 + is inclined to the substrate at a concentration of 5E14 ions / cm 2 or less in the n-channel. Ion implantation is performed, and these ions increase the impurity concentration of the substrate itself to prevent punch-through.
도 2b에 있어서, 형성된 구조물들의 노출된 표면 및 기판(21)의 표면에 산화막, 질화막 또는 SiON막을 증착하여 세미 엘디디층(31)을 형성한다. 이때 세미 엘디디층(31)은 게이트 측면에 형성된 부위는 게이트의 측벽 역할을 하며 기판(21) 부위에 형성된 부위는 이온주입시 채널링 효과를 억제하는 층으로 작용한다.In FIG. 2B, an oxide film, a nitride film, or a SiON film is deposited on the exposed surfaces of the formed structures and the surface of the substrate 21 to form a semi LED layer 31. In this case, the semi-LEDi layer 31 has a portion formed on the side of the gate serving as a sidewall of the gate and a portion formed on the portion of the substrate 21 serves as a layer for suppressing channeling effect during ion implantation.
게이트 측면 부위에 형성된 세미 엘디디층(31)과 잔류한 질화막(26) 상부에 형성된 세미 엘디디층(31)을 마스크로 이용하여 반도체기판(21) 표면부위에 n 채널인 경우에는 P+ 혹은 As+ 이온을 사용하고, p 채널인 경우에는 B+ 또는 BF2+를 1E15 ions/㎠ 이하의 농도로 기판에 엘디디 이온주입(28)을 실시한다.P + or As + in the case of the n-channel on the surface of the semiconductor substrate 21 using the semi LED layer 31 formed on the side surface of the gate and the semi LED layer 31 formed on the remaining nitride film 26 as a mask. In the case of the p-channel, ions are used, and the eddy ion implantation 28 is performed on the substrate at a concentration of 1 + 15 ions / cm 2 or less for B + or BF2 +.
도 2c에 있어서, 이와 같은 기판(21)의 전면에 질화막 또는 산화막을 증착한 다음 이를 에치백하여 게이트측벽(29)을 형성한다.In FIG. 2C, a nitride film or an oxide film is deposited on the entire surface of the substrate 21 and then etched back to form the gate sidewall 29.
그리고 게이트 패턴의 상부 및 측면에 형성된 세미 엘디디층(31) 및 게이트측벽(29)을 마스크로 이용한 이온주입을 실시하여 소스/드레인을 형성한다. 이때 n 채널인 경우에는 P+ 혹은 As+ 이온을 사용하고, p 채널인 경우에는 B+ 또는 BF2+를 사용하여 1E17 ions/㎠ 이하의 농도로 기판에 소스/드레인 형성용 이온주입(30)을 실시한다.A source / drain is formed by performing ion implantation using the semi LED layer 31 and the gate side wall 29 formed as a mask on the top and side surfaces of the gate pattern. In this case, P + or As + ions are used in the case of n-channel, and source / drain formation ion implantation 30 is performed on the substrate at a concentration of 1E17 ions / cm 2 or less using B + or BF2 + in the case of p-channel.
그리고 층간절연층(도시안함)을 형성한 다음 소스/드레인전극을 연결하는 금속배선(도시 안함)을 형성한 다음 보호막으로 패시베이션층(도시안함)을 형성한다.Then, an interlayer insulating layer (not shown) is formed, a metal wiring (not shown) connecting source / drain electrodes is formed, and then a passivation layer (not shown) is formed of a protective film.
따라서, 본 발명은 게이트라인을 형성한 다음 마스킹작업을 통해 할로이온주입을 한 다음 박막을 형성하여 게이트라인 측면에 세미 측벽을 형성하고 기판의 노출부위에는 채널링효과를 억제하는 이온주입 방해층을 형성한 다음이온주입을 실시하여 이미 형성된 할로 이온주입 부위의 바깥 지역에 이온주입층을 형성하므로서 쇼트채널효과 억제효과와 졍션누설전류를 감소시키는 장점이 있고, 또한 엘디디 형성 이온주입이나 고농도의 소스/드레인 형성을 위한 이온주입시 채널링 효과를 억제하는 장점이 있다.Accordingly, the present invention forms a gate line and then implants a halo ion through a masking operation and then forms a thin film to form semi-sidewalls on the side of the gate line and to form an ion implantation barrier layer on the exposed portion of the substrate to suppress channeling effects. Then, ion implantation is performed to form an ion implantation layer outside the previously formed halo ion implantation site, thereby reducing the short channel effect and reducing the cushion leakage current, and in addition to the LED formation ion implantation or high concentration source / There is an advantage of suppressing the channeling effect during ion implantation for forming the drain.
Claims (5)
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