KR20010045183A - Method for manufacturing dual gate electrodes of CMOS device - Google Patents
Method for manufacturing dual gate electrodes of CMOS device Download PDFInfo
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- KR20010045183A KR20010045183A KR1019990048378A KR19990048378A KR20010045183A KR 20010045183 A KR20010045183 A KR 20010045183A KR 1019990048378 A KR1019990048378 A KR 1019990048378A KR 19990048378 A KR19990048378 A KR 19990048378A KR 20010045183 A KR20010045183 A KR 20010045183A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히 n+/p+ 듀얼 게이트의 불순물 확산을 방지하여 트랜지스터의 전기적 특성을 향상시킬 수 있는 반도체장치의 CMOS 듀얼 게이트전극 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a CMOS dual gate electrode of a semiconductor device capable of improving the electrical characteristics of a transistor by preventing impurity diffusion of an n + / p + dual gate.
일반적으로, CMOS 트랜지스터는 NMOS 및 PMOS의 게이트전극으로서 폴리실리콘막내에 도전성을 띄도록 n형 불순물을 도프트해서 사용하고 있다. 이로 인해, NMOS 트랜지스터는 기판 표면 근방에 채널이 형성되는 표면 채널 모드(surface channel mode)로 동작하게 되고, PMOS 트랜지스터의 경우에는 기판 표면보다 깊은 부위에서 채널이 형성되는 매몰 채널 모드(buried channel mode)로 동작하게 된다.In general, a CMOS transistor is doped with n-type impurities so as to exhibit conductivity in a polysilicon film as gate electrodes of NMOS and PMOS. As a result, the NMOS transistor operates in a surface channel mode in which a channel is formed near the substrate surface, and in the case of a PMOS transistor, a buried channel mode in which a channel is formed deeper than the substrate surface. Will work.
하지만, 반도체장치의 집적도가 증가함에 따라 MOS 트랜지스터의 게이트 길이 또한 감소되고 있다. 최근에는, 1Giga급 DRAM(Dynamic Random Access Memory) 소자의 경우 약 0.2??m 이하의 게이트 길이를 갖도록 소자 설계가 이루어지고 있다. 축소된 게이트 길이에 따라 유효 채널길이 또한 짧아지게 되어, 채널영역이 게이트 전압뿐만 아니라 소오스/드레인영역의 공핍층 전하, 전계, 및 전위분포의 영향을 강하게 받는 소위, 쇼트-채널 효과(short-channel effect)가 발생하게 된다. 이러한 쇼트-채널 효과는 역치전압(threshold voltage)의 저하, 소오스/드레인간 내압의 저하, 및 서브-스레쉬홀드(sub-threshold) 특성의 저하를 수반하게 된다.However, as the degree of integration of semiconductor devices increases, the gate length of MOS transistors also decreases. Recently, a device design has been made to have a gate length of about 0.2 μm or less for a 1 Giga-class dynamic random access memory (DRAM) device. The reduced channel length also shortens the effective channel length, so that the channel region is strongly influenced by the depletion layer charge, electric field, and potential distribution of the source / drain regions as well as the gate voltage. effect) will occur. This short-channel effect is accompanied by a drop in threshold voltage, a breakdown in source / drain breakdown voltage, and a drop in sub-threshold characteristics.
그러므로, n형 불순물이 도프트된 게이트를 갖는 PMOS 트랜지스터의 경우에는 이러한 쇼트-채널 효과로 인해 그 특성이 저하되기 때문에 이를 개선하기 위해서 NMOS 트랜지스터에 비해 채널 길이가 길어야 하고, 또한 문턱 전압의 크기도 높아야만 하였다.Therefore, in the case of a PMOS transistor having a gate doped with an n-type impurity, the characteristics of the PMOS transistor are degraded due to the short-channel effect. Therefore, the channel length must be longer than that of the NMOS transistor, and the threshold voltage is also increased. Had to be high.
또한, 최근 반도체소자의 축소 및 저전원 동작 사양에 맞추어 매몰 채널을 갖는 PMOS 트랜지스터 대신에 표면 채널형 PMOS 트랜지스터로 구조 변경이 요구되고 있다.In addition, in recent years, a structure change is required to a surface channel type PMOS transistor instead of a PMOS transistor having a buried channel in accordance with the shrinkage of semiconductor devices and low power supply operation specifications.
표면 채널형 PMOS 트랜지스터 제조를 위해서는, 폴리실리콘내에 도전형 불순물로서 p형 불순물을 도프하게 된다. 즉, 표면 채널 NMOS 및 PMOS 트랜지스터의 게이트전극은 폴리실리콘막내에 각각 n형 불순물과 p형 불순물이 도프트된 폴리실리콘을 포함하게 된다.For the production of surface channel type PMOS transistors, p-type impurities are doped as conductive type impurities in polysilicon. That is, the gate electrodes of the surface channel NMOS and PMOS transistors each include polysilicon doped with n-type impurities and p-type impurities in the polysilicon film.
그러나, 이러한 표면 채널형 PMOS 트랜지스터의 제조 공정시 게이트전극의 저저항을 위해 도프트 폴리실리콘 상부에 텅스텐 실리사이드를 적층해서 게이트전극을 형성할 경우, 후속 열공정으로 인해 폴리실리콘막내의 도펀트가 상부 텅스텐 실리사이드막으로 확산이 발생하게 되어 폴리실리콘막내의 p형 불순물(예컨대, 보론) 농도가 불균일하게 된다. 이에 따라, 표면 채널형 PMOS 트랜지스터의 문턱 전압이 감소하게 되고 온/오프 특성이 저하되어 듀얼 게이트를 포함한 트랜지스터의 동작 마진 및 그 전기적 특성이 저하되는 문제점이 있었다.However, when the gate electrode is formed by stacking tungsten silicide on top of the doped polysilicon for low resistance of the gate electrode in the manufacturing process of the surface channel type PMOS transistor, the dopant in the polysilicon film is formed by the upper tungsten due to the subsequent thermal process. Diffusion occurs in the silicide film, resulting in non-uniform concentration of p-type impurities (eg, boron) in the polysilicon film. As a result, the threshold voltage of the surface channel PMOS transistor is reduced and the on / off characteristic is deteriorated, thereby degrading the operating margin and electrical characteristics of the transistor including the dual gate.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여, CMOS 트랜지스터의 n+/p+ 듀얼 게이트 구조에서 상기 도프트 폴리실리콘막과 금속 실리사이드막 사이에 확산 방지막을 추가 함으로써 도프트 폴리실리콘막의 도펀트 확산을 방지하고, RTP(rapid thermal processing) 공정의 적용을 통해 워드라인의 Rs를 감소시켜 반도체소자의 전기적 특성을 향상시킬 수 있는 반도체장치의 CMOS 듀얼 게이트전극 제조방법을 제공하는데 있다.An object of the present invention is to solve the above problems of the prior art, by adding a diffusion barrier between the doped polysilicon film and the metal silicide film in the n + / p + dual gate structure of the CMOS transistor dopant of the doped polysilicon film The present invention provides a method for manufacturing a CMOS dual gate electrode of a semiconductor device that prevents diffusion and improves electrical characteristics of a semiconductor device by reducing Rs of a word line by applying a rapid thermal processing (RTP) process.
도 1 내지 도 8은 본 발명에 따른 듀얼 게이트전극을 갖는 CMOS 트랜지스터의 제조 공정을 나타낸 단면도들이다.1 to 8 are cross-sectional views illustrating a manufacturing process of a CMOS transistor having a dual gate electrode according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10: 실리콘 기판 11: p-웰10: silicon substrate 11: p-well
12: n-웰 14: 소자분리막12: n-well 14: device isolation film
16: 게이트절연막 18: 비정질 실리콘막16: gate insulating film 18: amorphous silicon film
18a: n+ 도프트 실리콘막 18b: p+ 도프트 실리콘막18a: n + doped silicon film 18b: p + doped silicon film
18a',18b': 도프트 폴리실리콘막 20,22: 포토레지스트 패턴18a ', 18b': doped polysilicon film 20,22: photoresist pattern
24: 확산 방지막 26: 텅스텐 실리사이드막24: diffusion barrier film 26: tungsten silicide film
G: 게이트전극 28: 스페이서G: gate electrode 28: spacer
30a,30b: 소오스/드레인 영역30a, 30b: source / drain regions
상기 목적을 달성하기 위하여 본 발명은 반도체 CMOS 트랜지스터의 듀얼 게이트전극의 제조 방법에 있어서, 반도체기판에 소자분리막을 형성하는 단계와, 소자분리막이 형성된 기판내에 서로 인접한 p-웰 및 n-웰을 형성하는 단계와, 기판 전면에 게이트절연막을 증착하는 단계와, 게이트절연막 상부에 비정질 실리콘을 증착하는 단계와, p-웰 부위의 비정질 실리콘막에만 선택적으로 n+ 불순물을 주입하고, n-웰 부위의 비정질 실리콘막에만 p+ 불순물을 주입하는 단계와, 결과물에 H2O2와 H2SO4를 사용하여 세정공정을 실시하여 비정질 실리콘막상부에 불순물 확산을 방지하는 확산 방지막을 형성하는 단계와, 확산 방지막 상부에 금속 실리사이드막을 적층하는 단계와, 금속 실리사이드막에 급속 열처리 공정을 실시하는 단계와, 적층된 금속 실리사이드막, 확산 방지막, 및 도프트 폴리실리콘막을 패터닝해서 p-웰 및 n-웰의 기판 상부에 각각 듀얼 게이트전극을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of manufacturing a dual gate electrode of a semiconductor CMOS transistor, comprising: forming an isolation layer on a semiconductor substrate, and forming p-wells and n-wells adjacent to each other in the substrate on which the isolation layer is formed; And depositing a gate insulating film on the entire surface of the substrate, depositing amorphous silicon on the gate insulating film, selectively implanting n + impurities only into the amorphous silicon film in the p-well region, and amorphous in the n-well region. Implanting p + impurities only into the silicon film, performing a cleaning process using H 2 O 2 and H 2 SO 4 on the resultant to form a diffusion barrier layer on the amorphous silicon layer to prevent diffusion of impurities; Laminating a metal silicide film on top, performing a rapid heat treatment process on the metal silicide film, and laminating the metal silicide film Film, a diffusion film, and a doped bit by patterning a polysilicon film and a step of respectively forming the dual-gate electrode over the substrate in the p- well and the n- well.
본 발명의 제조 방법에 있어서, 상기 확산 방지막 형성시 H2O2와 H2SO4의 비를 4:1로 하고, 그 막 두께를 15∼25Å정도로 한다.In the production method of the present invention, the ratio of H 2 O 2 to H 2 SO 4 is 4: 1 at the time of forming the diffusion barrier, and the film thickness is about 15 to 25 kPa.
본 발명의 제조 방법에 있어서, 상기 급속 열처리 공정은 900∼1100℃의 온도에서 10∼30초동안 N2분위기에서 진행한다. 바람직하게는, 급속 열처리 공정은 950℃의 반응 온도, 20초 동안 N2를 3ℓ분위기로 한다.In the production method of the present invention, the rapid heat treatment process is performed in an N 2 atmosphere for 10 to 30 seconds at a temperature of 900 ~ 1100 ℃. Preferably, the rapid heat treatment process is a reaction temperature of 950 ℃, N 2 in 3L atmosphere for 20 seconds.
본 발명의 제조 방법에 있어서, 상기 금속 실리사이드막은 텅스텐 실리사이드이다.In the production method of the present invention, the metal silicide film is tungsten silicide.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 1 내지 도 8은 본 발명에 따른 듀얼 게이트전극을 갖는 CMOS 트랜지스터의 제조 공정을 나타낸 단면도들로서, 이를 참조하면 본 발명에 따른 금속 폴리사이드 구조의 듀얼 게이트전극 제조 방법은 다음과 같다.1 to 8 are cross-sectional views illustrating a manufacturing process of a CMOS transistor having a dual gate electrode according to the present invention. Referring to this, a method of manufacturing a dual gate electrode having a metal polyside structure according to the present invention is as follows.
우선, 도 1에 도시된 바와 같이, 반도체 기판으로서 p형 실리콘기판(10)에 반도체 소자의 활성 영역과 비활성 영역을 정의하는 소자분리막(14)을 형성한다. 그리고, 소자분리막(14)이 형성된 기판내에 서로 인접한 p-웰(11) 및 n-웰(12)을 형성한다. 상기 기판(10) 전면에 30∼50Å 정도의 게이트절연막(16)을 형성하되, 이 절연막(16)은 약 800℃의 습식 산화 공정 및 N2O 어닐링으로 얻을 수 있다. 여기서, N2O 어닐링 공정은 900℃의 온도에서, 30분간 진행한다.First, as shown in FIG. 1, an isolation layer 14 for defining an active region and an inactive region of a semiconductor device is formed on a p-type silicon substrate 10 as a semiconductor substrate. Then, p-wells 11 and n-wells 12 that are adjacent to each other are formed in the substrate on which the device isolation film 14 is formed. A gate insulating film 16 of about 30 to 50 kV is formed on the entire surface of the substrate 10. The insulating film 16 can be obtained by a wet oxidation process of about 800 ° C. and N 2 O annealing. Here, the N 2 O annealing step proceeds at a temperature of 900 ° C. for 30 minutes.
그 다음, 도 2에 도시된 바와 같이, 상기 게이트절연막(16) 상부에 비정질 실리콘(18)을 증착한다. 이때, 비정질 실리콘막(18) 증착 공정은 Si2H6을 이용해서 480∼550℃의 온도에서 0.1∼1.0 torr의 압력하에서 700∼1000Å 두께로 증착한다. 여기서, 바람직한 비정질 실리콘막(18)의 두께는 800Å이다.Next, as shown in FIG. 2, amorphous silicon 18 is deposited on the gate insulating layer 16. At this time, the deposition process of the amorphous silicon film 18 is deposited using a Si 2 H 6 to a thickness of 700 to 1000 Pa at a temperature of 480 to 550 ° C. under a pressure of 0.1 to 1.0 torr. Here, the thickness of the preferred amorphous silicon film 18 is 800 kPa.
그리고, 도 3에 도시된 바와 같이, 상기 기판 상부에 p-웰(11) 부위의 비정질 실리콘막만을 개방하는 포토레지스트 패턴(20)을 형성하고, n+ 불순물로서 P31을 이온 주입한다(18a참조). 이때, P31의 이온 주입 공정은 그 에너지세기를 12∼20KeV로 하고, 도우즈량을 1.0∼6.0E15/㎠으로 한다.As shown in FIG. 3, a photoresist pattern 20 is formed on the substrate to open only the amorphous silicon film of the p-well 11, and P31 is ion implanted as an n + impurity (see 18a). . At this time, the ion implantation step of P31 sets the energy intensity to 12 to 20 KeV and the dose amount to 1.0 to 6.0E15 / cm 2.
그리고나서, 상기 포토레지스트 패턴(20)을 제거한다. 도 4에 도시된 바와 같이, 기판에 n-웰(12) 부위의 비정질 실리콘막만을 개방하는 포토레지스트 패턴(22)을 형성하고, p+ 불순물로서 B11을 이온 주입한다(18b 참조). 이때, B11의 이온 주입공정은 그 에너지세기를 4∼6KeV, 도우즈량을 1.0∼6.0E15/㎠으로 한다.Then, the photoresist pattern 20 is removed. As shown in FIG. 4, a photoresist pattern 22 is formed on the substrate to open only an amorphous silicon film of the n-well 12 region, and B11 is ion implanted as a p + impurity (see 18b). At this time, in the ion implantation step of B11, the energy intensity is 4 to 6 KeV and the dose is 1.0 to 6.0E15 / cm 2.
이어서, 도 5에 도시된 바와 같이, 상기 결과물에 금속 폴리사이드, 예컨대 텅스텐 실리사이드를 형성하기 전에 실시하는 세정 공정시 H2O2와 H2SO4를 사용하여 세정공정을 실시한다. 이로인해, 상기 p-웰(11) 및 n-웰(12) 상부에 각각 n+/p+ 도펀트 주입된 비정질 실리콘막(18a,18b) 상부 전면에 불순물 확산을 방지하는 확산 방지막(24)을 형성한다. 여기서, 확산 방지막(24) 형성시, H2O2와 H2SO4의 비를 4:1로 하고, 그 막 두께를 15∼25Å정도로 한다.Subsequently, as shown in FIG. 5, the cleaning process is performed using H 2 O 2 and H 2 SO 4 during the cleaning process performed before the metal polyside such as tungsten silicide is formed in the resultant. As a result, a diffusion barrier layer 24 is formed on the upper surfaces of the amorphous silicon layers 18a and 18b implanted with n + / p + dopants on the p-wells 11 and n-wells 12, respectively. . Here, at the time of formation of the diffusion barrier film 24, the ratio of H 2 O 2 to H 2 SO 4 is 4: 1, and the film thickness thereof is about 15 to 25 kPa.
이어서, 도 6에 도시된 바와 같이, 상기 확산 방지막(24) 상부에 금속막(26)으로서 텅스텐 실리사이드를 800∼1500Å정도 증착한다. 이때, 바람직한 텅스텐 실리사이드막(26)의 두께는 1100Å이다.Next, as shown in FIG. 6, tungsten silicide is deposited on the diffusion barrier 24 as a metal film 26 at about 800-1500 kV. At this time, the thickness of the preferable tungsten silicide film 26 is 1100 kPa.
그 다음, 급속 열처리 공정(rapid thermal process)을 실시하여 텅스텐 실리사이드막(26)을 결정화하고, 비정질 실리콘막(18a,18b)을 도프트 폴리실리콘화(18a',18b')한다. 이때, 급속 열처리 공정은 900∼1100℃의 온도에서 10∼30초동안 N2분위기에서 진행하되, 바람직한 열처리 공정 조건은 950℃의 온도와 20초의 시간내에서 N2를 3ℓ로 한다. 그러면, 급속 열처리 공정에 의해 도프트 폴리실리콘막(18a',18b')내의 n+/p+ 불순물의 활성화를 증가시킨다. 또한, 텅스텐 실리사이드막과 도프트 폴리실리콘막 사이의 확산 방지막이 유전체 역할을 하여 도프트 폴리실리콘의 비저항이 나빠질 수 있으나, 상기 열처리 공정에 의해 게이트전극의 비저항(Rs)을 약 4∼5Ω/㎠정도 낮출 수 있다.Then, a rapid thermal process is performed to crystallize the tungsten silicide film 26 and doped polysilicon 18a 'and 18b' on the amorphous silicon films 18a and 18b. At this time, the rapid heat treatment process is carried out in N 2 atmosphere for 10 to 30 seconds at a temperature of 900 ~ 1100 ℃, the preferred heat treatment process conditions is 2 2 N 2 in a temperature of 950 ℃ and 20 seconds. Then, activation of n + / p + impurities in the doped polysilicon films 18a 'and 18b' is increased by a rapid heat treatment process. In addition, although the diffusion prevention film between the tungsten silicide film and the doped polysilicon film serves as a dielectric material, the specific resistance of the doped polysilicon may deteriorate. Can be lowered.
이어서, 도 7에 도시된 바와 같이, 게이트 마스크를 이용한 사진 및 식각 공정을 실시하여 순차 적층된 텅스텐 실리사이드막(26'), 확산 방지막(24'), 및 도프트 폴리실리콘막(18a',18b')을 패터닝하여 p-웰(11) 및 n-웰(12)의 기판 상부에 각각 듀얼 게이트전극(G)을 형성한다. 이때, 게이트절연막(16) 또한 상기 듀얼 게이트전극(G)에 정렬되게 식각한다.Subsequently, as shown in FIG. 7, the tungsten silicide layer 26 ', the diffusion barrier layer 24', and the doped polysilicon layers 18a 'and 18b are sequentially stacked by performing a photolithography and an etching process using a gate mask. ') Is patterned to form dual gate electrodes G on the substrates of the p-well 11 and the n-well 12, respectively. In this case, the gate insulating layer 16 is also etched to be aligned with the dual gate electrode G.
그 다음, 도 8에 도시된 바와 같이, 기판 전면에 절연물질로서 실리콘질화막을 증착하고, 이를 건식 식각으로 식각해서 상기 듀얼 게이트전극(G) 측벽에 스페이서(28)를 형성한다.Next, as shown in FIG. 8, a silicon nitride film is deposited on the entire surface of the substrate as an insulating material and etched by dry etching to form a spacer 28 on the sidewall of the dual gate electrode G. Referring to FIG.
그리고, 통상의 소오스/드레인 이온 주입을 실시하여 상기 p-웰(11) 및 n-웰(12)의 게이트전극(G)과 소자분리막(14) 사이의 기판 내에 n+/p+ 불순물이 주입된 소오스/드레인 영역(30a,30b)을 형성해서 본 발명에 따른 텅스텐 폴리사이드 구조의 CMOS 듀얼 게이트전극을 갖는 NMOS 및 PMOS 트랜지스터를 완성한다.In addition, a source in which n + / p + impurities are implanted into the substrate between the gate electrode G and the device isolation layer 14 of the p-well 11 and n-well 12 by performing normal source / drain ion implantation The / drain regions 30a and 30b are formed to complete the NMOS and PMOS transistors having the CMOS dual gate electrode of the tungsten polyside structure according to the present invention.
상기와 같은 제조 공정에 따른 CMOS 트랜지스터의 듀얼 게이트전극을 갖는 반도체 소자는, 게이트전극 내의 하부 폴리실리콘과 상부 텅스텐 실리사이드 사이에 NH4OH+ H2O2의 세정 공정으로 형성된 확산 방지막을 구비함으로써, 표면 채널 트랜지스터를 위한 n+/p+ 폴리실리콘막내의 도펀트인 인(P)과 보론(B)이 상부의 텅스텐 실리사이드막으로 확산되는 것을 막을 수 있다. 이에 따라, NMOS와 PMOS 트랜지스터의 게이트전극내 도펀트의 내부 확산을 차단하여 해당 트랜지스터의 문턱 전압 증가를 최소화할 수 있으며 또한, 폴리실리콘막의 도핑 농도를 높일 수 있어 게이트 공핍을 근본적으로 제거할 수 있다.A semiconductor device having a dual gate electrode of a CMOS transistor according to the above manufacturing process is provided with a diffusion barrier layer formed by a cleaning process of NH 4 OH + H 2 O 2 between a lower polysilicon and an upper tungsten silicide in the gate electrode, thereby providing a surface. Phosphorus (P) and boron (B), which are dopants in the n + / p + polysilicon film for the channel transistor, can be prevented from diffusing into the upper tungsten silicide film. Accordingly, the internal diffusion of the dopant in the gate electrode of the NMOS and PMOS transistors can be blocked to minimize the increase of the threshold voltage of the corresponding transistor, and the doping concentration of the polysilicon film can be increased to fundamentally eliminate the gate depletion.
또한, 본 발명의 게이트전극 내 확산 방지막은 상부 텅스텐 실리사이드로부터 확산되어 내려오는 불소계 이온이 게이트절연막/기판으로 확산되는 경로를 미연에 차단하여 폴리실리콘막내의 도펀트 농도, 특히 보론 농도(불소는 보론 확산을 촉진시킴)를 일정하게 유지할 수 있어 게이트절연막의 질 저하를 막을 수 있으며 TDDB(Time Dependent Dielectric Breakdown) 특성을 향상시킬 수 있다.In addition, the diffusion barrier in the gate electrode of the present invention blocks the path in which the fluorine-based ions diffused from the upper tungsten silicide diffuses to the gate insulating film / substrate in advance, thereby increasing the dopant concentration in the polysilicon film, in particular, the boron concentration (fluorine diffusion of boron). It is possible to maintain a constant to prevent the deterioration of the gate insulating film quality and to improve the time dependent dielectric breakdown (TDDB) characteristics.
상술한 바와 같이, 본 발명은 CMOS 트랜지스터의 표면 채널형 n+/p+ 듀얼 게이트 구조에서 도프트 폴리실리콘막과 금속 실리사이드막 사이에 절연성의 확산 방지막을 추가함으로써 도프트 폴리실리콘막의 도펀트 확산을 방지하여 트랜지스터의 문턱전압 감소, 게이트 공핍 억제 등의 소자 특성을 향상시킬 수 있다.As described above, the present invention prevents the dopant diffusion of the doped polysilicon film by adding an insulating diffusion preventing film between the doped polysilicon film and the metal silicide film in the surface channel type n + / p + dual gate structure of the CMOS transistor. Device characteristics such as reducing the threshold voltage and suppressing gate depletion can be improved.
그리고, 본 발명은 반도체소자의 PMOS 트랜지스터의 크기를 NMOS 트랜지스터와 동일하게 할 수 있어 전체적인 넷 다이 수를 증대시킬 수 있으며, NMOS와 PMOS 트랜지스터의 문턱 전압을 동일하게 할 수 있어 낮은 문턱 전압을 유지하면서 누설 특성을 확보할 수 있어 저전압용 반도체 소자의 제작에 이용할 수 있다.In the present invention, the size of the PMOS transistor of the semiconductor device can be the same as that of the NMOS transistor, thereby increasing the total number of net dies, and the threshold voltages of the NMOS and PMOS transistors can be the same, while maintaining a low threshold voltage. Leakage characteristics can be secured and can be used for manufacturing low voltage semiconductor devices.
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| KR100691491B1 (en) * | 2005-08-31 | 2007-03-09 | 주식회사 하이닉스반도체 | Dual gate of semiconductor device and method for forming the same |
| US7402478B2 (en) | 2005-08-24 | 2008-07-22 | Samsung Electronics Co., Ltd. | Method of fabricating dual gate electrode of CMOS semiconductor device |
| US8329539B2 (en) | 2005-10-04 | 2012-12-11 | Samsung Electronics Co., Ltd. | Semiconductor device having recessed gate electrode and method of fabricating the same |
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| JPH07122649A (en) * | 1993-10-26 | 1995-05-12 | Matsushita Electric Ind Co Ltd | Fabrication of cmos transistor |
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| JPH07115196A (en) * | 1993-10-14 | 1995-05-02 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| JPH07122649A (en) * | 1993-10-26 | 1995-05-12 | Matsushita Electric Ind Co Ltd | Fabrication of cmos transistor |
| US5943592A (en) * | 1996-06-24 | 1999-08-24 | Sony Corporation | Method of making a MIS transistor |
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| US7402478B2 (en) | 2005-08-24 | 2008-07-22 | Samsung Electronics Co., Ltd. | Method of fabricating dual gate electrode of CMOS semiconductor device |
| KR100691491B1 (en) * | 2005-08-31 | 2007-03-09 | 주식회사 하이닉스반도체 | Dual gate of semiconductor device and method for forming the same |
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