KR940016619A - Gate electrode formation method of semiconductor device - Google Patents

Gate electrode formation method of semiconductor device Download PDF

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Publication number
KR940016619A
KR940016619A KR1019920024026A KR920024026A KR940016619A KR 940016619 A KR940016619 A KR 940016619A KR 1019920024026 A KR1019920024026 A KR 1019920024026A KR 920024026 A KR920024026 A KR 920024026A KR 940016619 A KR940016619 A KR 940016619A
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KR
South Korea
Prior art keywords
gate
forming
gate electrode
drain region
region
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Application number
KR1019920024026A
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Korean (ko)
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KR960006428B1 (en
Inventor
박해성
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019920024026A priority Critical patent/KR960006428B1/en
Publication of KR940016619A publication Critical patent/KR940016619A/en
Application granted granted Critical
Publication of KR960006428B1 publication Critical patent/KR960006428B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 제조공정중 게이트전극 형성방법에 관한 것으로 소오스영역 및 드레인영역을 먼저 형성한후 게이트 폴리실리콘을 형성하여 산화막 스페이서 공정을 감소시키며 소오스영역과 드레인영역의 측면확산의 마진을 확보하고 특히 소오스영역과 드레인영역의 게이트채널 쪽으로의 확산으로 인한 쇼트채널효과를 방지하여 소자의 전기적 특성을 향상시키는 반도체 소자의 게이트전극 형성방법이다.The present invention relates to a method of forming a gate electrode during a semiconductor device fabrication process, which first forms a source region and a drain region, and then forms a gate polysilicon to reduce the oxide spacer process and to secure a side diffusion of the source region and the drain region. In particular, the method of forming a gate electrode of a semiconductor device improves the electrical characteristics of the device by preventing the short channel effect caused by diffusion of the source region and the drain region toward the gate channel.

Description

반도체 소자의 게이트전극 형성방법Gate electrode formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래 기술방법에 의하여 형성된 게이트전극의 단면도, 제2A도 내지 제2D도는 본 발명의 제 1 실시예에 의하여 형성된 게이트전극의 단면도, 제3A도 내지 제3D도는 본 발명의 다른 실시예에 의하여 형성된 게이트전극의 단면도.1 is a cross-sectional view of a gate electrode formed by a prior art method, FIGS. 2A through 2D are cross-sectional views of a gate electrode formed by a first embodiment of the present invention, and FIGS. 3A through 3D are shown in another embodiment of the present invention. Sectional drawing of the gate electrode formed by this.

Claims (2)

반도체 소자의 게이트전극 형성방법에 있어서, 소오스 및 드레인영역의 게이트 채널영역으로의 확산에 의한 쇼트채널 효과를 방지하기 위하여, 실리콘기판 상부에 먼저 얇은 두께의 산화막을 증착하고 불순물을 주입하여 소오스영역과 드레인영역을 형성하는 단계와, 소오스영역과 드레인영역의 안정화를 위하여 열처리공정을 진행하고 산화막을 적층하여 마스크 패턴을 형성하는 단계와, 산화막의 예정된 부분을 건식식각하고 게이트채널용 불순물을 주입하여 게이트 채널영역을 형성한후 그 상부에 게이트 절연막과 게이트 폴리실리콘을 적층하고 게이트전극 마스크를 형성하는 단계와, 게이트 폴리실리콘과 게이트 절연막을 식각하고 감광막 마스크를 제거하여 게이트전극을 형성하는 단계로 이루어진 반도체 소자의 게이트전극 형성방법.In the method of forming a gate electrode of a semiconductor device, in order to prevent a short channel effect caused by diffusion of a source and a drain region into a gate channel region, a thin oxide film is first deposited on an upper surface of a silicon substrate, and impurities are implanted into the source region. Forming a drain region, performing a heat treatment process to stabilize the source region and the drain region, forming an oxide layer to form a mask pattern, dry etching a predetermined portion of the oxide layer, and injecting impurities for the gate channel to gate Forming a channel region, stacking a gate insulating film and a gate polysilicon thereon, forming a gate electrode mask, etching the gate polysilicon and the gate insulating film, and removing the photoresist mask to form a gate electrode; Method for forming a gate electrode of the device. 제 1 항에 있어서, 게이트 절연막과 게이트 폴리실리콘 식각시 마스크 없이 블랭킷 에치백 식각공정으로 진행하는 것을 특징으로 하는 반도체 소자의 게이트전극 형성방법.The method of claim 1, wherein the gate insulating layer and the gate polysilicon are etched without a mask and subjected to a blanket etch back etching process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920024026A 1992-12-12 1992-12-12 Method of manufacturing a gate for semiconductor device KR960006428B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920024026A KR960006428B1 (en) 1992-12-12 1992-12-12 Method of manufacturing a gate for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920024026A KR960006428B1 (en) 1992-12-12 1992-12-12 Method of manufacturing a gate for semiconductor device

Publications (2)

Publication Number Publication Date
KR940016619A true KR940016619A (en) 1994-07-23
KR960006428B1 KR960006428B1 (en) 1996-05-15

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KR1019920024026A KR960006428B1 (en) 1992-12-12 1992-12-12 Method of manufacturing a gate for semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403323B1 (en) * 1996-06-29 2004-05-10 주식회사 하이닉스반도체 Method for forming pattern of semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101253740B1 (en) * 2005-04-29 2013-04-11 매그나칩 반도체 유한회사 Method for manufacturing a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403323B1 (en) * 1996-06-29 2004-05-10 주식회사 하이닉스반도체 Method for forming pattern of semiconductor device

Also Published As

Publication number Publication date
KR960006428B1 (en) 1996-05-15

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