KR970054238A - Method for manufacturing mask ROM of semiconductor device - Google Patents

Method for manufacturing mask ROM of semiconductor device Download PDF

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KR970054238A
KR970054238A KR1019950062113A KR19950062113A KR970054238A KR 970054238 A KR970054238 A KR 970054238A KR 1019950062113 A KR1019950062113 A KR 1019950062113A KR 19950062113 A KR19950062113 A KR 19950062113A KR 970054238 A KR970054238 A KR 970054238A
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South Korea
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oxide
insulating layer
gate electrode
film
forming
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KR1019950062113A
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Korean (ko)
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KR100219047B1 (en
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준 황
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 소자의 마스크 롬 제조방법에 있어서, 실리콘 기판상에 게이트 산화막(2), 제1폴리실리콘막(3), 제1산화막(4)을 차례로 형성한 후 감광막 패턴(P/R)을 상기 제1산화막(4) 상에 형성하는 단계; 상기 감광막 패턴을 식각 마스크로 상기 제1산화막(4), 제1폴리실리콘막(3)을 식각하여 산화막 패턴(4′)과 제1게이트 전극(3′)을 형성한 후 제2산화막(5)을 전체구조 상부에 도포하는 단계; 상기 제2산화막(5)을 비등방성 식각하여 상기 산화막 패턴(4′) 및 제1게이트 전극(3′)의 측벽에 산화막 스페이서(5′)를 형성하는 단계; 상기 비등방성 식각에 의해 노출된 실리콘 기판(1) 상에 제2게이트 산화막(6)를 형성하는 단계; 전체구조 상부에 제2폴리실리콘막(7)을 전체구조 상부에 도포하는 단계; 상기 제1게이트 전극(3′)상에 위치한 산화막 패턴(4′)과 산화막 스페이서(5′)의 상부 일부가 노출되도록 상기 제2폴리실리콘막(7)을 에치백(etch back)하여 제2게이트 전극(7′)을 형성하는 단계; 상기 산화막 스페이서(5′)를 습식식각하여 제거하는 단계; 및 상기 습식식각 하여 제거된 상기 산화막 스페이서(5′) 하부에 위치한 실리콘 기판(1)에 불순물 이온을 주입하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 마스크 롬 제조방법.In the method of manufacturing a mask ROM of a semiconductor device, a photoresist pattern (P / R) is formed after sequentially forming a gate oxide film 2, a first polysilicon film 3, and a first oxide film 4 on a silicon substrate. Forming on the first oxide film (4); The first oxide layer 4 and the first polysilicon layer 3 are etched using the photoresist pattern as an etch mask to form an oxide layer pattern 4 ′ and a first gate electrode 3 ′, followed by a second oxide layer 5. ) Is applied over the entire structure; Anisotropically etching the second oxide film 5 to form oxide spacers 5 'on sidewalls of the oxide pattern 4' and the first gate electrode 3 '; Forming a second gate oxide film (6) on the silicon substrate (1) exposed by the anisotropic etching; Applying a second polysilicon film (7) on top of the entire structure; The second polysilicon layer 7 is etched back to expose the oxide pattern 4 'positioned on the first gate electrode 3' and the upper portion of the oxide spacer 5 '. Forming a gate electrode 7 '; Wet etching and removing the oxide spacer 5 '; And implanting impurity ions into the silicon substrate (1) located below the oxide spacer (5 ') by the wet etching.

Description

반도체 소자의 마스크 롬 제조방법Method for manufacturing mask ROM of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 마스크 롬의 회로도,1 is a circuit diagram of a general mask ROM,

제2도는 종래 방법에 따른 마스크 롬의 단면도,2 is a cross-sectional view of the mask ROM according to the conventional method,

제3A도 내지 제3E도는 본 발명에 따른 마스크 롬 제조 공정 단면도.3A through 3E are cross-sectional views of a mask ROM manufacturing process according to the present invention.

Claims (5)

반도체 소자의 마스크 롬 제조방법에 있어서, 실리콘 기판 상에 제1게이트 산화막, 제1폴리실리콘막, 제1절연막을 차례로 형성한 후 감광막 패턴을 상기 제1절연막 상에 형성하는 단계; 상기 감광막 패턴을 식각마스크로 상기 제1절연막, 제1폴리실리콘막을 식각하여 절연막 패턴과 제1게이트 전극을 형성한 후 2절연막을 전체구조 상부에 도포하는 단계; 상기 제2절연막을 비등방성 식각하여 상기 절연막 패턴 및 제1게이트전극의 측벽에 절연막 스페이서를 형성하는 단계; 상기 비등방성 식각에 의해 노출된 실리콘 기판 상에 제2게이트 산화막을 형성하는 단계; 전체구조 상부에 제2폴리실리콘막을 전체구조 상부에 도포하는 단계; 상기 제1게이트 전극 상에 위치한 절연막 패턴과 절연막 스페이서의 상부 일부가 노출되도록 상기 제2폴리실리콘막을 에치백(etch back)하여 제2게이트 전극을 형성하는 단계; 상기 절연막 스페이서를 습식식각하여 제거하는 단계; 및 상기 습식식각 하여 제거된 상기 절연막 스페이서 하부에 위치한 실리콘 기판에 불순물 이온을 주입하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 마스크 롬 제조방법.A method for manufacturing a mask ROM of a semiconductor device, the method comprising: forming a first gate oxide film, a first polysilicon film, and a first insulating film on a silicon substrate, and then forming a photoresist pattern on the first insulating film; Etching the first insulating layer and the first polysilicon layer using the photoresist pattern as an etch mask to form an insulating layer pattern and a first gate electrode, and then applying a second insulating layer over the entire structure; Anisotropically etching the second insulating layer to form insulating layer spacers on sidewalls of the insulating layer pattern and the first gate electrode; Forming a second gate oxide layer on the silicon substrate exposed by the anisotropic etching; Applying a second polysilicon film on the entire structure above the entire structure; Forming a second gate electrode by etching back the second polysilicon layer to expose an insulating layer pattern on the first gate electrode and an upper portion of the insulating layer spacer; Removing the insulating film spacer by wet etching; And implanting impurity ions into a silicon substrate disposed under the insulating spacer, which is removed by the wet etching. 제1항에 있어서, 상기 제1절연막의 두께는 1000∼2000A인 것을 특징으로 하는 반도체 소자의 마스크 롬 제조방법.The method of claim 1, wherein the first insulating layer has a thickness of 1000 to 2000 A. 3. 제1항에 있어서, 상기 제2절연막의 두께는 1500∼3500A인 것을 특징으로 하는 반도체 소자의 마스크 롬 제조방법.The method of claim 1, wherein the second insulating layer has a thickness of 1500 to 3500 A. 제1항에 있어서, 상기 제2폴리실리콘막의 두께는 상기 제1게이트 전극의 두께보다 더 두껍게 도포되는 것을 특징으로 하는 반도체 소자의 마스크 롬 제조방법.The method of claim 1, wherein a thickness of the second polysilicon layer is greater than a thickness of the first gate electrode. 제1항에 있어서, 상기 절연막 스페이서의 최대 폭은 0.1∼0.3㎛인 것을 특징으로 하는 반도체 소자의 마스크 롬 제조방법.The method of claim 1, wherein a maximum width of the insulating film spacer is 0.1 to 0.3 μm. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950062113A 1995-12-28 1995-12-28 A fabrication method of mask rom semiconductor device KR100219047B1 (en)

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KR1019950062113A KR100219047B1 (en) 1995-12-28 1995-12-28 A fabrication method of mask rom semiconductor device

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KR970054238A true KR970054238A (en) 1997-07-31
KR100219047B1 KR100219047B1 (en) 1999-09-01

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