KR960005782A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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Publication number
KR960005782A
KR960005782A KR1019940016092A KR19940016092A KR960005782A KR 960005782 A KR960005782 A KR 960005782A KR 1019940016092 A KR1019940016092 A KR 1019940016092A KR 19940016092 A KR19940016092 A KR 19940016092A KR 960005782 A KR960005782 A KR 960005782A
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KR
South Korea
Prior art keywords
contact hole
semiconductor device
forming
concentration impurity
gate electrode
Prior art date
Application number
KR1019940016092A
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Korean (ko)
Other versions
KR0134859B1 (en
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940016092A priority Critical patent/KR0134859B1/en
Publication of KR960005782A publication Critical patent/KR960005782A/en
Application granted granted Critical
Publication of KR0134859B1 publication Critical patent/KR0134859B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 불순물 이온주입영역과 게이트 전극을 동시에 접속하기 위한 콘택홀 제조시 질화막을 식각 정지층으로 하여 산화막 스페이서를 제거하여 설계여유도를 확보할 수 있는 반도체 소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and in the manufacture of a contact hole for simultaneously connecting an impurity ion implantation region and a gate electrode, an oxide spacer can be removed by using an nitride film as an etch stop layer to secure a design margin. A method for forming a contact hole in a semiconductor device.

Description

반도체 소자의 콘택홀 형성 방법Contact hole formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2a도 내지 제2d도는 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to the present invention.

Claims (2)

설계여유도를 확보하기 위한 반도체 소자의 콘택홀 형성방법에 있어서, 실리콘 기판(11)상에 게이트 산화막(12) 및 게이트 전극(13)을 형성한 다음 전체구조 상부에 질화막(14)을 얇게 증착하는 단계와, 상기 단계로부터 저농도 불순물 이온을 주입하여 저농도 불순물 영역(15)을 형성한 후 산화막 스페이서(16)를 형성하고, 이후 고농도 불순물 이온을 주입하여 고농도 불순물 영역(17)을 형성하는 단계와, 상기 단계로부터 전체구조 상부에 절연층(18)을 형성한 다음 상기 질화막(14)을 식각 정지층으로 한 사진식각법으로 불순물 영역(15 및 17)과 게이트 전극(13)의 상부가 일부 노출되는 콘택홀(19)을 형성하는 단계와, 상기 단계로부터 산화막 스페이서(16)를 습식식각으로 제거하고, 반응성 이온식각으로 불순물 영역(15 및 17)과 게이트 전극(13) 상부에 노출된 질화막(14)을 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.In the method of forming a contact hole of a semiconductor device to secure design margin, a gate oxide film 12 and a gate electrode 13 are formed on a silicon substrate 11 and then a thin nitride film 14 is deposited on the entire structure. And implanting low concentration impurity ions from the above step to form the low concentration impurity region 15, and then forming oxide spacers 16, and then implanting high concentration impurity ions to form the high concentration impurity region 17; After the insulating layer 18 is formed over the entire structure from the above step, the impurity regions 15 and 17 and the upper portion of the gate electrode 13 are partially exposed by photolithography using the nitride film 14 as an etch stop layer. Forming a contact hole 19, and removing the oxide spacer 16 by wet etching, and exposing the impurity regions 15 and 17 and the upper portion of the gate electrode 13 by reactive ion etching. The method of forming contact holes of a semiconductor device, characterized in that comprising the step of removing the film 14. 제1항에 있어서, 상기 반응성 이온식각은 CF4와 O2개스를 사용하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein the reactive ion etching comprises CF 4 and O 2 gas. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940016092A 1994-07-06 1994-07-06 Fabrication method of contact hole in semiconductor device KR0134859B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940016092A KR0134859B1 (en) 1994-07-06 1994-07-06 Fabrication method of contact hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940016092A KR0134859B1 (en) 1994-07-06 1994-07-06 Fabrication method of contact hole in semiconductor device

Publications (2)

Publication Number Publication Date
KR960005782A true KR960005782A (en) 1996-02-23
KR0134859B1 KR0134859B1 (en) 1998-04-20

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ID=19387336

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940016092A KR0134859B1 (en) 1994-07-06 1994-07-06 Fabrication method of contact hole in semiconductor device

Country Status (1)

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KR (1) KR0134859B1 (en)

Also Published As

Publication number Publication date
KR0134859B1 (en) 1998-04-20

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